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Title:
METHODS AND SYSTEMS FOR COMBINED LOSSLESS AND LOSSY CODING
Document Type and Number:
WIPO Patent Application WO/2022/047129
Kind Code:
A1
Abstract:
A decoder includes circuitry configured to receive a bitstream, identify, in the bitstream, a current frame, wherein the current frame includes a first region, detect, in the bitstream, an indication that the first region is encoded according to a lossless encoding protocol, and decode the current frame, wherein decoding the current frame further comprises decoding the first region using a lossless decoding protocol.

Inventors:
FURHT BORIVOJE (US)
KALVA HARI (US)
ADZIC VELIBOR (US)
Application Number:
PCT/US2021/047902
Publication Date:
March 03, 2022
Filing Date:
August 27, 2021
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
OP SOLUTIONS LLC (US)
International Classes:
H04N7/12
Foreign References:
US20130077696A12013-03-28
US20160165248A12016-06-09
US20190174141A12019-06-06
US20170111656A12017-04-20
US20130003838A12013-01-03
Attorney, Agent or Firm:
DRAYTON, Micah (US)
Download PDF:
Claims:
WHAT IS CLAIMED IS:

1. A decoder, the decoder comprising circuitry configured to: receive a bitstream; identify, in the bitstream, a current frame, wherein the current frame includes a first region; detect, in the bitstream, an indication that the first region is encoded according to a lossless encoding protocol; and decode the current frame, wherein decoding the current frame further comprises decoding the first region using a lossless decoding protocol.

2. The decoder of claim 1, wherein: the bitstream further includes a region header corresponding to the first region; and detecting further comprises detecting the indication that the first region is encoded according to a lossless encoding protocol in the region header.

3. The decoder of claim 2, wherein the region header is explicitly included in data corresponding to the current frame.

4. The decoder of claim 1, wherein the first region forms part of a quadtree plus binary decision tree.

5. The decoder of claim 1, wherein the first region includes a coding tree unit.

6. The decoder of claim 1, wherein the first region includes a coding unit.

7. The decoder of claim 1, wherein the first region includes a prediction unit.

8. The decoder of claim 1, wherein the first region includes the entirety of the frame.

9. The decoder of claim 1, wherein the first region includes a slice.

10. The decoder of claim 1, wherein the first region includes a tile.

11. The decoder of claim 1, wherein: the current frame further comprises a second region.

12. The decoder of claim 1, wherein the decoder is further configured to: detect that the second region is encoded according to a lossy encoding protocol; and decode the second region according to a lossy decoding protocol corresponding to the lossy encoding protocol.

13. The decoder of claim 12, wherein: the bitstream further includes a region header corresponding to the second region; and the decoder is further configured to detect the indication that the second region is encoded according to a lossy encoding protocol in the region header.

14. The decoder of claim 13, wherein the region header is explicitly included in data corresponding to the current frame.

15. The decoder of claim 13, wherein the region header is included by reference to an identifier of a region header corresponding to a third region.

16. The decoder of claim 1, wherein the decoder is further configured to decode the first region using a first processor thread; and decode the second region element using a second processor thread.

17. The decoder of claim 2, wherein the first region is included by reference to an identifier of a region header corresponding to a third region.

18. The decoder of claim 1, wherein the second region forms part of a quadtree plus binary decision tree.

19. The decoder of claim 1, wherein the second region includes a coding tree unit.

20. The decoder of claim 1, wherein the second region includes a coding unit.

21. The decoder of claim 1, wherein the second region includes a prediction unit.

22. The decoder of claim 1, further comprising: an entropy decoder processor configured to receive the bit stream and decode the bitstream into quantized coefficients; an inverse quantization and inverse transformation processor configured to process the quantized coefficients including performing an inverse discrete cosine; a deblocking filter; a frame buffer; and an intra prediction processor.

23. A method, the method comprising: receiving, by a decoder, a bitstream; identifying, by the decoder and in the bitstream, a current frame, wherein the current frame includes a first region; detecting, by the decoder and in the bitstream, an indication that the first region is encoded according to a lossless encoding protocol; and decoding the current frame, wherein decoding the current frame further comprises decoding the first region using a lossless decoding protocol.

24. The method of claim 23, wherein: the bitstream further includes a region header corresponding to the first region; and detecting further comprises detecting the indication that the first region is encoded according to a lossless encoding protocol in the region header.

25. The method of claim 25, wherein the region header is explicitly included in data corresponding to the current frame.

26. The method of claim 23, wherein the first region forms part of a quadtree plus binary decision tree.

27. The method of claim 23, wherein the first region includes a coding tree unit.

28. The method of claim 23, wherein the first region includes a coding unit.

29. The method of claim 23, wherein the first region includes a prediction unit.

30. The method of claim 23, wherein the first region includes the entirety of the frame.

31. The method of claim 23, wherein the first region includes a slice.

32. The method of claim 23, wherein the first region includes a tile.

33. The method of claim 23, wherein: the current frame further comprises a second region.

34. The method of claim 23, wherein the decoder is further configured to: detect that the second region is encoded according to a lossy encoding protocol; and decode the second region according to a lossy decoding protocol corresponding to the lossy encoding protocol.

35. The method of claim 34, wherein: the bitstream further includes a region header corresponding to the second region; and the decoder is further configured to detect the indication that the second region is encoded according to a lossy encoding protocol in the region header.

36. The method of claim 35, wherein the region header is explicitly included in data corresponding to the current frame.

37. The method of claim 35, wherein the region header is included by reference to an identifier of a region header corresponding to a third region.

38. The method of claim 23, wherein the decoder is further configured to decode the first region using a first processor thread; and decode the second region element using a second processor thread.

39. The method of claim 23, wherein the first region is included by reference to an identifier of a region header corresponding to a third region. 40. The method of claim 23, wherein the second region forms part of a quadtree plus binary decision tree.

41. The method of claim 23, wherein the second region includes a coding tree unit.

42. The method of claim 23, wherein the second region includes a coding unit.

43. The method of claim 23, wherein the second region includes a prediction unit. 44. The method of claim 23, wherein the decoder further comprises: an entropy decoder processor configured to receive the bit stream and decode the bitstream into quantized coefficients; an inverse quantization and inverse transformation processor configured to process the quantized coefficients including performing an inverse discrete cosine; a deblocking filter; a frame buffer; and an intra prediction processor.

Description:
METHODS AND SYSTEMS FOR COMBINED LOSSLESS AND LOSSY CODING

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority of U.S. Provisional Application Serial No. 63/071,574, filed on September 3, 2020, and entitled “METHODS AND SYSTEMS FOR COMBINED LOSSLESS AND LOSSY CODING,” which is incorporated by reference herein in its entirety.

FIELD OF THE INVENTION

The present invention generally relates to the field of video compression. In particular, the present invention is directed to methods and systems for combined lossless and lossy coding.

BACKGROUND

A video codec can include an electronic circuit or software that compresses or decompresses digital video. It can convert uncompressed video to a compressed format or vice versa. In the context of video compression, a device that compresses video (and/or performs some function thereof) can typically be called an encoder, and a device that decompresses video (and/or performs some function thereof) can be called a decoder.

A format of the compressed data can conform to a standard video compression specification. The compression can be lossy in that the compressed video lacks some information present in the original video. A consequence of this can include that decompressed video can have lower quality than the original uncompressed video because there is insufficient information to accurately reconstruct the original video.

There can be complex relationships between the video quality, the amount of data used to represent the video (e.g., determined by the bit rate), the complexity of the encoding and decoding algorithms, sensitivity to data losses and errors, ease of editing, random access, end-to- end delay (e.g., latency), and the like.

Motion compensation can include an approach to predict a video frame or a portion thereof given a reference frame, such as previous and/or future frames, by accounting for motion of the camera and/or objects in the video. It can be employed in the encoding and decoding of video data for video compression, for example in the encoding and decoding using the Motion Picture Experts Group (MPEG)'s advanced video coding (AVC) standard (also referred to as H.264). Motion compensation can describe a picture in terms of the transformation of a reference picture to the current picture. The reference picture can be previous in time when compared to the current picture, from the future when compared to the current picture. When images can be accurately synthesized from previously transmitted and/or stored images, compression efficiency can be improved.

SUMMARY OF THE DISCLOSURE

In an aspect, a decoder including circuitry is configured to receive a bitstream, identify, in the bitstream, a current frame, wherein the current frame includes a first region, detect, in the bitstream, an indication that the first region is encoded according to a lossless encoding protocol, and decode the current frame, wherein decoding the current frame further comprises decoding the first region using a lossless decoding protocol.

In another aspect, a method includes receiving, by a decoder, a bitstream, identifying, by the decoder and in the bitstream, a current frame, wherein the current frame includes a first region, detecting, by the decoder and in the bitstream, an indication that the first region is encoded according to a lossless encoding protocol, and decoding the current frame, wherein decoding the current frame further comprises decoding the first region using a lossless decoding protocol.

The details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims.

DESCRIPTION OF DRAWINGS

For the purpose of illustrating the invention, the drawings show aspects of one or more embodiments of the invention. However, it should be understood that the present invention is not limited to the precise arrangements and instrumentalities shown in the drawings, wherein:

FIG. 1, is a block diagram illustrating an exemplary embodiment of a frame;

FIG. 2 is a block diagram illustrating an exemplary embodiment of a frame having a plurality of sub-pictures;

FIG. 3 is a block diagram illustrating an exemplary embodiment of a frame having a plurality of slices, tiles, and CTUs;

FIG. 4 is a block diagram illustrating an exemplary embodiment of a frame having a plurality of slices, tiles, and CTUs; FIG. 5 is a block diagram illustrating an exemplary embodiment of a frame having a plurality of slices, tiles, and CTUs;

FIG. 6 is a block diagram illustrating an exemplary embodiment of a frame having a plurality of slices, tiles, and CTUs;

FIG. 7 is an illustration of an exemplary embodiment of a frame having two sub-pictures;

FIG. 8 is a process flow diagram illustrating an example process for decoding a video according to some implementations of the current subject matter;

FIG. 9 is a system block diagram illustrating an example decoder capable of decoding a bit stream according to some implementations of the current subject matter;

FIG. 10 is a process flow diagram illustrating an example process of encoding a video according to some implementations of the current subject matter; and

FIG. 11 is a block diagram of a computing system that can be used to implement any one or more of the methodologies disclosed herein and any one or more portions thereof.

The drawings are not necessarily to scale and may be illustrated by phantom lines, diagrammatic representations, and fragmentary views. In certain instances, details that are not necessary for an understanding of the embodiments or that render other details difficult to perceive may have been omitted. Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

In traditional video coding systems, video sequence is divided into groups-of-pictures (GOP). Each GOP is self-contained in the sense of temporal and spatial prediction. Usually, first picture in the group is used as a reference picture for the subsequent pictures. Temporal and spatial relationships between the pictures allow for the very efficient compression using predictive coding.

Past coding systems have typically operated using lossy coding, in which some information from an encoded frame is omitted during the encoding process and is not recovered during decoding. Such lossy processes may sacrifice a certain degree of detail and/or resolution in decoded frames and/or video pictures to achieve higher degrees of efficiency, for instance and without limitation by reducing quantities of data transmitted in a bit stream from an encoder to a decoder, processing time and/or memory resources used to encode and/or decode a frame or group of pictures, or the like. An alternative approach to the above process may include lossless encoding, wherein a frame is encoded and decoded with no or negligible loss of information; this may result in greater resolution and/or other detail in an output frame and/or video picture. However, while lossless encoding and decoding may occasionally be more efficient for certain kinds of image processing as noted in further detail below, lossless encoding can also be very expensive in terms of memory resources and processing times. This is particularly apparent in ultra high definition (UHD) video coding, in which a picture or image size may go up to 8K x 4K (7680x4320); a big picture size may pose great challenge for chip and/or module design. One reason for this is that the UHD requires a bigger search range in motion estimation and on-chip or other processing memory for buffering reference blocks for motion estimation and compensation. UHD processing may even present challenges for lossy encoding and decoding owing to the greater picture sizes involved.

Embodiments disclosed herein enable more efficient signaling, decoding, and encoding using combined lossless and lossy video compression coding. In an embodiment, a picture may first be divided into sub-pictures based on quality and computation requirements. An encoder may create as many sub-pictures as there are processing cores (or hardware threads) on a CPU or other device, circuit, or component that is performing encoding and/or decoding of pictures and/or GOP. Since each sub-picture may be independently coded, this form of task partitioning may allow for efficient encoding and/or decoding by using all available computing resources effectively. Moreover, lossless encoding may furnish better compression than lossy coding that uses transform and quantization, for instance for certain sub-pictures of an overall frame; as a result, combined lossless and lossy coding may result in superior performance to lossless coding alone.

Referring now to FIG. 1, an exemplary embodiment of a current frame 100 is illustrated. Current frame 100 may include one or more regions 104, defined as any contiguous set of pixels on current frame 100, including the entirety of current frame 100 and/or any sub-region of current frame 100, including without limitation a sub-picture, tile, slice, coding tree unit (CTU), coding unit (CU), and/or prediction unit.

Referring now to FIG. 2, an exemplary embodiment of a current frame divided into a plurality of sub-pictures is illustrated. Sub-pictures may include any portion of current frame smaller than current frame; sub-pictures of current frame may combine to cover all of current frame. Although FIG. 2 illustrates exemplary current frames divided into two or four subpictures, persons skilled in the art having viewed the entirety of this disclosure will appreciate that any number of sub-pictures may be used as appropriate for resolution, efficiency, or any other consideration.

Still referring to FIG. 2, a sub-picture may have any suitable shape, including without limitation a square and/or rectangular shape, a shape defined by combination of two or more blocks having square and/or rectangular shapes, or the like. Each block may be identified and/or signaled using coordinates of one or more portions and/or features of a block, where coordinates may indicate number of pixels across frame and/or picture as measured from one or more comers and/or sides of the frame and/or picture. For instance, and without limitation, a block may be identified using coordinates of vertices, such as two x coordinates and two y coordinates for identification of a rectangular block. A sub-picture and/or portion thereof may alternatively or additionally be identified using any suitable geometric description of points, lines, and/or shapes, including without limitation geometric partition using one or more line segments, as defined by linear equations or mathematically equivalent expressions such as line-segment endpoints, using one or more curved edges such as without limitation defined using exponential or other curves, or the like.

Referring now to FIG. 3, a picture such as current frame 100 may be divided into one or more tile columns. A “tile,” as used in this disclosure is a sequence of CTUs that covers a rectangular region of a picture. A CTU in a tile may be scanned in raster scan order within that tile. A picture, such as without limitation current frame 100, may be alternatively or additionally divided into slices. A “slice,” as used in this disclosure, is a region of a picture consisting of an integer number of complete tiles or an integer number of consecutive complete CTU rows within a tile of a picture. A slice may be (i) a raster-scan slice and/or (ii) a rectangular slice. A rasterscan slice contains a sequence of complete tiles in a tile raster scan of a picture. A rectangular slice contains either a number of complete tiles that collectively form a rectangular region of a picture, such as without limitation current frame 100, or a number of consecutive complete CTU rows of one tile that collectively form a rectangular region of the picture. FIG. 3 illustrates an exemplary embodiment of a picture, such as current picture 100, with raster-scan slice partitioning; the exemplary picture includes 18x12 CTUs and is partitioned into 12 tiles and 3 raster-scan slices. FIG. 4 illustrates an exemplary embodiment of a picture, such as without limitation current picture 100, with rectangular slice partitioning; the exemplary picture with 18x12 CTUs is partitioned into 24 tiles and 9 rectangular slices. In an embodiment, lossless and/or lossy coding may be performed, for instance by an encoder and/or decoder as described in further detail below, by identifying regions, such as regions having high degrees of motion, to be subject to lossless coding, with “1”, and regions, such as regions with low or no motion, that are to be encoded and/or decoded with lossy coding with “0”, as shown without limitation in FIGS. 5 and 6. Some tiles and/or other regions may be fully coded using lossless coding, while others may be entirely coded using lossy coding. In Figure 5, an entire slice consisting of two tiles in the upper left is illustrated as coded using lossy coding, while a single tile of a slice adjoining the above-described slice is illustrated as being coded using lossless coding with other tiles thereof are coded with lossy coding. A third slice in FIG. 5 is shown as having three tiles coded with lossy coding, one tile entirely coded with lossless coding, and one tile having six lossless CTUs and twelve lossy CTUs. As a further non-limiting example, FIG. 6 shows an upper row of three slices coded entirely with lossy coding, a second row showing a slice having four individually coded lossy tiles, a slice having two individually coded lossless tiles and two individually coded lossy tiles, and two individually coded lossy tiles, and a central slice in which individual CTUs are coded as lossy or lossless, creating tiles in which some coding is lossy and other coding is lossless.

With continued reference to FIG. 6, regions may be coded separately from one another. For instance, and without limitation, a first region, including without limitation a first region of a plurality of regions may be encoded and/or decoded using a first processor thread and a second region element may be decoded using a second processor thread. A “processor thread” as used herein may include any processor core and/or other hardware element capable of executing a thread of a multithreaded parallel process that may occur to persons skilled in the art upon reviewing the entirety of this disclosure. In an embodiment, where each region is independently coded, this form of task partitioning may allow for efficient encoding by using all available compute resources effectively

Still referring to FIG. 6 lossless coding may be selectively applied to a subset of blocks of a picture where it is desirable for one or more reasons described above for a source video to be preserved without any loss. As a non-limiting example, selection of a subset of a picture for lossless coding may be done for reasons of coding efficiency. In such cases, lossless coding mode decision may be made after evaluating a rate-distortion (RD) cost of coding a CTU in lossy and lossless modes. In certain use cases, portions of a video may be selected by the user to be encoded in lossless mode for reasons dictated by applications. A non-limiting example may include situations where portion of a frame where source quality retention is desirable for a user. When such user selections are made, an entire region may be marked as using lossless coding without performing any RD analysis.

Alternatively or additionally, and further referring to FIG. 6, a region may be identified by an encoder and/or other hardware and/or software component and/or process as an area, region and/or subdivision of a picture in which greater amounts of motion are detected and/or present; such regions may be identified considered significant and coded using lossless coding, while regions with little or no motion may be coded using lossy coding. An example is show in FIG. 7, where a picture 700 is divided in two regions: a first region 704 with motion, and second region 708 with no motion. As noted above, in some cases lossless coding may give better compression than lossy coding with that uses transform and quantization.

Referring again to FIG. 6, a picture may be divided into sub-pictures, slices, and tiles. Blocks (CTUs) may be coding units that may be coded in intra or inter coding mode. A region may include a single CTU and/or plurality of CTUs. In an embodiment, each CTU in a subset of CTUs may signal whether lossless coding is used in the CTU; alternatively or additionally, a set of CTUs, such as without limitation a set of contiguously located CTUs may be signaled together. Lossless and/or lossy coding may be signaled in one or more headers provided to a bitstream. For instance, and without limitation, CTUs may be coded in lossless coding mode by signaling lossless and/or lossy coding mode in a CTU header. Selective use of lossless coding for a sub-set of blocks (CTUs) may alternatively or additionally be signaled at a higher-level syntactic unit. For example, a tile, slice, and/or sub-picture header may signal the use of lossless coding modes for all the CTUs in that syntactic unit. A sub-picture header may be either explicitly present or included by reference using a mechanism such as an identifier of another header such as a previously signaled picture header. An enablement flag indicating mixed lossy and lossless coding, such as without limitation a mixed lossy lossless flag, may be signaled in PPS. Lower level signaling may be at a slice and/or ctu level, for instance as illustrated in the following exemplary syntax: if(pps_mixed_lossy_lossless_enabled){ sh_slice_uses_loss_less_coding_flag;

}

As a non-limiting example, and continuing to refer to FIG. 6, data and/or logic within a sub-picture header, CTU header, and/or other header may include, without limitation, a first bit indicating whether lossless mode signaling is enabled, or in other words whether encoder and/or decoder should signal and/or receive a signal indicating whether lossless and/or lossy mode is being used for the relevant CTU, sub-picture, or the like. Data and/or logic within a sub-picture header, CTU header, and/or other header may include, without limitation, a second bit indicating lossless and/or lossy mode, where a lossless mode is a mode in which relevant CTU, sub-picture, or the like is encoded and decoded using a lossless encoding and decoding protocol as described above. The following is a non-limiting and illustrative example of logic and data that may be employed, for instance, where region is a sub-picture:

Sub _pi cture header { lossless mode signaling [1-bit] if(lossless_mode_signaling){ lossless mode [1 bit];

}

}

Still referring to FIG. 6, an encoder and/or decoder configured to perform processes described in this disclosure may be configured to signal and/or detect a lossless encoding protocol used, for instance using an identifier and/or bit corresponding to the lossless encoding protocol. Alternatively or additionally, encoder and/or decoder may be configured to operate a specific lossless encoding and decoding protocol, for instance as consistent with a given standard, release, or other approach to adopting uniform standard. There may be two or more standard protocols, selection of which may be signaled in a bitstream using a sufficient number of bits to encode the two or more potential selections.

With continued reference to FIG. 6, lossless coding protocol may include any protocol for lossless encoding of images, videos, frames, pictures, sub-pictures or the like. As a nonlimiting example, encoder and/or decoder may accomplish lossless coding is to bypass a transform coding stage and encode residual directly. This approach, which may be referred to in this disclosure as “transform skip residual coding,” may be accomplished by skipping transformation of a residual, as described in further detail below, from spatial into frequency domain by applying a transform from the family of discrete cosine transforms (DCTs), as performed for instance in some forms of block-based hybrid video coding. Lossless encoding and decoding may be performed according to one or more alternative processes and/or protocols, including without limitation processes and/or protocols as proposed at Core Experiment CE3-1 of JVET-Q00069 pertaining to rregular and TS residual coding (RRC, TSRC) for lossless coding, and modifications to RRC and TSRC for lossless and lossy operation modes, Core Experiment CE3-2 of JVET-Q0080, pertaining to enabling block differential pulse-code modulation (BDPCM) and high-level techniques for lossless coding, and the combination of BDPCM with different RRC/TSRC techniques, or the like.

Referring now to FIG. 8, a method 800 of combined lossless and lossy coding is illustrated. At step 805, a decoder receives a bitstream. At step 810, decoder identifies a current frame in bitstream.

At step 815, and still referring to FIG. 8, method includes detecting, in the bitstream, an indication that the first region is encoded according to a lossless encoding protocol. This may be implemented in any manner described above. Bitstream may include a region header corresponding to the first region. Detecting may include detecting the indication that the first region is encoded according to a lossless encoding protocol in the region header. Region header may be explicitly included in data corresponding to the current frame. First region may form part of a quadtree plus binary decision tree, a coding tree unit. First region may include a coding unit, a CTU, a prediction unit, the entirety of current frame, a slice, a tile, and/or any other region as described above. At step 820, and with further reference to FIG. 8, method 800 includes decoding the current frame, where decoding the current frame further includes decoding the first region using a lossless decoding protocol; this may be implemented, without limitation, as described above.

Still referring to FIG. 8, current frame may include a second region. Decoder may detect that second region is encoded according to a lossy or lossless encoding protocol, for instance and without limitation as described above. Decoder may decode second region according to a lossy decoding protocol corresponding to the lossy encoding protocol; decoder may alternatively decode second region according to a lossless encoding protocol. Bitstream may include a region header corresponding to the second region. Decoder may detect an indication that second region is encoded according to a lossy and/or lossless encoding protocol in region header. Region header may be explicitly included in data corresponding to current frame. Region header may be included by reference to an identifier of a region header corresponding to a third region. Decoder may be further configured to decode the first region using a first processor thread and decode the second region element using a second processor thread. Second region may be included by reference to an identifier of a region header corresponding to a third region. Second region may include any region suitable for use as first region. For instance, and without limitation, second region may form part of a quadtree plus binary decision tree. Second region may include a coding tree unit, a coding unit, a prediction unit, or the like.

Further referring to FIG. 8, decoder may include an entropy decoder processor configured to receive the bit stream and decode the bitstream into quantized coefficients, an inverse quantization and inverse transformation processor configured to process the quantized coefficients including performing an inverse discrete cosine, a deblocking filter, a frame buffer, and/or an intra prediction processor.

FIG. 9 is a system block diagram illustrating an example decoder 900 capable of decoding a bit stream 970 with adaptive cropping that can enable additional flexibility for the video encoder/decoder allowing bitrate savings in various use cases. The decoder 900 includes an entropy decoder processor 910, an inverse quantization and inverse transformation processor 920, a deblocking filter 930, a frame buffer 940, motion compensation processor 950 and intra prediction processor 960.

FIG. 9 is a system block diagram illustrating an example decoder 900 capable of decoding a bitstream 928 using combined lossy and lossless coding protocols. Decoder 900 may include an entropy decoder processor 904, an inverse quantization and inverse transformation processor 908, a deblocking filter 912, a frame buffer 916, a motion compensation processor 920 and/or an intra prediction processor 924.

In operation, and still referring to FIG. 9, bit stream 928 may be received by decoder 900 and input to entropy decoder processor 904, which may entropy decode portions of bit stream into quantized coefficients. Quantized coefficients may be provided to inverse quantization and inverse transformation processor 908, which may perform inverse quantization and inverse transformation to create a residual signal, which may be added to an output of motion compensation processor 920 or intra prediction processor 924 according to a processing mode. An output of the motion compensation processor 920 and intra prediction processor 924 may include a block prediction based on a previously decoded block. A sum of prediction and residual may be processed by deblocking filter 912 and stored in a frame buffer 916.

With continued reference to FIG. 9 decoder 900 may be designed and/or configured to perform any method, method step, or sequence of method steps in any embodiment described in this disclosure, in any order and with any degree of repetition. For instance, decoder 900 may be configured to perform a single step or sequence repeatedly until a desired or commanded outcome is achieved; repetition of a step or a sequence of steps may be performed iteratively and/or recursively using outputs of previous repetitions as inputs to subsequent repetitions, aggregating inputs and/or outputs of repetitions to produce an aggregate result, reduction or decrement of one or more variables such as global variables, and/or division of a larger processing task into a set of iteratively addressed smaller processing tasks. Decoder 900 may perform any step or sequence of steps as described in this disclosure in parallel, such as simultaneously and/or substantially simultaneously performing a step two or more times using two or more parallel threads, processor cores, or the like; division of tasks between parallel threads and/or processes may be performed according to any protocol suitable for division of tasks between iterations. Persons skilled in the art, upon reviewing the entirety of this disclosure, will be aware of various ways in which steps, sequences of steps, processing tasks, and/or data may be subdivided, shared, or otherwise dealt with using iteration, recursion, and/or parallel processing.

FIG. 10 is a system block diagram illustrating an exemplary embodiment of a video encoder 1000 capable of constructing a motion vector candidate list including adding a single global motion vector candidate to the motion vector candidate list. Example video encoder 1000 may receive an input video 1004, which may be initially segmented and/or dividing according to a processing scheme, such as a tree-structured macro block partitioning scheme (e.g., quad-tree plus binary tree). An example of a tree-structured macro block partitioning scheme may include partitioning a picture frame into large block elements called coding tree units (CTU). In some implementations, each CTU may be further partitioned one or more times into a number of subblocks called coding units (CU). A final result of this portioning may include a group of subblocks that may be called predictive units (PU). Transform units (TU) may also be utilized.

Still referring to FIG. 10, example video encoder 1000 may include an intra prediction processor 1012, a motion estimation / compensation processor 1012 (also referred to as an inter prediction processor) capable of constructing a motion vector candidate list including adding a single global motion vector candidate to the motion vector candidate list, a transform /quantization processor 1016, an inverse quantization / inverse transform processor 1020, an inloop filter 1024, a decoded picture buffer 1028, and/or an entropy coding processor 1032. Bit stream parameters may be input to entropy coding processor 1032 for inclusion in an output bit stream 1036.

In operation, and with continued reference to FIG. 10, for each block of a frame of input video 1004, whether to process block via intra picture prediction or using motion estimation / compensation may be determined. Block may be provided to intra prediction processor 1008 or motion estimation / compensation processor 1012. If block is to be processed via intra prediction, intra prediction processor 1008 may perform processing to output a predictor. If block is to be processed via motion estimation / compensation, motion estimation / compensation processor 1012 may perform processing including constructing a motion vector candidate list including adding a single global motion vector candidate to the motion vector candidate list, if applicable.

Still referring to FIG. 10, a residual may be formed by subtracting predictor from input video. Residual may be received by transform / quantization processor 1016, which may perform transformation processing (e.g., discrete cosine transform (DCT)) to produce coefficients, which may be quantized. Quantized coefficients and any associated signaling information may be provided to entropy coding processor 1032 for entropy encoding and inclusion in an output bit stream 1036. Entropy encoding processor 1032 may support encoding of signaling information related to encoding a current block. In addition, quantized coefficients may be provided to inverse quantization / inverse transformation processor 1020, which may reproduce pixels, which may be combined with predictor and processed by in loop filter 1024, an output of which may be stored in decoded picture buffer 1028 for use by motion estimation / compensation processor 1012 that is capable of constructing a motion vector candidate list including adding a single global motion vector candidate to the motion vector candidate list.

Further referencing FIG. 10, although a few variations have been described in detail above, other modifications or additions are possible. For example, in some implementations, current blocks may include any symmetric blocks (8x8, 16x16, 32x32, 64x64, 128 x 128, and the like) as well as any asymmetric block (8x4, 16x8, and the like).

In some implementations, and still referring to FIG. 10, a quadtree plus binary decision tree (QTBT) may be implemented. In QTBT, at a Coding Tree Unit level, partition parameters of QTBT may be dynamically derived to adapt to local characteristics without transmitting any overhead. Subsequently, at a Coding Unit level, a joint-classifier decision tree structure may eliminate unnecessary iterations and control risk of false prediction. In some implementations, LTR frame block update mode may be available as an additional option available at every leaf node of a QTBT.

In some implementations, and still referring to FIG. 10, additional syntax elements may be signaled at different hierarchy levels of a bitstream. For example, a flag may be enabled for an entire sequence by including an enable flag coded in a Sequence Parameter Set (SPS). Further, a CTU flag may be coded at a coding tree unit (CTU) level.

With continued reference to FIG. 10, non-transitory computer program products (i.e., physically embodied computer program products) may store instructions, which when executed by one or more data processors of one or more computing systems, causes at least one data processor to perform operations, and/or steps thereof described in this disclosure, including without limitation any operations described above 400 and/or encoder 1000 may be configured to perform. Similarly, computer systems are also described that may include one or more data processors and memory coupled to the one or more data processors. The memory may temporarily or permanently store instructions that cause at least one processor to perform one or more of the operations described herein. In addition, methods can be implemented by one or more data processors either within a single computing system or distributed among two or more computing systems. Such computing systems can be connected and can exchange data and/or commands or other instructions or the like via one or more connections, including a connection over a network (e.g. the Internet, a wireless wide area network, a local area network, a wide area network, a wired network, or the like), via a direct connection between one or more of the multiple computing systems, or the like.

In an embodiment, a decoder includes circuitry configured to receive a bitstream, identify, in the bitstream, a current frame, wherein the current frame includes a first region, detect, in the bitstream, an indication that the first region is encoded according to a lossless encoding protocol, and decode the current frame, wherein decoding the current frame further comprises decoding the first region using a lossless decoding protocol.

In an embodiment, the bitstream may include a region header corresponding to the first region, and detecting may include detecting the indication that the first region is encoded according to a lossless encoding protocol in the region header. Region header may be explicitly included in data corresponding to the current frame. First region may form part of a quadtree plus binary decision tree. First region may include a coding tree unit. First region may include a coding unit. The first region may include a prediction unit. The first region may include the entirety of the frame. The first region may include a slice. First region may include a tile. The current frame may include a second region. The decoder may be further configured to detect that the second region is encoded according to a lossy encoding protocol and decode the second region according to a lossy decoding protocol corresponding to the lossy encoding protocol. The bitstream may include a region header corresponding to the second region and the decoder may be further configured to detect the indication that the second region is encoded according to a lossy encoding protocol in the region header. The region header may be explicitly included in data corresponding to the current frame. The region header may be included by reference to an identifier of a region header corresponding to a third region. The decoder may be further configured to decode the first region using a first processor thread and decode the second region element using a second processor thread. The first region may be included by reference to an identifier of a region header corresponding to a third region. The second region may form part of a quadtree plus binary decision tree. The second region may include a coding tree unit. The second region may include a coding unit. The second region may include a prediction unit. The decoder may include an entropy decoder processor configured to receive the bit stream and decode the bitstream into quantized coefficients, an inverse quantization and inverse transformation processor configured to process the quantized coefficients including performing an inverse discrete cosine, a deblocking filter, a frame buffer, and an intra prediction processor.

In an embodiment, a method includes receiving, by a decoder, a bitstream, identifying, by the decoder and in the bitstream, a current frame, wherein the current frame includes a first region, detecting, by the decoder and in the bitstream, an indication that the first region is encoded according to a lossless encoding protocol, and decoding the current frame, wherein decoding the current frame further comprises decoding the first region using a lossless decoding protocol.

The bitstream may include a region header corresponding to the first region and detecting may include detecting the indication that the first region is encoded according to a lossless encoding protocol in the region header. Region header may be explicitly included in data corresponding to the current frame. First region may form part of a quadtree plus binary decision tree. First region may include a coding tree unit. First region may include a coding unit. First region may include a prediction unit. First region may include the entirety of the frame. First region may include a slice. First region may include a tile. Current frame may include a second region. Decoder may be further configured to detect that the second region is encoded according to a lossy encoding protocol and decode the second region according to a lossy decoding protocol corresponding to the lossy encoding protocol. The bitstream may include a region header corresponding to the second region, and the decoder may be further configured to detect the indication that the second region is encoded according to a lossy encoding protocol in the region header. Region header may be explicitly included in data corresponding to the current frame. Region header is included by reference to an identifier of a region header corresponding to a third region. The decoder may be further configured to decode the first region using a first processor thread and decode the second region element using a second processor thread. The first region may be included by reference to an identifier of a region header corresponding to a third region. The second region may form part of a quadtree plus binary decision tree. The second region may include a coding tree unit. The second region may include a coding unit. The second region may include a prediction unit. The decoder may include an entropy decoder processor configured to receive the bit stream and decode the bitstream into quantized coefficients, an inverse quantization and inverse transformation processor configured to process the quantized coefficients including performing an inverse discrete cosine, a deblocking filter, a frame buffer, and an intra prediction processor.

It is to be noted that any one or more of the aspects and embodiments described herein may be conveniently implemented using one or more machines (e.g., one or more computing devices that are utilized as a user computing device for an electronic document, one or more server devices, such as a document server, etc.) programmed according to the teachings of the present specification, as will be apparent to those of ordinary skill in the computer art. Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will be apparent to those of ordinary skill in the software art. Aspects and implementations discussed above employing software and/or software modules may also include appropriate hardware for assisting in the implementation of the machine executable instructions of the software and/or software module.

Such software may be a computer program product that employs a machine-readable storage medium. A machine-readable storage medium may be any medium that is capable of storing and/or encoding a sequence of instructions for execution by a machine (e.g., a computing device) and that causes the machine to perform any one of the methodologies and/or embodiments described herein. Examples of a machine-readable storage medium include, but are not limited to, a magnetic disk, an optical disc (e.g., CD, CD-R, DVD, DVD-R, etc.), a magnetooptical disk, a read-only memory “ROM” device, a random access memory “RAM” device, a magnetic card, an optical card, a solid-state memory device, an EPROM, an EEPROM, and any combinations thereof. A machine-readable medium, as used herein, is intended to include a single medium as well as a collection of physically separate media, such as, for example, a collection of compact discs or one or more hard disk drives in combination with a computer memory. As used herein, a machine-readable storage medium does not include transitory forms of signal transmission.

Such software may also include information (e.g., data) carried as a data signal on a data carrier, such as a carrier wave. For example, machine-executable information may be included as a data-carrying signal embodied in a data carrier in which the signal encodes a sequence of instruction, or portion thereof, for execution by a machine (e.g., a computing device) and any related information (e.g., data structures and data) that causes the machine to perform any one of the methodologies and/or embodiments described herein. Examples of a computing device include, but are not limited to, an electronic book reading device, a computer workstation, a terminal computer, a server computer, a handheld device (e.g., a tablet computer, a smartphone, etc.), a web appliance, a network router, a network switch, a network bridge, any machine capable of executing a sequence of instructions that specify an action to be taken by that machine, and any combinations thereof. In one example, a computing device may include and/or be included in a kiosk.

FIG. 11 shows a diagrammatic representation of one embodiment of a computing device in the exemplary form of a computer system 1100 within which a set of instructions for causing a control system to perform any one or more of the aspects and/or methodologies of the present disclosure may be executed. It is also contemplated that multiple computing devices may be utilized to implement a specially configured set of instructions for causing one or more of the devices to perform any one or more of the aspects and/or methodologies of the present disclosure. Computer system 1100 includes a processor 1104 and a memory 1108 that communicate with each other, and with other components, via a bus 1112. Bus 1112 may include any of several types of bus structures including, but not limited to, a memory bus, a memory controller, a peripheral bus, a local bus, and any combinations thereof, using any of a variety of bus architectures.

Processor 1104 may include any suitable processor, such as without limitation a processor incorporating logical circuitry for performing arithmetic and logical operations, such as an arithmetic and logic unit (ALU), which may be regulated with a state machine and directed by operational inputs from memory and/or sensors; processor 1104 may be organized according to Von Neumann and/or Harvard architecture as a non-limiting example. Processor 1104 may include, incorporate, and/or be incorporated in, without limitation, a microcontroller, microprocessor, digital signal processor (DSP), Field Programmable Gate Array (FPGA), Complex Programmable Logic Device (CPLD), Graphical Processing Unit (GPU), general purpose GPU, Tensor Processing Unit (TPU), analog or mixed signal processor, Trusted Platform Module (TPM), a floating point unit (FPU), and/or system on a chip (SoC).

Memory 1108 may include various components (e.g., machine-readable media) including, but not limited to, a random-access memory component, a read only component, and any combinations thereof. In one example, a basic input/output system 11111 (BIOS), including basic routines that help to transfer information between elements within computer system 1100, such as during start-up, may be stored in memory 1108. Memory 1108 may also include (e.g., stored on one or more machine-readable media) instructions (e.g., software) 1120 embodying any one or more of the aspects and/or methodologies of the present disclosure. In another example, memory 1108 may further include any number of program modules including, but not limited to, an operating system, one or more application programs, other program modules, program data, and any combinations thereof.

Computer system 1100 may also include a storage device 1124. Examples of a storage device (e.g., storage device 1124) include, but are not limited to, a hard disk drive, a magnetic disk drive, an optical disc drive in combination with an optical medium, a solid-state memory device, and any combinations thereof. Storage device 1124 may be connected to bus 1112 by an appropriate interface (not shown). Example interfaces include, but are not limited to, SCSI, advanced technology attachment (ATA), serial ATA, universal serial bus (USB), IEEE 1394 (FIREWIRE), and any combinations thereof. In one example, storage device 1124 (or one or more components thereof) may be removably interfaced with computer system 1100 (e.g., via an external port connector (not shown)). Particularly, storage device 1124 and an associated machine-readable medium 1128 may provide nonvolatile and/or volatile storage of machine- readable instructions, data structures, program modules, and/or other data for computer system 1100. In one example, software 1120 may reside, completely or partially, within machine- readable medium 1128. In another example, software 1120 may reside, completely or partially, within processor 1104.

Computer system 1100 may also include an input device 1132. In one example, a user of computer system 1100 may enter commands and/or other information into computer system 1100 via input device 1132. Examples of an input device 1132 include, but are not limited to, an alpha-numeric input device (e.g., a keyboard), a pointing device, a joystick, a gamepad, an audio input device (e.g., a microphone, a voice response system, etc.), a cursor control device (e.g., a mouse), a touchpad, an optical scanner, a video capture device (e.g., a still camera, a video camera), a touchscreen, and any combinations thereof. Input device 1132 may be interfaced to bus 1112 via any of a variety of interfaces (not shown) including, but not limited to, a serial interface, a parallel interface, a game port, a USB interface, a FIREWIRE interface, a direct interface to bus 1112, and any combinations thereof. Input device 1132 may include a touch screen interface that may be a part of or separate from display 1136, discussed further below. Input device 1132 may be utilized as a user selection device for selecting one or more graphical representations in a graphical interface as described above.

A user may also input commands and/or other information to computer system 1100 via storage device 1124 (e.g., a removable disk drive, a flash drive, etc.) and/or network interface device 1140. A network interface device, such as network interface device 1140, may be utilized for connecting computer system 1100 to one or more of a variety of networks, such as network 1144, and one or more remote devices 1148 connected thereto. Examples of a network interface device include, but are not limited to, a network interface card (e.g., a mobile network interface card, a LAN card), a modem, and any combination thereof. Examples of a network include, but are not limited to, a wide area network (e.g., the Internet, an enterprise network), a local area network (e.g., a network associated with an office, a building, a campus or other relatively small geographic space), a telephone network, a data network associated with a telephone/voice provider e.g., a mobile communications provider data and/or voice network), a direct connection between two computing devices, and any combinations thereof. A network, such as network 1144, may employ a wired and/or a wireless mode of communication. In general, any network topology may be used. Information (e.g., data, software 1120, etc.) may be communicated to and/or from computer system 1100 via network interface device 1140.

Computer system 1100 may further include a video display adapter 1152 for communicating a displayable image to a display device, such as display device 1136. Examples of a display device include, but are not limited to, a liquid crystal display (LCD), a cathode ray tube (CRT), a plasma display, a light emitting diode (LED) display, and any combinations thereof. Display adapter 1152 and display device 1136 may be utilized in combination with processor 1104 to provide graphical representations of aspects of the present disclosure. In addition to a display device, computer system 1100 may include one or more other peripheral output devices including, but not limited to, an audio speaker, a printer, and any combinations thereof. Such peripheral output devices may be connected to bus 1112 via a peripheral interface 1156. Examples of a peripheral interface include, but are not limited to, a serial port, a USB connection, a FIREWIRE connection, a parallel connection, and any combinations thereof.

The foregoing has been a detailed description of illustrative embodiments of the invention. Various modifications and additions can be made without departing from the spirit and scope of this invention. Features of each of the various embodiments described above may be combined with features of other described embodiments as appropriate in order to provide a multiplicity of feature combinations in associated new embodiments. Furthermore, while the foregoing describes a number of separate embodiments, what has been described herein is merely illustrative of the application of the principles of the present invention. Additionally, although particular methods herein may be illustrated and/or described as being performed in a specific order, the ordering is highly variable within ordinary skill to achieve methods, systems, and software according to the present disclosure. Accordingly, this description is meant to be taken only by way of example, and not to otherwise limit the scope of this invention.

Exemplary embodiments have been disclosed above and illustrated in the accompanying drawings. It will be understood by those skilled in the art that various changes, omissions and additions may be made to that which is specifically disclosed herein without departing from the spirit and scope of the present invention.