BACKGROUND

[0001] The present invention relates to microfluidic chips, and more specifically, to microfluidic chips comprising thin substrates and/or a high density of vias.

[0002] Extensive and growing interest in lab-on-a-chip ("LOC”) technologies is evident from the tens of thousands of currently available in literature from close-system microfluidic publications alone. Such a broad interest in microfluidic technologies is representative of their many advantages over traditional laboratory methods, such as the ability to carry out separation and detection with high resolution and sensitivity, need for only very small quantities of sample and reagent, small footprint of the analytical devices these chips contain, low cost of manufacture, and short time of analysis.

[0003] With such great potential benefits, a number of material options and techniques have been explored to integrate microfluidic features and devices to separate, detect, and manipulate biological analytes. For microfluidic applications requiring high-density parallelization, biological samples and other fluids introduced into a silicon chip must have exit points, or fluidic outlets, at a high packing density to collect material. When fluidic vias are integrated at low density, structured glass (glass with holes) can be bonded to silicon as a last process step or defined in thermoplastics; however, at high density, wherein hundreds or thousands of vias are required at small sizes (e.g., 50 micrometers (pm) diameters or less), these standard options are no longer possible, either physically (e.g., in silicon due difficulties of etching through the thickness of a standard 200 millimeter (mm) or 300 mm wafer) or practically from a cost perspective (e.g., due to structured glass manufacturing limitations). Therefore, a method of manufacture is required that can accomplish this feat to enable applications that require a high density of vias (e.g., nanoscale deterministic lateral displacement ("nanoDLD”) arrays) for separating particles (e.g., exosomes).

[0004] A key challenge for LOC manufacturing in silicon, when high-density vias are implemented into a design, is to make the vias fluidically accessible and eliminate downstream wets processing common in semiconductor manufacturing, such as wet cleans. Wet processes can wick these fluids into the microfluidic device through capillary action, rendering the device unusable.

SUMMARY

[0005] The following presents a summary to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or critical elements, or delineate any scope of the invention or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. Embodiments of the invention described herein provide apparatuses, methods, and microfluidic chips with high via density.

[0006] According to an embodiment, an apparatus is provided. The apparatus comprises a silicon device layer comprising a plurality of vias. The vias comprise greater than or equal to 100 and less than or equal to 100,000 vias per square centimeter of the surface of the device layer. The vias extend through the device layer.

The apparatus also comprises a sealing layer bonded to the device layer, which can have greater rigidity than the device layer.

[0007] The apparatus may further comprise a microfluidic element located on a second surface of the device layer. The microfluidic element is in fluid communication with a via of the vias. Also, the microfluidic element is encapsulated by a combination of the device layer and the sealing layer.

[0008] According to another embodiment of the invention, a method is provided. The method comprises defining a microfluidic element on a first surface of a device layer. The method also comprises bonding a sealing layer to the first surface of the device layer. A combination of the sealing layer and the device layer encapsulates the microfluidic element. The method further comprises forming, after the bonding, a via within the device layer.

The via extends from a second surface of the device layer to a first surface of the device layer. Also, the second surface can be located on an opposite side of the device layer than the first surface. The method may further comprise thinning the device layer after the bonding and before the forming of the via.

[0009] According to another embodiment of the invention, an apparatus is provided. The apparatus comprises a silicon device layer comprising a via and a microfluidic device. The via extends through the device layer and is in fluid communication with the microfluidic device. Also, the device layer has a thickness greater than or equal to 7 micrometers and less than or equal to 500 micrometers. The apparatus also comprises a sealing layer bonded to the device layer. The sealing layer can have greater rigidity than the device layer.

[0010] The via may be within a plurality of vias. The vias may comprise greater than or equal to 100 vias and less than or equal to 100,000 vias per square centimeter of a surface of the device layer opposite to the sealing layer.

[0011] Thus, various embodiments of the invention described herein can provide a manufacturable structure and approach to create LOC technologies with high-density microfluidic vias. It is useful, for example, for LOC technologies that require high-throughput sample preparation. Also, one or more methods described herein can provide a means of protecting sealed microfluidic features from downstream wets processing (e.g., by opening vias last to make microfluidic features accessible using a final dry process). BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 is a diagram of a microfluidic chip embodying the invention that can comprise a high density of vias;

[0013] FIG. 2 is a photo of a wafer containing microfluidic chips embodying the invention;

[0014] FIG. 3 is another photo of a microfluidic chip having a high density of vias embodying the invention;

[0015] FIG. 4 is a flow diagram of a method embodying the invention for manufacturing a microfluidic chip that can comprise a high density of vias;

[0016] FIG. 5 is a diagram of a microfluidic chip embodying the invention at a first stage of manufacturing;

[0017] FIG. 6 is a diagram of a microfluidic chip embodying the invention at a second stage of manufacturing;

[0018] FIG. 7 is a diagram of a microfluidic chip embodying the invention at a third stage of manufacturing;

[0019] FIG. 8 is a diagram of a microfluidic chip embodying the invention at a fourth stage of manufacturing;

[0020] FIG. 9 is a diagram of a microfluidic chip embodying the invention at a fifth stage of manufacturing; and

[0021] FIG. 10 is a diagram of a microfluidic chip embodying the invention comprising a high density of vias.

DETAILED DESCRIPTION

[0022] The following detailed description is merely illustrative and is not intended to limit the invention or its uses. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding Background or Summary sections, or in the Detailed Description section.

[0023] One or more embodiments of the invention are now described with reference to the drawings, wherein like referenced numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of the invention. It is evident, however, in various cases, that the invention can be practiced without these specific details.

[0024] FIG. 1 is a diagram of a microfluidic chip 100 embodying the invention. The chip 100 comprises one or more vias 102, a sealing layer 104, one or more buses 106, one or more microfluidic elements 108, and a device layer 110. The microfluidic chip 100 comprises a high density of vias 102 within the device layer 110. The chip 100 may comprise a thin device layer 110 and one or more vias 102 in fluid communication with the microfluidic elements 108, which can be characterized by one or more dimensions that are greater than or equal to 1 nanometer and less than or equal to 10 millimeters. The sealing layer 104 and the device layer 110 may respectively comprise silicon (e.g., silicon compositions), glass, a combination thereof, and/or the like. [0025] Silicon is a well-established material in fabrication methods that can utilize subtractive (e.g. wet or dry etching) or additive methods (e.g. metal or chemical vapor deposition) to create microfluidic structures with nanoscale placement and features. High elastic modulus (e.g., characterized by 130-180 gigapascals (GPa)) can form rigid well-defined structures. Silanol group (-Si-OH) surface chemistry is well developed (e.g., surface modification with silanes). Further, silicon's ability to scale and integrate to provide complex functionality is very high. However, silicon is not transparent to visible light, so typical fluorescence detection or fluid imaging is challenging; although this can be overcome by bonding a transparent material to the surface of silicon, such as a polymer or glass. Also, silicon's high elastic modulus can make silicon difficult to be made into active fluidic components such as valves and pumps.

[0026] Glass fabrication methods exist that can utilize subtractive or additive methods to create microfluidic structures but not at the precision and scale of silicon. Glass may have low background fluorescence, and like silicon, has silanol-based surface modification chemistries readily available. Also, glass can be compatible with biological samples, can have relatively low nonspecific adsorption, and can be gas impermeable. However, compared to silicon, glass fabrication methods are not nearly as broad or precise (e.g., nanoscale features for microfluidics that are possible in silicon can be difficult to implement in glass). Glass also has a large, composition- dependent elastic modulus (e.g., hybrid devices can be required for active components such as valves and pumps).

[0027] Other materials for microfluidic chip technologies include ceramics, elastomers, thermoplastics, and paper. However, microfluidic chips 100 described herein comprise silicon and/or glass materials due at least in part to one or more structural and/or manufacturing difficulties ceramics, elastomers, thermoplastics, and/or paper can exhibit in microfluidic platforms. For example, low-temperature cofired ceramics ("LTCC”) can be fabricated into complex three-dimensional devices, wherein each layer can be inspected for quality control before assembling. Electrodes can be deposited using expansion matched metal pastes (e.g., for added functionality for detection and separation). Also, organically modified ceramics can provide an optically transparent, UV-curable material.

However, high-density ceramic electronics and multiplexed or integrated ceramic architectures can be difficult to implement. Further, features such as electrodes and channels can typically be 10's to 100's of microns in size and. not adaptable to certain types of microfluidic elements such as smaller pillar arrays or nanochannels. Also, ceramics can have a high elastic modulus, thereby rendering ceramics difficult to be made into active fluidic components such as valves and pumps. Moreover, ceramics can be difficult to hybridize with other materials.

[0028] Regarding elastomers, polydimethylsiloxane ("PDMS”) can be low in cost and is perhaps the most common microfluidic substrate. Elastomers can be easy to fabricate using a number of processes, including conventional machining and photolithography, and elastomers can be cast, stamped, and cured on molds.

Elastomers can have low elastic modulus (e.g., 300-500 kilopascals (kPa)), thereby making them useful for making values and pumps. PDMS can be gas permeable and thereby useful for oxygen and/or carbon dioxide transport in cellular studies. Also, elastomers can be transparent in the visible range, so typical fluorescence detection or fluid imaging can be employed. However, since PDMS can be gas permeable, it can cause problematic bubble formation. Also, PDMS can be a hydrophobic material and thereby susceptible to nonspecific adsorption and permeation by hydrophobic molecules. Other example elastomers can include, but are not limited to: thermoset polyester ("TPE”), polyfluoropolyether diol methacrylate ("PFPE-DMA”), and/or polystyrene ("PS”).

[0029] Further, thermoplastics can be highly moldable and manufacturable given they are durable, amenable to micromachining, hot embossing, and injection molding processes. Thermoplastics can be optically clear, resistant to permeation of small molecules, and stiffer than elastomers. Also, thermoplastics can be thermally, and/or laser, bonded to seal two layers together. For example, cyclic-olefin copolymer ("COC”) can be suitable for use with most solvents and aqueous solutions and can have low background fluorescence. Further, thermoplastics can have low manufacturing costs. However, COC can be hydrophobic, and thereby require surface modification to reduce nonspecific adsorption. Also, thermoplastics can typically require another medium (e.g., a master mold) to replicate many devices (e.g. silicon master).

[0030] Moreover, paper can be extremely cheap and readily available, can be disposed of by burning or natural degradation, and can be easily patterned and functionalized. Porous paper can allow for a combination of flow, filtering, and separation. Also, paper can be biologically compatible and chemically modified through composition or formulation changes or by implementing surface chemistry. However, paper can rely on passive capillary action for operation, and thereby paper system may not be amenable to more complex functionality or material hybridization.

[0031] Considerations regarding the selection of materials comprising the sealing layer 104 and/or the device layer 110 can include, but are not limited to: the required function of the layers, the degree of microfluidic element integration needed on the layers, and/or the final application of the chip 100. The choice of silicon and/or silicon- glass systems is attractive in LOC applications requiring high-density device integration, parallelization, multi functional or multi-device arrangements (separation and detection, for example) or in applications requiring embedded microelectronics. The sealing layer 104 may comprise glass and the device layer 110 may comprise silicon (e.g., a crystalline silicon such as a silicon wafer). Where the device layer 110 comprises silicon, high pressures can be applied to the microfluidic element 108 as a driving force to operate the microfluidic chip 100 without deforming the structures.

[0032] The sealing layer 104 is bonded to the device layer 110. The sealing layer 104 can have greater rigidity that the device layer 110, thereby providing enhanced rigidity to the device layer 110 during manufacturing of the chip 100. The sealing layer 104 encapsulates the microfluidic elements 108 and/or the buses 106; thereby protecting the microfluidic elements 108 and/or the buses 106 during manufacturing of the chip 100. The sealing layer 104 may have a thickness greater than or equal to 100 m and less than or equal to 2.5 mm. The device layer 110 may have a thickness greater than or equal to 7 pm and less than or equal to 500 pm. The sealing layer 104 may be thicker than the device layer 110.

[0033] The buses 106 (e.g., fluid buses) may be embedded, subtractively patterned, and/or otherwise etched into the device layer 110. The buses 106 serve as channels that guide and/or transport fluid through the chip 100 with low fluidic resistance. The buses 106 form a bus network that carry fluid to and from the microfluidic elements 108. The microfluidic elements 108 are embedded within the device layer 110 and located on a top surface of the device layer 110, which is bonded to the sealing layer 104. The microfluidic elements 108 may comprise one or more devices that utilize deterministic displacement arrays and/or deterministic lateral displacement technologies ("DLD”), such as condenser arrays (e.g., microscale condenser arrays and/or nanoscale condenser arrays) and/or nanoDLD arrays. Further example microfluidic elements 108 include, but are not limited to: microscale and/or nanoscale pillars, channels, biosensors, fluid mixing features, fluidic bus networks, fluidic inlets, and fluidic outlets.

[0034] One or more of the buses 106 and/or the microfluidic elements 108 are in fluid communication with the vias 102. The vias 102 traverse through the device layer 110. The vias 102 may extend from a first side to a second side of the device layer 110 (e.g., wherein the sealing layer 104 is bonded to the second side of the device layer 110).

[0035] The chip 100 may have a high density of vias 102 traversing the device layer 110. For example, the chip 100 may comprise hundreds to tens of thousands of vias 102 per square centimeter of the device layer 110.

For instance, the chip 100 can comprise greater than or equal to 100 and less than or equal to 100,000 vias 102 per square centimeter of the device layer 110. Additionally, the vias 102 may have diameters greater than or equal to 5 pm and less than or equal to 5 mm. Moreover, vias 102 may share a common diameter or have different diameters. One of ordinary skill in the art will recognize that although FIG. 1 shows a particular number of vias 102, buses 106, and/or microfluidic elements 108, the architecture of the microfluidic chip 100 is not so limited. For example, the chip 100 may comprise fewer or additional vias 102, buses 106, and/or microfluidic elements 108 than those depicted in FIG. 1.

[0036] FIG. 2 is a photo of a wafer 200 comprising one or more microfluidic chips 100 (e.g., including a device layer 110 (e.g., comprising silicon) and/or sealing layer 104 (e.g., comprising glass)). The wafer 200 may have a thickness greater than or equal to 300 pm and less than or equal to 2.5 mm. Also, the wafer 200 may comprise greater than or equal to 1 and less than or equal to 32,000 chips 100. For example, the wafer 200 may have a thickness of 200 mm and comprise 32 chips 100. Further, wafer 200 of FIG. 2 may comprise chips 100 that have vias 102 having a common diameter of 50 pm and/or a density of 1 ,000 vias 102 per square centimeter.

Additionally, the wafer 200 may comprise one or more chip boarders (not shown) etched into the wafer 200 to facilitate separation of one or more of the chips 100 (e.g., via chip dicing). The chip boarders help prevent damage to the thin device layer 110 at the edges of the chip 100 being separated.

[0037] FIG. 3 is a scanning electron micrograph ("SEM”) of a microfluidic chip 100 of the wafer 200 shown in FIG. 2. FIG. 3 is a cross-section of the chip 100. As shown in FIG. 3, the chip 100 comprises a glass sealing layer 104 having a thickness of 700 pm, and a silicon device layer 110 of 90 pm.

[0038] Conventional methods of manufacturing are unable to produce the microfluidic chip 100 due at least to the following considerations. First, the vias 102 require much thinner substrates (e.g., device layer 110) to etch completely through the wafers (e.g., wafer 200) to create fluidically accessible holes. The vias 102 can have aspect ratios greater than 1 :10 (diameter: depth), which are challenging to create using the conventional standard for via creation of reactive-ion etch ("RIE”). Second, etching completely through a wafer (e.g., wafer 200) can also be problematic as many RIE chambers have inductively coupled wafer chucks and use vacuum systems that will be damaged or error out during processing if the device layer 110 is etched through completely. Third, the thin device layer 110 requires a carrier wafer of some kind to support the thin device layer 110, which can be extremely brittle when thinned to, for example, 50 pm thickness (e.g., which can facilitate 5 pm diameter vias 102). Thin wafers (e.g., thin device layers 110) are desired to reduce RIE process time to create the vias 102. Fourth, thin device layers 110 cannot be de-bonded from the carrier after polishing as the silicon is too brittle and a sealing layer 104 can still be required. This presents a fifth challenge of preventing fluidic wicking or capillary wetting of microfluidic features due to post via wet processing common in semiconductor manufacturing. Standard thru-silicon via ("TSV”) technology can use a fill material, such as copper, to plug the vias 102, which does not translate to microfluidic devices. Collectively, these challenges call for a via-last structure and method that can protect sealed microfluidic features from downstream wets processing (e.g. chemical mechanical polishing (CMP) and cleans) and that can provide a permanent sealing layer 104 for support.

[0039] FIG. 4 is a flow diagram of a method 400 embodying the invention for facilitating manufacturing the chip 100.

[0040] At 402, the method 400 comprises defining microfluidic elements 108 and/or buses 106 onto the surface of a device layer 110. The elements 108 and/or the buses 106 may be defined on a first lithography layer and patterned onto the surface of the device layer 110. Depending on the minimum feature size of the elements 108 and/or buses 106, a number of lithography options may be employed during the method 400, including but not limited to: various wavelength optical lithography (mid-ultraviolet ("UV”), deep-UV, 193 nm (e.g. argon fluoride laser)), immersion lithography, e-beam lithography, imprint lithography, interference lithography, x-ray lithography, a combination thereof, and/or the like. [0041] FIG. 5 is a diagram of chip 100 being manufactured in accordance with method 400. FIG. 5 is a cross- section of the chip 100 after completion of the defining at 402. The defining at 402 comprises defining one or more microfluidic elements 108 and/or one or more buses 106 onto a first surface 502 of the device layer 110.

[0042] Referring again to FIG. 4, at 404 the method 400 may optionally comprise deepening the buses 106. Respective buses 106 can be deepened in their entirety at 404, or only a portion of a respective bus 106 can be deepened. The deepening at 404 can be facilitated by a second lithography layer, which can be used in conjunction with an etch process (e.g., RIE, tetramethylammonium hydroxide ("TMAFI”) etching, potassium hydroxide ("KOFI”) etching, a combination thereof, and/or the like). The deepening at 404 may be omitted for sufficiently small chips 100 or those whose microfluidic elements 108 are very fluidically restrictive. Essentially, parallel device arrays or other microfluidic elements 108 can drop most of the fluidic resistance to avoid discrepancies in fluidic rate conditions in the buses 106 (e.g., the buses 106 can comparably have very high fluidic conductance).

[0043] FIG. 6 is a diagram of chip 100 manufactured in accordance with method 400. FIG. 6 is a cross- section of chip 100 after completion of the deepening at 404.

[0044] Referring again to FIG. 4, at 406 the method 400 comprises bonding a sealing layer 104 to the surface of the device layer 110. The sealing layer 104 may be permanently bonded to the device layer 110. The sealing layer 104 can be anodically bonded glass (e.g. Borofloat 33), a thermally bonded silicon wafer, and/or other substrates. Glass and other transparent substrate options offer the advantage of transparency for applications that require some kind of in situ analysis, such as fluorescence microscopy. Sealing the device layer 110 serves at least two purposes: 1) it prevents downstream damage, wetting, and process contamination from impacting the microfluidic chip 100 features, and 2) it acts as a support for a thinned device layer 110 when polished subsequently in the method 400.

[0045] FIG. 7 is a diagram of chip 100 manufactured in accordance with method 400. FIG. 7 is a cross- section of chip 100 after completion of the bonding at 406.

[0046] Referring again to FIG. 4, at 408 the method 400 comprises reducing the thickness of the device layer 110 to a final thickness. The thinning at 408 may be facilitated using a chemical-mechanical planarization ("CMP”) or a wet process (e.g., TMAFI and/or KOFI etching). The device layer 110 may be thinned to a thickness of 7-500 pm post subsequent to the bonding at 406. By thinning the device layer 110, scaled fluidic vias 102 with diameters ranging from 5 pm to 100 pm can be possible to fabricate in up to 300 mm wafers 200 with a starting nominal thickness of 775 pm, which can mate with the elements 108 and/or buses 106 to input and extract a sample from various access points on the microfluidic chip 100. [0047] FIG. 8 is a diagram of chip 100 manufactured in accordance with method 400. FIG. 8 is a cross- section of chip 100 after completion of the reducing at 408. As shown in FIGs. 7 and 8, "Ti” represents the thickness of the device layer 110 prior to the thinning at 408, and "T2” represents the thickness of the device layer 110 subsequent to the thinning at 408; wherein T 1 can be greater than T2.

[0048] Referring again to FIG. 4, at 410 the method 400 comprises forming vias 102 in the device layer 110. The vias 102 extend completely through the device layer 110. Front-to-back alignment of the vias 102 may be performed using an optical and/or infrared (“IR”) camera to ensure alignment accuracy of a third lithography layer needed to align the vias 102 patterned on the back side of the device layer 110 (e.g., the side opposite to a side comprising the elements 108) with the front side elements 108, which reside in the device layer 110 (e.g., comprised of silicon) at the interface of the sealing layer 104 and device layer 110. The third lithography layer may be used to pattern the vias 102 in a hard mask, such as silicon oxide and/or silicon nitride, followed by removal of the resist and cleaning of the device layer 110, after which the vias 102 may be defined by a RIE process.

Alternatively, the third lithography layer may be used as the etch mask itself and can be removed with an oxygen plasma after the vias 102 have been opened. The first approach of defining the vias 102 in a hard mask has the advantage of being able to more thoroughly clean the bonded layer pair (e.g., the device layer 110 bonded to the sealing layer 104) before the final via 102 opening RIE process. Wherein multiple chips 100 are formed on a wafer 200, the chips 100 can then be diced employing a standard dicing process and bonding film of sufficient tack to prevent fluid from entering the vias 102.

[0049] FIG. 9 is a diagram of chip 100 being manufactured in accordance with method 400. FIG. 9 is a cross- section of chip 100 after completion of the forming of the vias 102 at 410. As shown in FIG. 9, once formed the vias 102 extend from a second surface 902 of the device layer 110 to the first surface 502 of the device layer 110.

[0050] The microfluidic chip 100 may further comprise sacrificial plugs 1002. The method 400 may comprise inserting the plugs 1002 into the device layer 110 after defining the buses 106 (e.g., at 402 and/or 404) and prior to bonding the device layer 110 to the sealing layer 104 (e.g., at 406). The plugs 1002 may be patterned using a resist material. The plugs 1002 perform the function of ensuring uniformity of RIE breakthrough to the elements 108, ensuring that the elements 108 are not themselves etched by the forming of the vias 102. This may be particularly useful in cases where the vias 102 have different dimensions and thus etch at different rates. The plugs 1002 may be extracted using a downstream oxygen plasma (e.g., before or after the chip 100 is diced).

[0051] FIG. 10 is a diagram of a chip 100 manufactured in accordance with method 400. FIG. 7 is a cross- section of chip 100 after completion of the forming of the vias 102 at 410, wherein one or more sacrificial plugs 1002 were inserted into the device layer 110. [0052] Thus, method 400 facilitates manufacturing microfluidic chips 100 described herein by forming the vias 102 as a last step. Unlike conventional TSV technology, the vias 102 of chip 100 can be open structures, which makes chips that implement them vulnerable to destruction by capillary action of wet processing common in semiconductor manufacturing. However, method 400 avoids destruction of the chip 100 by using a final RIE process (dry) to open the vias 102. Additionally, by thinning the device layer 110 (e.g., silicon) prior to forming the vias 102, the method 400 avoids conventional requirements of ultra-deep silicon etching that would otherwise be required to create the vias 102 and is problematic to implement in a practical process flow. Moreover, while method 400 is described herein with regard to chip 100 comprising a high density of vias 102, method 400 can also applicable to the manufacturing of microfluidic chips 100 only a few vias 102.

[0053] In a preferred embodiment of the invention, there is provided an apparatus, comprising: a silicon device layer comprising a via and a microfluidic device, the via extending through the silicon device layer and in fluid communication with the microfluidic device, wherein the silicon device layer has a thickness greater than or equal to about 7 micrometers and less than or equal to about 500 micrometers; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer.

[0054] The sealing layer preferably has a second thickness greater than or equal to about 100 micrometers and less than or equal to about 2.5 millimeters.

[0055] In addition, the term "or” is intended to mean an inclusive "or” rather than an exclusive "or.” That is, unless specified otherwise, or clear from context, "X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B” is satisfied under any of the foregoing instances. Moreover, articles "a” and "an” as used in the subject specification and annexed drawings should generally be construed to mean "one or more” unless specified otherwise or clear from context to be directed to a singular form. As used herein, the terms "example” and/or "exemplary” are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as an "example” and/or "exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.

[0056] What has been described above include mere examples of systems and methods. It is, of course, not possible to describe every conceivable combination of components and methods for purposes of describing the invention, but one of ordinary skill in the art can recognize that many further combinations and permutations of the invention are possible. Furthermore, to the extent that the terms "includes,” "has,” "possesses,” and the like are used in the detailed description, claims, appendices and drawings such terms are intended to be inclusive in a manner similar to the term "comprising” as "comprising” is interpreted when employed as a transitional word in a claim. The descriptions of the various embodiments of the invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the invention. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The terminology used herein was chosen to best explain the principles of the invention, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments of the invention disclosed herein.