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Title:
MONITOR DEFLECTION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2002/052533
Kind Code:
A2
Abstract:
A monitor deflection circuit includes a bipolar power transistor for applying power from a high voltage supply to a horizontal deflection coil. The monitor deflection circuit further includes a base drive circuit for selectively turning the bipolar power transistor on and off. The base drive circuit includes a flyback transformer having a primary winding and a secondary winding coupled to the base of the bipolar power transistor, a voltage source coupled to one end of the primary winding, and a drive switch coupling the other end of the primary winding to ground. The base driver circuit further includes a constant current circuit coupled between the voltage source and the primary winding of the flyback transformer for controlling a base current of the bipolar power transistor before the bipolar power transistor conducts.

Inventors:
QIAN JINRONG
Application Number:
PCT/IB2001/002668
Publication Date:
July 04, 2002
Filing Date:
December 19, 2001
Export Citation:
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Assignee:
KONINKL PHILIPS ELECTRONICS NV (NL)
International Classes:
G09G1/04; H03K4/62; H04N3/16; H04N3/18; (IPC1-7): G09G1/04
Foreign References:
US5614794A1997-03-25
US5808426A1998-09-15
US4177393A1979-12-04
Attorney, Agent or Firm:
Groenendaal, Antonius W. M. (Internationaal Octrooibureau B.V. Prof. Holstlaan 6 AA Eindhoven, NL)
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Claims:
CLAIMS:
1. A monitor deflection circuit comprising: a switching transistor (BJT) having a control input and a main current path between a first and a second electrode; a high voltage supply (VB+) for providing a high voltage, said high voltage supply being coupled to the first electrode of said switching transistor; a parallel arrangement of a retrace capacitor (Cr) and a damping rectifier (Dr) arranged across the first and the second electrode; a series arrangement of a horizontal deflection yoke (Ly) and an Scorrection capacitor (Cs) also arranged across the first and the second electrode; and a driver circuit for driving the control input of the switching transistor, said driver circuit including a flyback transformer (T) having a primary winding (N1) and a secondary winding (N2) coupled to the control input, a voltage source (Vc) coupled across a series arrangement of the primary winding (N1) and a drive switch (S 1), wherein the base driver circuit further comprises: a constant current circuit (R10R12, C10, Cl 1, DW, TR) coupled between the voltage source (Vc) and the primary winding of the flyback transformer for controlling a base current of the bipolar power transistor (BJT) before the bipolar power transistor (BJT) conducts.
2. A monitor deflection circuit as claimed in claim 1, wherein the switching transistor is a bipolar transistor having a base, an emitter and a collector, the control input being the base, the first and second electrode being the collector and the emitter, respectively, and wherein the voltage source (Vc) to one end of the primary winding (N1) and the drive switch (S 1) coupling the other end of the primary winding (N1) to ground.
3. The monitor deflection circuit as claimed in claim 1, wherein the constant current circuit comprises: a pnp transistor (TR) having a base, an emitter and a collector, the emitter of the pnp transistor (TR) being connected to the primary winding (N1) ; a series arrangement of a first and a second resistor (R10, Rl 1) connecting the voltage source (Vc) to the collector of the pnp transistor (TR); a first capacitor (C10) coupling a junction between the first and second resistors to ground; a Zener diode (DW) connecting said junction to the base of the pnp transistor (TR); and a series arrangement of a third resistor (R12) and a second capacitor (C11) connecting the base of the pnp transistor (TR) to the emitter, a junction between the third resistor (R12) and the second capacitor (C11) being connected to ground.
4. The monitor deflection circuit as claimed in claim 3, wherein the base driver circuit further comprises a series arrangement of a fourth resistor (R13) and a third capacitor (C12) arranged across the drive switch (S1).
5. The monitor deflection circuit as claimed in claim 1, wherein said monitor deflection circuit further comprises: a fast switching device (Sb) arranged in series with the collectoremitter path of said bipolar power transistor (BJT), whereby said fast switching device (Sb) speeds up the turnoff process of the bipolar power transistor (BJT).
6. The monitor deflection circuit as claimed in claim 5, wherein said flyback transformer (T) comprises serially arranged first and second secondary windings (N2, N3), the baseemitter path of said bipolar power transistor (BJT) and said fast switching device (Sb) being coupled across said first secondary winding (N2), and said parallel arrangement of said damping diode (Dr) and said retrace capacitor (Cr), as well as said series arrangement of said yoke (Ly) and said Scorrection capacitor (Cs), being arranged across the collector emitter path of said bipolar power transistor (BJT) and said second secondary winding (N3).
7. The monitor deflection circuit as claimed in claim 5, wherein said flyback transformer (T) comprises serially arranged first and second secondary windings (N2, N3), the baseemitter path of said bipolar power transistor (BJT) and said fast switching device (Sb) being coupled across said first secondary winding (N2), and said secondary winding (N3) being arranged in series with the high voltage supply (VB+) and the emitter of said bipolar power transistor (BJT), said parallel arrangement of said damping diode (Dr) and said retrace capacitor (Cr), as well as said series arrangement of said yoke (Ly) and said S correction capacitor (Cs), being arranged across the second secondary winding (N3), the collectoremitter path of the bipolar power transistor (BJT) and the fast switching device (Sb).
8. The monitor deflection circuit as claimed in claim 1, wherein said flyback transformer (T) comprises serially arranged first and second secondary windings (N2, N3), the baseemitter path of said bipolar power transistor (BJT) being coupled across said first secondary winding (N2), and said parallel arrangement of said damping diode (Dr) and said retrace capacitor (Cr), as well as said series arrangement of said yoke (Ly) and said S correction capacitor (Cs), being arranged across the collectoremitter path of said bipolar power transistor (BJT) and said second secondary winding (N3).
9. The monitor deflection circuit as claimed in claim 3, wherein said monitor deflection circuit further comprises: a fast switching device (Sb) arranged in series with the collectoremitter path of said bipolar power transistor (BJT), whereby said fast switching device (Sb) speeds up the turnoff process of the bipolar power transistor (BJT).
10. The monitor deflection circuit as claimed in claim 9, wherein said fast switching device (Sb) is a MOSFET.
11. The monitor deflection circuit as claimed in claim 9, wherein said flyback transformer (t) comprises serially arranged first and second secondary windings (N2), the baseemitter path of said bipolar power transistor (BJT) and said fast switching device (Sb) being coupled across said first secondary winding (N2), and said parallel arrangement of said damping diode (Dr) and said retrace capacitor (Cr), as well as said series arrangement of said yoke (Ly) and said Scorrection capacitor (Cs), being arranged across the collectoremitter path of said bipolar power transistor (BJT) and said second secondary winding (N3).
12. The monitor deflection circuit as claimed in claim 9, wherein said flyback transformer (T) comprises serially arranged first and second secondary windings (N2, N3), the baseemitter path of said bipolar power transistor (BJT) and said fast switching device (Sb) being coupled across said first secondary winding (N2), and said secondary winding (N3) being arranged in series with the high voltage supply (VB+) and the emitter of said bipolar power transistor (BJT), said parallel arrangement of said damping diode (Dr) and said retrace capacitor (Cr), as well as said series arrangement of said yoke (Ly) and said S correction capacitor (Cs), being arranged across the second secondary winding (N3), the collectoremitter path of the bipolar power transistor (BJT) and the fast switching device (Sb).
13. The monitor deflection circuit as claimed in claim 3, wherein said flyback transformer (T) comprises serially arranged first and second secondary windings (N2, N3), the baseemitter path of said bipolar power transistor (BJT) being coupled across said first secondary winding (N2), and said parallel arrangement of said damping diode (Dr) and said retrace capacitor (Cr), as well as said series arrangement of said yoke (Ly) and said S correction capacitor (Cs), being arranged across the collectoremitter path of said bipolar power transistor (BJT) and said second secondary winding (N3).
14. The monitor deflection circuit as claimed in claim 4, wherein said monitor deflection circuit further comprises: a fast switching device (Sb) arranged in series with the collectoremitter path of said bipolar power transistor (BJT), whereby said fast switching device (Sb) speeds up the turnoff process of the bipolar power transistor (BJT).
15. The monitor deflection circuit as claimed in claim 14, wherein said fast switching device (Sb) is a MOSFET.
16. The monitor deflection circuit as claimed in claim 14, wherein said flyback transformer (T) comprises serially arranged first and second secondary windings (N2, N3), the baseemitter path of said bipolar power transistor (BJT) and said fast switching device (Sb) being coupled across said first secondary winding (N2), and said parallel arrangement of said damping diode (Dr) and said retrace capacitor (Cr), as well as said series arrangement of said yoke (Ly) and said Scorrection capacitor (Cs), being arranged across the collector emitter path of said bipolar power transistor (BJT) and said second secondary winding (N3).
17. The monitor deflection circuit as claimed in claim 14, wherein said flyback transformer (T) comprises serially arranged first and second secondary windings (N2, N3), the baseemitter path of said bipolar power transistor (BJT) and said fast switching device (Sb) being coupled across said first secondary winding (N2), and said secondary winding (N3) being arranged in series with the high voltage supply (VB+) and the emitter of said bipolar power transistor (BJT), said parallel arrangement of said damping diode (Dr) and said retrace capacitor (Cr), as well as said series arrangement of said yoke (Ly) and said S correction capacitor (Cs), being arranged across the second secondary winding (N3), the collectoremitter path of the bipolar power transistor (BJT) and the fast switching device (Sb).
18. The monitor deflection circuit as claimed in claim 4, wherein said flyback transformer (T) comprises serially arranged first and second secondary windings (N2, N3), the baseemitter path of said bipolar power transistor (BJT) being coupled across said first secondary winding (N2), and said parallel arrangement of said damping diode (Dr) and said retrace capacitor (Cr), as well as said series arrangement of said yoke (Ly) and said S correction capacitor (Cs), being arranged across the collectoremitter path of said bipolar power transistor (BJT) and said second secondary winding (N3).
19. A monitor comprising a monitor deflection circuit as claimed in claim 1.
Description:
Monitor deflection circuit BACKGROUND OF THE INVENTION Field of The Invention The subject invention relates to a circuit for deflecting an electron beam in a monitor.

Description of The Related Art As shown in Fig. 1, a conventional deflection circuit includes a bipolar power transistor BJT, a damping diode Dr, a retrace capacitor Cr, a horizontal deflection coil Ly, S- correction capacitor Cs and a base driver circuit. The base driver circuit consists of a flyback isolation transformer T, damping resistors Rl and R2, a snubber circuit D1, R3 and C1, and a drive switch S1. Fig. 2 shows the key waveforms of the deflection circuit. In operation, the damping diode Dr, which is in anti-parallel with the bipolar transistor BJT, is turned on at to.

The voltage Vs is applied to the deflection coil Ly and causes the deflection coil current iy to increase. The damping diode Dr is turned off at zero voltage at tl, where the deflection coil current iy reverses. The transistor BJT is then turned on and takes the deflection coil current.

The drive switch S 1 is turned on at t2 and a negative voltage is applied to the base-emitter of the transistor BJT. After a storage time, the transistor BJT is turned off at t3. The deflection coil Ly and the retrace capacitor Cr form a resonant circuit which generates a high voltage for resetting the deflection coil Ly. This high voltage across the collector and emitter of the BJT Vce. can be expressed as: where ts and tr are the sweep time and retrace time, respectively.

Because the power transistor BJT has a large tail current, this overlaps the collector-emitter voltage and generates a high switching turn-off loss. In addition, high voltage rating power transistors have a small current gain hfe (the ratio of the collector current to the base current), which requires a high based current to turn the device on and off. Thus, the power loss in the base drive circuit is significant.

The waveform of the base current for the transistor BJT has a great influence on its power loss. Unlike majority carrier power switches, such as MOSFETs and IGBTs, the BJT requires high base current to turn the device on and off, especially for high voltage and high current bipolar transistors, which have low current gains, usually less than 10. For monitor applications, the collector current of the BJT linearly increases with the sweep time, as shown in Fig. 2. Thus, the required base drive current should follow the collector current waveshape to achieve optimum operation of the BJT. In other words, it needs the highest base drive current at the end of the horizontal sweep at t2, where the BJT conducts the highest deflection coil current. Besides, since the horizontal deflection circuit operates at a wide rage of frequencies, typically from 30 kHz to 86 kHz, and even 100 kHz for high resolution, the base drive circuit should be able to supply proper base current for the operating frequency range. The conventional base drive circuit employs a flyback transformer to supply base current to the bipolar transistor BJT and uses high turns ratio to reduce the current level in the circuit on the primary side. As shown in Fig. 2, when S 1 is turned on, a negative voltage, generated in the secondary winding, is applied to the emitter- base junction and turns off the transistor BJT. The supply voltage is supplied in the primary winding, which causes the magnetizing current to increase. When the drive switch S 1 is turned off, the magnetizing current is reflected to the secondary winding and used as the base current to turn on the transistor BJT. Because of the nature of the flyback transformer, the base current linearly decreases with the sweep time. With the increase of the collector current, the base current provided by the drive circuit is actually decreased. This is contradictory to the requirements, this high base current being needed for the high collector current. If the base current is kept high enough at the end of the sweep time of t2 to fully conduct the deflection coil current, then the transistor BJT is definitely overdriven at the beginning of the transistor BJT conduction. As a result, high power dissipation exists and high rating components have to be used in the base drive circuit, which consequently increases the cost.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a base drive circuit for a deflection circuit having a reduced power consumption for reducing the cost thereof.

To this end, a first aspect of the invention provides a monitor deflection circuit as claimed in claim 1. A second aspect of the invention provides a monitor as claimed in claim 19.

Applicant has found that by including a constant current circuit to control the base current of the bipolar power transistor prior to it conducting, the base current is significantly reduced, which reduces the power dissipation.

It is an advantage of the present invention to provide a simplified base drive circuit for a bipolar transistor having an optimum base current waveform.

It is a further advantage of the present invention to provide a base drive circuit for supplying a base current proportional to the collector current with a wide range of operating frequencies.

BRIEF DESCRIPTION OF THE DRAWINGS With the above and additional objects and advantages in mind as will hereinafter appear, the invention will be described with reference to the accompanying drawings, in which: Fig. 1 is a schematic diagram of a known deflection circuit; Fig. 2 shows typical waveforms in the deflection circuit of Fig. 1; Fig. 3 shows a first embodiment of the deflection circuit of the subject invention; Fig. 4 shows waveforms appearing in the deflection circuit of Fig. 3; Fig. 5 shows a second embodiment of the deflection circuit of the subject invention; Fig. 6 shows a third embodiment of the deflection circuit of the subject invention; and Fig. 7 shows a monitor comprising the deflection circuit of the subject invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 3 shows a first embodiment of the monitor deflection circuit which exhibits power loss reduction in the base drive circuit and the power transistor BJT. In the base drive circuit, a supply voltage Vc is applied to the series arrangements of damping resistors RIO and R11 and to the emitter of PNP transistor TR. A zener diode DW connects the base of the transistor TR to the junction between the damping resistors RIO and RI 1, while a capacitor C10 connects this junction to ground. A resistor R12 connects the base to ground, while the collector of the transistor TR is connected to ground via a capacitor C 11, and to end of a primary winding N1 of flyback transistor T. The other end of the primary

winding Nl is connected to ground via the parallel arrangement of a drive switch S1, on the one hand, and a series arrangement of a capacitor C12 and a resistor R13.

The flyback transformer T has a first secondary winding N2 which is shunted, on the one hand, by a resistor Rb and, on the other hand, by the base-emitter of the power transistor BJT in series with a MOSFET Sb. A second secondary winding N3 has one end connected to the low side of the first secondary winding N2. A high voltage VB+ is coupled to the collector of the transistor BJT through an inductor LB. A parallel combination of a diode Dr and a capacitor Cr connects the collector of the transistor BJT to the other end of the second secondary winding N3. Finally, a series arrangement of the deflection coil Ly and a capacitor Cs connect the collector of the transistor BJT to the other end of the secondary winding N3.

In operation, a constant current circuit, comprising the components R10, RI 1, R12, DW, C10, C11 and TR, is used to control the base current before the transistor BJT conducts. The required base current is fairly small when the BJT conducts a small collector current before tl, as shown in Fig. 4, when the deflection coil current becomes positive. Thus, the value of the current source il is only a few milliamperes, which consequently causes a significant loss reduction in the base drive circuit. The constant current circuit is independent of the operation frequency. As a result, this base drive, circuit is able to operate with a wide range of frequency while maintaining minimum power loss. In the subject invention, the base current is even lower than in the prior art during the time interval to and tl than during the time period between t, and t2. Therefore, the base current is significantly reduced, which reduces the power dissipation. After tl, the transistor BJT begins to conduct the deflection coil current. The windings N2 and N3 are tightly coupled. Based on Ampere's law, the base current ib is give by: <BR> <BR> <BR> <BR> <BR> <BR> <BR> ib= N3 I. c (2)<BR> ib = ic<BR> <BR> N2 The base current of the transistor BJT is primarily provided by part of the collector current. If the turns ratio between windings N2 and N3 is properly chosen and equals the current gain of the transistor BJT, for instance, 5, then energy supplied to the base is not from the drive supply Vc, but from the deflection circuit. Furthermore, the base current ib is proportional to the collector current according to Equation (2), which is good for the transistor BJT to operate efficiently. The voltage drop across the winding N3 is given by <BR> <BR> <BR> <BR> zu<BR> <BR> <BR> <BR> N3 Vbe where Vbe is the forward biased voltage drop across the base-emitter, typically<BR> <BR> <BR> z

around 1.0 V. Hence, the voltage drop across the winding N3 is approximately 0.2 V, and will not affect the linearity of the deflection coil current.

Since the transistor BJT is a minority carrier power device, it has a fairly long storage time, which is also dependent on various parameters. This will make control system more complicated. Besides, the transistor BJT has a relatively high tail current when it is turned off, which causes high turn-off switching loss. In the circuit of the subject invention, a fast switch device, MOSFET Sb is in series with the transistor BJT to speed up the turn-off process of the transistor BJT. Once MOSFET Sb is turned off, it cuts the emitter current immediately and no tail current flows through the transistor BJT. As a result, the power loss due to the tail current is greatly reduced. Besides, by properly controlling the switching timing of the MOSFET Sb, the storage time is also controllable and storage time tolerance can be eliminated. As shown in Fig. 4, when switch S 1 is turned on, the supply voltage Ve is provided to the primary winding N1, which induces a negative voltage across winding N2.

This negative voltage will give a negative bias voltage to the base-emitter to turn off the transistor BJT. Since there are extra minority carriers in the collector N-region and the emitter, a negative base current drives these minority carriers out of the emitter and collector.

At t3, MOSFET Sb is turned off, which cuts the emitter current of the transistor BJT. As a result, the negative base is equal to the collector current, flows out of the base to speed up the turn-off process. Because the MOSFET Sb turn-off speed is much faster than the transistor BJT, the switching loss in the transistor BJT is significantly reduced. Once the minority carriers are all out of from the collector, the transistor BJT is basically turned off, and the deflection coil current begins to resonate with the capacitor Cr, which increases the voltage Vce in a sinusoidal form. The high voltage Vce will reset the deflection coil current to a negative value until t4, where the anti-parallel diode Dr starts conducting.

Tests have shown that the power loss in the base drive circuit is less than 1 watt, while prior art circuits exhibited over 4 watts power loss with 85kHz operation frequency and 6 A yoke current. In addition, the storage time of the BJT transistor is also significantly reduced by properly controlling the timing of the MOSFET Sb. Due to the emitter switch Sb, there is no tail current of the BJT transistor so as to reduce the switching loss.

Fig. 5 shows a second embodiment of the invention which has a substantially similar performance as that of Fig. 3. In this embodiment, the coupling winding N3 is connected to the collector terminal of the BJT transistor, as opposed to the emitter terminal.

Therefore, the source of MOSFET Sb is connected to ground and no gate isolation

transformer or level shifter for MOSFET Sb is need, compared with the embodiment of Fig.

3. The result is that cost can be further reduced.

Fig. 6 shows a third embodiment of the invention which again has a substantially similar performance as that of Fig. 3. In this embodiment, there is no emitter open switch connected to the emitter of the transistor BJT, as such, the MOSFET Sb has been eliminated. While this implementation further reduces cost, it has higher switching losses as compared with the circuits of Figs. 3 and 5.

Fig. 7 shows a monitor comprising the deflection circuit 3 of the subject invention. An input video signal 1 (for example: composite or separate synchronization and RGB signals) is supplied to a synchronization circuit 2 to process the synchronization signals to obtain drive signal 6 for the deflection circuit 3, and to a video signal processing circuit 5.

The deflection circuit 3 supplies deflection currents 7 to deflection coils arranged around a picture tube 4 to deflect the electron beam (s). The video signal processing circuit 5 supplies video drive signals 8 (usually R, G, and B) to the picture tube 4 to modulate the intensity of the electron beam (s).

Numerous alterations and modifications of the structure herein disclosed will present themselves to those skilled in the art. However, it is to be understood that the above described embodiment is for purposes of illustration only and not to be construed as a limitation of the invention. All such modifications which do not depart from the spirit of the invention are intended to be included within the scope of the appended claims.