Title:
MULTI-DIE PEAK POWER MANAGEMENT FOR THREE-DIMENSIONAL MEMORY
Document Type and Number:
WIPO Patent Application WO/2022/027403
Kind Code:
A1
Abstract:
Embodiments of a peak power management (PPM) circuit on a memory die are disclosed. The PPM circuit includes a first transistor and a second transistor arranged in parallel, wherein the first and second transistors each has a drain terminal electrically connected to a first power source and a second power source, respectively. The PPM circuit also includes a resistor having a first terminal electrically connected to respective source terminals of the first and second transistors. The PPM circuit further includes a first contact pad on the memory die, electrically connected to a second contact pad on a different memory die through a die-to-die connection. The PPM circuit also includes a third transistor with a drain terminal electrically connected to a second terminal of the resistor, and a source terminal electrically connected to the first contact pad.
Inventors:
TANG QIANG (CN)
GUO JASON (CN)
GUO JASON (CN)
Application Number:
PCT/CN2020/107294
Publication Date:
February 10, 2022
Filing Date:
August 06, 2020
Export Citation:
Assignee:
YANGTZE MEMORY TECH CO LTD (CN)
International Classes:
G11C16/30
Foreign References:
| US20140195734A1 | 2014-07-10 | |||
| US10629277B2 | 2020-04-21 | |||
| US20130107632A1 | 2013-05-02 | |||
| US10622074B2 | 2020-04-14 |
Attorney, Agent or Firm:
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD. (CN)
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