CROSS-REFERENCES TO RELATED APPLICATIONS

[0001] This application claims priority to Indian provisional patent application No. 201841033933 dated September 10, 2018 and entitled“Auto reconfigurable multi-phase voltage regulator”.

FIELD OF THE INVENTION

[0002] The disclosure relates generally to voltage regulators and in particular to devices and methods for regulating voltage.

DESCRIPTION OF THE RELATED ART

[0003] Power management is an essential module of battery-powered devices such as smartphones and tablets. With an effort to integrate more hardware features, number of power supplies required in these devices is growing proportionally. This power supply demand is catered by voltage regulators, which may be linear low-drop out (LDO) regulator or switching dc-dc converter.

[0004] High efficiency over wide range of load current and input/output voltage ratio makes switching dc-dc converter an ideal choice over LDO. However, simpler design and minimum external component count make LDO highly cost effective, thus are always preferred over switching regulator for low current applications. Even though LDOs cater to small portion of overall system power (usually 10% or below), they may still outnumber switching regulators. For instance, a number of LDOs used in power management in a typical mobile device are more than twice the number of switching regulators. This is mainly due to a large number of low power analog modules present in a mobile device. Smaller board space available on a mobile device may limit the number of LDOs, which may be integrated on a single chip. Therefore, it is desirable to have LDO with smaller on/off-chip area. The off-chip area may be reduced by eliminating the external output capacitor which otherwise requires large bandwidth for good transient performance and power supply rejection (PSR).

[0005] Reducing on-chip area with conventional two-stage LDO topology is quite challenging due to large compensation capacitors and a high-gain error amplifier. High gain bandwidth (GBW) for error amplifier increases quiescent current (IQ) consumption and reduces the battery life for always/mostly-ON LDOs. Prior art voltage regulators include digital LDOs (D-LDO) that may have poor power supply rejection affecting the performance. Accuracy of the output in D-LDO is determined by the step size of least significant bit (LSB) hence may often require more than lO-bit resolution to achieve accuracy as good as analog. Increasing the resolution of D/A converter not only complicates the design but also further slows down the loop. Further, D-LDO faces tradeoffs between transient response, output resolution or output voltage ripple.

[0006] Conventional LDOs also suffers from trade-off between power and area. Most of state-of-the art LDOs either consume high quiescent current, large on-chip capacitance or achieve limited bandwidth. Further, prior art LDOs may not operate with wide range of load currents. Also, prior art LDOs may use operational amplifier which suffer from inadequate headroom voltage under low supply voltage conditions.

[0007] A digitally phase locked low dropout voltage regulator apparatus and system using ring oscillators are disclosed in the patent US9870012B2. An area-efficient capacitor-free low-dropout regulator based on a current-feedback frequency compensation technique is disclosed in the patent US7495422B2.The fundamental design requirements for a fully-integrated LDO supplying the digital core of an ultra-low power microcontrollers is disclosed (Luders et ak, “Fully-integrated LDO voltage regulator for digital circuits”, Advances in Radio science, 2011,9;263-267). A low-power fully integrated CMOS Low-Dropout (LDO) voltage regulator for battery-operated portable devices is disclosed (Bailon et ak,“Transient-enhanced Output-Capacitorless CMOS LDO Regulator for Battery-operated Systems”, IEEE , 2017). The present disclosure describes a device and method that overcomes some of the drawbacks of the existing devices.

SUMMARY OF THE INVENTION

[0008] In various embodiments, provided herein is a multi-phase low dropoutdropout (LDO) voltage regulator device. The device includes an output stage (L) having a load circuit. The output stage is configured to receive an input voltage from a power source operative to provide a regulated output voltage based on a load current in the load circuit. Further, the device includes a feedback stage (F). The feedback stage (F) includes a first oscillator configured to receive a unregulated feedback output voltage and generate multiple phase shifted output signals. Further, the feedback stage (F) includes a second oscillator configured to generate a plurality of reference clock signals.

[0009] In various embodiments, the multi-phase low dropout (LDO) voltage regulator device includes a feed forward compensating unit. The compensating unit includes a delay line. Further, the delay line includes a plurality of delay elements configured to shift in time a phase shifted output signal relative to a reference clock signal. In various embodiments, the multi-phase low dropout (LDO) voltage regulator device includes a regulating stage(R). The regulating stage(R) includes a phase selector. Further, the regulating stage includes a plurality of phases configured to be enabled or disabled by the phase selector based on a load current of the output stage.

[0010] In various embodiments, the regulating stage(R) includes a phase frequency detector coupled to each phase. The detector is configured to receive a phase shifted output signal and generate UP and DOWN pulses based on a phase difference between the phase shifted output signal and a reference clock signal. [0011] In various embodiments, the regulating stage(R) includes a charge pump. The charge pump includes an UP current source configured to generate a DC UP current based on the UP pulses from the phase detector and a DOWN current source configured to generate a DC DOWN current based on the DOWN pulses from the phase detector. The charge pump generates a charge pump current based on the DC UP or DC DOWN current;

[0012] In various embodiments, the regulating stage(R) includes a loop filter configured to receive the charge pump current and generate a loop filter voltage based on a net accumulation of charge from the charge pump current. Further, the stage regulating stage (R) includes a pass element controlled by the loop filter voltage. The pass element is configured to output a regulated voltage at the output stage.

[0013] In some embodiments, the feed forward compensating unit includes a plurality of transconductance elements configured to generate a control voltage to regulate the output voltage.

[0014] In various embodiments, provided herein is a multi-phase domino controlled voltage regulator. The multi-phase domino controlled voltage regulator includes a master low dropout (UDO) voltage regulator and a plurality of slave UDO voltage regulators. The master UDO includes an error amplifier configured to generate a voltage error signal responsive to a feedback voltage and a reference voltage. In some embodiments, the error amplifier includes an operational amplifier, transconductance amplifier or a time- based error amplifier.

[0015] In some embodiments, the master UDO includes a voltage regulation circuit configured to generate a voltage regulation signal in response to the error signal to regulate output voltage. In one embodiment, the master UDO voltage regulator is configured to enable a slave UDO when a load current exceeds above a preset threshold value. In some embodiments, the slave UDO voltage regulators are configured to be enabled sequentially by preceding slave LDO when the load current exceeds above a preset threshold value. In some embodiments, the master LDO is configured to provide a regulated output voltage of substantially constant level to a load irrespective of variations in the load current.

[0016] In some embodiments, the time-based error amplifier includes a first oscillator configured to generate multiple phase shifted output signals and a second oscillator configured to generate reference clock signals. Further, the master LDO includes a phase frequency detector. The detector is configured to receive a phase shifted output signal and generate UP and DOWN pulses based on a phase difference between the phase shifted output signal and a reference clock signal. The master LDO includes a charge pump having an UP current source configured to generate a DC UP current based on the UP pulses from the phase detector and a DOWN current source configured to generate a DC DOWN current based on the DOWN pulses from the phase detector. The charge pump generates a charge pump current based on the DC UP and DC DOWN current.

[0017] In various embodiments, the master LDO further includes a loop filter configured to receive the charge pump current and generate a loop filter voltage based on a net accumulation of charge from the charge pump current. The master LDO includes at least one pass element controlled by the loop filter voltage. The pass element is configured to output a regulated voltage at the output stage. In various embodiments, the master LDO further includes a current comparator configured to detect a load current. In one embodiment, when the load current detected by the comparator is above a threshold value, a slave LDO connected at an output of the comparator is enabled.

[0018] In various embodiments, each of the plurality of slave LDOs includes a feed forward transconductor, at least one pass element and a current comparator configured to detect a load current above a threshold value. In some embodiments, when the load current is above the threshold value subsequent slave LDO connected at an output of the corresponding comparator is enabled.

[0019] In various embodiments, the master LDO is configured to be in ON state to regulate the output voltage and the slave LDOs are turned ON or OFF based on a load current. In one embodiment, the slave LDOs are sequentially enabled when the load current is above the threshold value. In another embodiment, the slave LDOs are sequentially disabled when the load current is below the threshold value.

[0020] In various embodiments, provided herein is a method of operating a multi-phase domino controlled voltage regulator including a master low dropout (LDO) voltage regulator, a plurality of slave LDO voltage regulators and an output stage connected to a load. The method includes enabling the master LDO. Further, the method includes sensing a load current of the load. In some embodiments, the method includes enabling or disabling the slave LDOs sequentially based on the load current. In various embodiments, the method includes generating a voltage error signal by the master LDO responsive to a feedback voltage based on the load current and a reference voltage. Further, the method includes generating a voltage regulation signal in response to the error signal by the master LDO and regulating output voltage by the master LDO. In various embodiments, the method includes providing a regulated output voltage of substantially constant level to the load irrespective of changes in the load current.

[0021] In one embodiment, the slave LDOs are enabled sequentially when the load current is above a preset threshold value. In another embodiment, the slave LDOs are disabled sequentially when the load current is below the preset threshold value.

[0022] In various embodiments, provided herein is a method of operating a multi-phase voltage regulator. The method includes providing a multi-phase low dropout (LDO) voltage regulator device including a load circuit at an output stage. Further, the method includes enabling the regulator and sensing a load current. In various embodiments, the method includes enabling or disabling one or more of a plurality of phases of the multi phase LDO regulator based on the load current. In some embodiments, each phase of the plurality of phases is coupled to a phase frequency detector.

[0023] In various embodiments, the method further includes providing an unregulated output voltage as a feedback signal to a first oscillator. Further, the method includes generating multiple phase-shifted signals by the first oscillator and generating a reference clock signal by a second oscillator. In some embodiments, the method includes detecting a phase or time difference between a phase shifted signal and the reference clock signal by the phase frequency detector and generating UP or DOWN pulses based on the difference. Further, the method includes receiving UP or DOWN pulses by a charge pump and generating a UP current based on the UP pulses or a DOWN current based on the DOWN pulses. Each phase of the plurality of phases is coupled to a charge pump.

[0024] In various embodiments, the method includes generating a loop filter voltage based on a net accumulation of charge from the charge pump current. Each phase of the plurality of phases is coupled to a loop filter to receive the charge pump current. Further, the method includes controlling pass elements based on the loop filter voltage for obtaining a regulated output voltage at the output stage of the regulator. Each phase of the plurality of phases is coupled to the pass elements.

[0025] In one embodiment, one or more phases of the regulator are enabled to increase load current. In another embodiment, one or more phases of the regulator are disabled to decrease load current. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The invention has other advantages and features which will be more readily apparent from the following detailed description of the invention and the appended claims, when taken in conjunction with the accompanying drawings, in which:

[0027] FIG. 1A illustrates a multi-phase low dropout voltage regulator.

[0028] FIG. 1B illustrates an embodiment of the multi -phase low dropout voltage regulator with transconductors for feed-forward compensation .

[0029] FIG. 1C illustrates an embodiment of the multi -phase low drop out(LDO) voltage regulator using master-slave domino control.

[0030] FIG. 1D illustrates a circuit diagram of master LDO.

[0031] FIG. 1E illustrates a circuit diagram of slave LDO.

[0032] FIG. 2 illustrates a method of operating the multi-phase LDO regulator .

[0033] FIG. 3 illustrates the number of slave LDOs enabled with respect to load current .

[0034] FIG. 4 illustrates the stability response of the proposed LDO.

[0035] FIG. 5A shows the regulated output voltage with respect to load current.

[0036] FIG. 5B shows the number of slave regulators enabled with respect to load current.

[0037] FIG. 6A illustrates the load transient response of the proposed LDO for output voltages (V ₀ =0.9V, 1.0V and 1.1 V).

[0038] FIG. 6B illustrates the change in load current with respect to time.

[0039] FIG _. 7A illustrates the power supply rejection performance of the proposed LDO.

[0040] FIG. 7B illustrates the signal ripple in supply voltage VDD.

[0041] Referring to the drawings, like numbers indicate like parts throughout the views. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] While the invention has been disclosed with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt to a particular situation or material to the teachings of the invention without departing from its scope.

[0043] Throughout the specification and claims, the following terms take the meanings explicitly associated herein unless the context clearly dictates otherwise. The meaning of "a", "an", and "the" include plural references. The meaning of "in" includes "in" and "on." Referring to the drawings, like numbers indicate like parts throughout the views. Additionally, a reference to the singular includes a reference to the plural unless otherwise stated or inconsistent with the disclosure herein.

[0044] The invention in its various embodiments proposes a multi-phase low dropout (LDO) voltage regulator and a method to regulate the voltage. The regulator is configured to provide better transient response and achieve a high bandwidth with a low quiescent current. The method includes regulating the output voltage automatically according to a load current.

[0045] In various embodiments, a multi-phase low dropout (LDO) voltage regulator 100 as shown in FIG. 1A to regulate an output voltage is disclosed. The regulator 100 includes an output stage L, a feedback stage F and a regulating stage R. The feedback stage F is configured to provide unregulated feedback voltage to the regulating stage R. The regulating stage R is configured to provide a regulated voltage. The output stage L includes a load circuit. Further, the output stage is configured to receive an input voltage from a power source operative to provide a regulated output voltage based on a load current in the load circuit. [0046] In some embodiments, the regulator 100 is a time-based LDO voltage regulator. In various embodiments, the feedback stage F includes a first oscillator 103 configured to receive a feedback voltage based on a load current and generate multiple phase shifted output signals. Further, the feedback stage F includes a second oscillator 101 configured to generate a plurality of reference clock signals. In one embodiment, the first 103 and second oscillators 101 may be a ring oscillator. The feedback stage F includes a feed forward compensating unit 160 including a delay line. The delay line includes a plurality of delay elements Di,D2...D _n configured to shift in time a phase shifted output signal relative to a reference clock signal. In one embodiment, as shown in FIG. 1B, the feed forward compensating unit 160 includes a plurality of transconductance elements. In one embodiment, an op-amp may be used to provide feedback control. Further, the feedback stage may include a current comparator configured to measure a load current.

[0047] In various embodiments, the regulating stage R includes a phase selection unit configured to generate phase select signal in response to an output of the current comparator. In one embodiment, the phase selector may be configured to activate or deactivate one or more phases based on a current sensed by the current comparator.

[0048] In various embodiments, the regulating stage R includes a plurality of phases 150-1, 150-2...150-N configured to be enabled or disabled by the phase selector based on a load current. In some embodiments, each phase of the plurality of phases 150-1,150- 2...150-N is coupled to phase detector 110-1, 110-2..110-N respectively . The detector 110 is configured to receive a phase shifted output signal and generate UP or DOWN pulses based on a phase difference between the phase shifted output signal and a reference clock signal.

[0049] In various embodiments, each phase 150 includes a charge pump 120 configured to receive UP/DOWN pulses from the phase detector 110. In some embodiments, the charge pump 120 includes an UP current source configured to generate a DC UP current based on the UP pulses from the phase detector. Further, the charge pump 120 includes a DOWN current source configured to generate a DC DOWN current based on the DOWN pulses from the phase detector. The charge pump 120 is configured to generate a charge pump current based on the DC UP or DC DOWN current.

[0050] In various embodiments, each phase includes a loop filter 130 configured to receive the charge pump current and generate a loop filter voltage based on a net accumulation of charge from the charge pump current. Further, each phase is coupled to pass element 140 controlled by the loop filter voltage. The pass elements 140-1,140- 2..140-N are configured to output a regulated voltage at the output stage U. In one embodiment, the pass elements 140-1, 140-2..140-N may be a transistor.

[0051] In some embodiments, the voltage regulator 100 may be implemented as a multi-phase domino controlled regulator. The multi-phase domino controlled regulator configuration includes a master low dropout (UDO) voltage regulator 150-1 and a plurality of slave UDO voltage regulators 150-2,150-3.150-N as shown in FIG. 1C. In some embodiments, the slave UDOs 150-2,150-3.150-N are connected in parallel and enabled or disabled sequentially. In various embodiments, the master UDO 150-1 includes an error amplifier configured to generate a voltage error signal responsive to a feedback voltage and a reference voltage. In some embodiments, the error amplifier includes an operational amplifier, transconductance amplifier or a time-based error amplifier.

[0052] In various embodiments, the master UDO 150-1 further includes a voltage regulation circuit configured to generate a voltage regulation signal in response to the error signal to regulate output voltage. The master UDO 150-1 voltage regulator is configured to enable a slave UDO 150-2 when a load current exceeds above a preset threshold value. In one embodiment, the master UDO 150-1 voltage regulator is configured to disable the slave UDO 150-2 when the load current decreases below the preset threshold value. Further, the slave LDO voltage regulators 150-3, 150-4..150-N are connected in parallel and configured to be enabled sequentially by preceding slave LDO when the load current exceeds above a preset threshold value. In some embodiments, the slave LDO voltage regulators 150-3, 150-4..150-N are configured to be disabled sequentially by preceding slave LDO when the load current is below the preset threshold value.

[0053] In some embodiments, the time-based error amplifier includes the first oscillator 103 and the second oscillator 101. Further, the master LDO 150-1 includes phase frequency detector 110, a charge pump 120, a loop filter 130 and at least one pass element 140 for compensating the error voltage. The master LDO 150-1 includes a current comparator 170-1 configured to detect a load current. When the load current detected by the current comparator 170-1 is above a threshold value, a slave LDO 150-2 connected at an output of the current comparator 170-1 is enabled.

[0054] In various embodiments, the master LDO 150-1 is configured to be in ON state and slave LDOs 150-2,150-3.150-N are turned ON or OFF based on the load current.

In various embodiments, the master regulator as shown in FIG. 1D is configured to regulate the voltage.

[0055] In various embodiments, the slave LDO as shown in FIG. 1E includes a feed forward transconductor 160, pass elements 140 and a current comparator 170. The current comparators 170-2, 170-3..or 170-N are configured to detect a load current. In some embodiments, when the load current is above a threshold value, the slave LDOs 150-2, 150-3..150-N are sequentially activated. In another embodiment, when the load current is below the threshold value, the slave LDOs 150-2, 150-3..150-N are sequentially deactivated.

[0056] In one embodiment, dropout voltage ranges between lOOmv to 400mV and a figure of merit is less than or equal to 0.285ps. In some embodiments, the device 100 is configured to provide a power supply rejection (PSR) of 28dB at lMHz. In one embodiment, settling time to attain a regulated output voltage is less than or equal to 200ns. In some embodiments, the device 100 is configured to achieve a bandwidth of at least 3MHz with a quiescent current less than or equal to 11.5mA.

[0057] In various embodiments, a method 200 of operating a multi-phase voltage regulator 100 includes enabling the regulator in step 201. Further, in step 202, the load current or cycle slip in the regulator is determined. One or more phases are enabled or disabled based on the load current or cycle slip in step 203. In step 204, an unregulated output voltage is provided as a feedback signal to a first oscillator. Further, in step 205, multiple phase shifted signals are generated by the first oscillator. A reference clock signal is generated by the second oscillator in step 206. In step 207, phase difference between a phase shifted signal and a reference clock signal is determined by the phase detector. Further, UP or DOWN pulses are generated by the phase detector based on the difference. In step 208, UP or DOWN pulses are received by the charge pump. The charge pump then generates UP current based on the UP pulses and DOWN current based on the down pulses. Further, in step 209, a loop filter voltage is generated based on a net accumulation of charge from the charge pump current. The pass elements are controlled based on the loop filter voltage for obtaining a regulated output voltage in step 210

[0058] In some embodiments, the method 200 in step 203 for the multi-phase domino controlled regulator configuration shown in FIG. 1C includes enabling sequentially one or more slave UDO voltage regulators connected in parallel when the load current is above a threshold value. In another embodiment, the method 200 in step 203 includes disabling sequentially one or more slave UDO voltage regulators connected in parallel when the load current is below the threshold value. [0059] In various embodiments, a method of operating a multi-phase domino controlled voltage regulator includes enabling the master LDO 150-1 and sensing a load current of the load. Further, the method includes enabling or disabling slave LDOs 150-2,150- 3..150-N sequentially based on the load current. In some embodiments, the method includes generating a voltage error signal by the master LDO 150-1 responsive to a feedback voltage based on the load current and a reference voltage. Further, the method includes generating a voltage regulation signal in response to the error signal and regulating output voltage by the master LDO 150-1. In some embodiments, the master LDO 150-1 is configured to provide a regulated output voltage of substantially constant level to the load irrespective of changes in the load current.

[0060] The device and method disclosed here have advantages over existing devices and methods, as the device is configured to achieve high bandwidth with very low quiescent current and smaller area. Since, gates of each pass element (PE) in the device are decoupled from each other, the gate capacitance of each phase is smaller and ensures stable operation. The proposed LDO is a capacitor-less LDO and does not suffer from limit cycle oscillations. Further, the proposed LDO has excellent PSR (power supply rejection) and transient response. The disclosed method includes re-configuring the one or more phases according to a load current for regulating the output voltage.

[0061] While the above is a complete description of the embodiments of the invention, various alternatives, modifications, and equivalents may be used. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention as described above. In addition, many modifications may be made to adapt to a particular situation or material the teachings of the invention without departing from its scope. Therefore, the above description and the examples to follow should not be taken as limiting the scope of the invention, which is defined by the appended claims. EXAMPLES

Example 1: Performance analysis of multi-phase low dropout voltage regulator

[0062] The stability of the proposed multi-phase LDO regulator was verified .A master regulator and one or more slave regulators were designed. Each of the designed slave regulators were configured to handle load current up to lmA . The proposed regulator was verified for a load current ranging between 5mA-5hiA and output capacitance of lpF-lOOpF. The master regulator was kept enabled for load current less than lmA as shown in FIG. 3. It was observed that as the load current increased (more than lmA) one or more slave FDOs were turned ON. It may be observed from FIG. 4 that unity gain bandwidth (UGB) remains between 2.45- 3.8MHz and phase margin is above 59° degrees for all the cases.

[0063] The regulated output voltage with respect to load current is shown in FIG. 5A. Number of slave regulators enabled with respect to load current is shown in FIG. 5B. Slave FDOs start activating one by one as load current goes above lmA as shown in FIG. 5B and all four slave FDOs are turned ON for the load current above 4mA. The effectiveness of slave FDOs may be observed by the output voltage, V ₀ which is regulated at IV throughout the entire load range of 0 to 5 mA.

[0064] Foad transient response for load currents ranging from 100mA-5hiA was determined. Foad transient response at output voltages (V ₀ =0.9V, 1.0V and 1.1 V) as shown in FIG. 6A was simulated by applying a load step of 100mA-5hiA with rise/fall= lOOns as shown in FIG.6 B. The EDO achieves settling time of less than 200ns with undershoot/overshoot of < 62mV/40mV for a minimum output capacitance (lpF).

[0065] Power supply rejection (PSR) performance shown in FIG. 7A was obtained by adding lOOmV pk-to-pk, lMHz signal ripple in supply voltage VDD as shown in FIG. 7B and measuring V ₀ . Approximately 33x attenuation in the ripple at EDO output was observed showing high PSR up to lMHz.