Title:
MULTI-SEQUENCE CONTROL FOR A DATA PARALLEL SYSTEM
Document Type and Number:
WIPO Patent Application WO2008027566
Kind Code:
B1
Abstract:
The present invention is a data parallel system which is able to utilize a very high percentage of processing elements. In an embodiment, the data parallel system includes an array of processing elements and multiple instruction sequencers. Each instruction sequencer is coupled to the array of processing elements by a bus and is able to send an instruction to the array of processing elements. The processing elements are separated into classes and only execute instructions that are directed to their class, although all of the processing elements receive each instruction. In another embodiment, the data parallel system includes an array of processing elements and an instruction sequencer where the instruction sequencer is able to send multiple instructions. Again, the processing elements are separated in classes and execute instructions based on their class.
Inventors:
MITU BOGDAN (US)
STEFAN GHEORGHE (US)
BIVOLARSKI LAZAR (US)
STEFAN GHEORGHE (US)
BIVOLARSKI LAZAR (US)
Application Number:
PCT/US2007/019223
Publication Date:
October 30, 2008
Filing Date:
August 31, 2007
Export Citation:
Assignee:
BRIGHTSCALE INC (US)
MITU BOGDAN (US)
STEFAN GHEORGHE (US)
BIVOLARSKI LAZAR (US)
MITU BOGDAN (US)
STEFAN GHEORGHE (US)
BIVOLARSKI LAZAR (US)
International Classes:
G06F9/30
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