Title:
MULTIPLE INTEGRATION SCHEME WITH ASIC OR FPGA CHIP BONDING TO 3D CROSSPOINT CHIP
Document Type and Number:
WIPO Patent Application WO/2022/077148
Kind Code:
A1
Abstract:
A SSD, method, and integrated architecture with ASIC or FPGA chip bonding to 3D Xpoint chip is disclosed. 3D Xpoint memory cell is introduced into both volatile memory and non-volatile memory systems to reduce circuit area. Registers and on-chip memory (BRAM) in FPGA belong to respective control logic for unnecessary arbitration/caching elimination. FPGA's logical unit connection to surrounding logical units is determined at reprogramming/programming time with no need to communicate through shared memory. Xtacking technology bonds main control ASIC and/or FPGA chip to SSD to reduce circuit area. SRAM Cache is eliminated by this architecture reducing circuit area and the critical path's connection distance, thereby reducing delay and power consumption. Data processing/access speed and efficiency is significantly improved by this integrated architecture. This bonding technology also reduces wiring distance, parasitic RC effect, improves system integration, shortens process manufacturing cycle, reduces PCB board rate, and increases circuit design process window.
Inventors:
LIU JUN (CN)
Application Number:
PCT/CN2020/120322
Publication Date:
April 21, 2022
Filing Date:
October 12, 2020
Export Citation:
Assignee:
YANGTZE ADVANCED MEMORY IND INNOVATION CENTER CO LTD (CN)
International Classes:
H01L27/11514
Foreign References:
| CN110476209A | 2019-11-19 | |||
| US20190326357A1 | 2019-10-24 | |||
| CN106531213A | 2017-03-22 | |||
| CN110192269A | 2019-08-30 |
Attorney, Agent or Firm:
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD. (CN)
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