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Title:
NOVEL FWS DC-AC GRID CONNECTED INVERTER
Document Type and Number:
WIPO Patent Application WO/2020/097586
Kind Code:
A1
Abstract:
A new class of DC-AC inverter consists of a buck or two buck converters and two or four low frequency switches, and it achieves ultra-high efficiency, reactive power flow capability, small size and low cost in grid-connected applications.

Inventors:
CHEN XUE JIAN (CN)
Application Number:
PCT/US2019/060649
Publication Date:
May 14, 2020
Filing Date:
November 08, 2019
Export Citation:
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Assignee:
GUANGDONG REDX ELECTRICAL TECH LIMITED (CN)
CHEN XUE JIAN (CN)
International Classes:
H02M7/48; H02M7/497; H02M7/537
Domestic Patent References:
WO2018144866A12018-08-09
Foreign References:
US9413268B22016-08-09
US20090129134A12009-05-21
Attorney, Agent or Firm:
MA, Jundong (US)
Download PDF:
Claims:
CLAIMS

What is claimed is:

1. An DC-AC inverter apparatus comprising:

a set of one or more buck converters each having a bidirectional cell, said bidirectional cell comprising two switches not connected in serials, with the second switch conducting freewheeling current while the first switch being turned off; and

a set of two low-frequency switches coupled to two respective terminals of an AC source, each low-frequency switch generating a half wave of an AC sinusoidal.

Description:
NOVEL FWS DC-AC GRID CONNECTED INVERTER

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit under 35 U.S.C. § 119(e) of Provisional Patent Application No. 62/757,168, filed November 8, 2018, the entire disclosure of which is hereby incorporated by reference.

RELATED ART

[0002] The present disclosure relates to a DC-AC power inverter, particularly for grid-connected applications. In the past decade, some new power conversion topologies were proposed for grid- connected applications to achieve higher efficiency, lower cost and smaller footprint. The following publications are just some of the latest proposed topologies in this endeavor:

1. S. Dutta and K. Chatterjee, "A Buck and Boost Based Grid Connected PV

Inverter Maximizing Power Yield From Two PV Arrays in Mismatched Environmental Conditions," in IEEE Transactions on Industrial Electronics, vol.

65, no. 7, pp. 5561-5571, July 2018.

2. S. Strache, R. Wunderlich and S. Heinen, "A Comprehensive, Quantitative

Comparison of Inverter Architectures for Various PV Systems, PV Cells, and Irradiance Profiles," in IEEE Transactions on Sustainable Energy, vol. 5, no. 3, pp. 813-822, July 2014.

3. L. Zhou, F. Gao and T. Xu, "A Family of Neutral-Point-Clamped Circuits of

Single-Phase PV Inverters: Generalized Principle and Implementation," in IEEE Transactions on Power Electronics, vol. 32, no. 6, pp. 4307-4319, June 2017.

4. J. F. Ardashir, M. Sabahi, S. H. Hosseini, F. Blaabjerg, E. Babaei and G. B.

Gharehpetian, "A Single-Phase Transformerless Inverter With Charge Pump Circuit Concept for Grid-Tied PV Applications," in IEEE Transactions on Industrial Electronics, vol. 64, no. 7, pp. 5403-5415, July 2017.

5. S. Saridakis, E. Koutroulis and F. Blaabjerg, "Optimization of SiC-Based H5 and

Conergy-NPC Transformerless PV Inverters," in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 3, no. 2, pp. 555-567, June 2015.

6. W. Li, Y. Gu, H. Luo, W. Cui, X. He and C. Xia, "Topology Review and

Derivation Methodology of Single-Phase Transformerless Photovoltaic Inverters for Leakage Current Suppression," in IEEE Transactions on Industrial Electronics, vol. 62, no. 7, pp. 4537-4551, July 2015. 7. Y. Zhou, W. Huang, P. Zhao and J. Zhao, "A Transformerless Grid-Connected Photovoltaic System Based on the Coupled Inductor Single-Stage Boost Three- Phase Inverter," in IEEE Transactions on Power Electronics, vol. 29, no. 3, pp.

1041-1046, March 2014.

8. L. Zhang, K. Sun, Y. Xing and M. Xing, "H6 Transformerless Full-Bridge PV

Grid-Tied Inverters," in IEEE Transactions on Power Electronics, vol. 29, no. 3, pp. 1229-1238, March 2014.

[0003] All of the above-listed publications are hereby incorporated by reference in their respective entireties.

[0004] In the meantime, a wide range of power conversion topologies can also be found in a number of patent documents. Below is a exemplary list of those U.S patent documents.

Exemplary U.S. Patent Documents

8,369,113 B2 02/2013 Rodriguez

8,582,331 B2 11/2013 Frisch et al.

8,971,082 B2 03/2015 Rodriguez

9,071,141 B2 06/2015 Dong et al.

9,093,897 B1 06/2015 Weng et al.

9,148,072 B2 09/2015 Ueki et al.

9,318,974 B2 04/2016 Yoscovich et al.

9,413,268 B2 08/2016 Fu et. al

9,584,044 B2 02/2017 Zhou et al.

9,627,995 B2 04/2017 Ayai

9,641,098 B2 05/2017 Fu et al.

9,692,321 B2 06/2017 Hu et al.

9,806,529 B2 10/2017 Fu

9,806,637 B2 10/2017 Fu

9,812,985 B2 11/2017 Rodriguez 9,831,794 B2 11 /2017 Rodriguez

9,866,147 B2 01/2018 Kidera et al

9,871,436 B 1 01/2018 Jiao et al.

9,941,813 B2 04/2018 Yoscovich

10,008,858 B2 06/2018 Garrity

10,033,292 B2 07/2018 Rodriguez

[0005] All of the above-listed exemplary U.S. patent documents are hereby incorporated by reference in their respective entireties.

[0006] Prevailing power conversion topologies, including, e.g., those discussed in, e.g., U.S. Pat. No. 8,369,113, U.S. Pat. No. 9,941,813, U.S. Pat. No. 10,008,858, and U.S. Pat. No. 10,033,292, which are just some of the examples, in Applicant’s view, are still in need of improvement in terms of performance. First, many prevailing inverter topologies has limitation in regards to reducing switching losses, thereby causing each to have output inductor L and passive components that are large in size.

[0007] In this aspect, there are a few classes of grid-connected inverter topologies, namely, isolated and none-isolated inverters, mid-frequency (MF) (10 KHz-30 KHz), high frequency (HF) (above 100 KHz) or HF with low frequency (LF) switches inverter topologies. FIGS. 2B, 2C, 2F, 2J illustrate a few MF inverters. The ability of MF inverters to reduce switching losses is limited due to its MF switching frequencies. However, due to its limitation in reducing switching losses, such a MF inverter’s output inductor L and passive components are relatively large in size, which is undesirable. FIGS. 2G, 21 are MF inverters with LF switches. Those inverter topologies are still limited in terms of controlling its switching losses with its MF switching frequency. As a result, such a inverter topology still sees its output inductor L and passive components large in size.

[0008] Second, many prevailing inverter topologies has limitation in regards to having reactive power flow capability. For those grid-connected inverter topologies, achieving reactive power flow while connecting the grid is, however, desirable. Inverters with the topologies illustrated in FIGS. 2A, 2E and 2K, can be operated in HF with LF switches. As a result, for such an inverter, its output inductor L can be smaller and higher efficiency can be achieved, thus being relatively okay with the above-discussed first aspect. However, those topologies do not have reactive power flow capability, therefore limiting them to work at unity power generation only.

[0009] Reactive power flow capability is seen as a very important feature for today’s inverter technology. FIG. 1E shows three configurations of power stage cells. Configuration (A) is unidirectional cell, whose configuration is used in the topologies illustrated in FIGS. 2E and 2K. A skilled artisan readily appreciates and recognizes that this configuration can only supports unidirectional current flow, thus being incapable of having reactive power flow.

[0010] Continuing with the discussion on FIG. 1E, configuration (B) of a power stage cell is a conventional half bridge configuration, which supports bidirectional current flow that may include reactive power flow. It is worth noting that this configuration is used in almost all other conventional topologies. Although this bidirectional configuration is easy to be applied in IGBT type’s inverter circuit, the associated operation switching frequency is limited. For a modern power semiconductor device such as a MOSFET, higher switching operational frequency is possible. However, due to that high voltage devices have slow recovery times on a body diode of such a semiconductor device, resulting in an inverter suffering from excess switching losses that otherwise can be avoided or reduced. As result, a MOSFET operating in configure (B) has a potential problem of being conducted in shoot-through, causing the inverter to break down.

[0011] Accordingly, there is a need to improve the above-discussed undesirable problems existed in the conventional power conversion topologies.

BRIEF SUMMARY

[0012] In one aspect, the presently disclosed novel conversation topologies, as generally illustrated in FIG. 1(A), comprises one or two buck converter(s). Under the presently disclosed conversion topologies, soft switching can be readily achieved, which is in contrast to H bridge or half bridge configurations. During each half cycle of a conduction period, there are two switches in the respective conduction path, which is in contrast to other topologies (where there might have been three or more switches connected in series). As a result, a better efficiency can be achieved, thereby improving on the size of the associated output inductor L and passive components.

[0013] In another aspect, under the presently disclosed conversion topologies, each set of output terminals receives low-frequency half wave signals. Thus, undesirable high frequency leakage current is minimized. [0014] In yet another aspect, under the presently disclosed configuration (C) illustrated in FIG. 1E, the involved switches are not connected in series as of the same phase leg. Thus, the slow body diode does not conduct current, thereby resulting in the power stage to not have a shoot-through issue, while having the capability of reactive power flow. On the other hand, the coupled inductor and the switch Tl causes the power stage to work equivalent to a half bridge power stage, which is bidirectional. Since there is no two power devices are connected in series, the body diode reverse recovery issue can be avoided. The switch Tl works in ZVS (zero voltage switching) mode, resulting in switching loss being small. This then also improves the aspect of the size of the associated output inductor L and passive components.

[0015] The above summary contains simplifications, generalizations and omissions of detail and is not intended as a comprehensive description of the claimed subject matter but, rather, is intended to provide a brief overview of some of the functionality associated therewith. Other systems, methods, functionality, features and advantages of the claimed subject matter will be or will become apparent to one with skill in the art upon examination of the following figures and detailed written description.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The description of the illustrative embodiments can be read in conjunction with the accompanying figures. It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures, unless expressly specified, have not necessarily been drawn to scale. Also, any text and/or any numerical data (numbers) appeared on any drawing figures is provided to illustrate an exemplary embodiment or implementation, and thus is provided for the purpose of illustration and not for the purpose of limitation. For example, the dimensions of some of the elements may be exaggerated relative to other elements. Embodiments incorporating teachings of the present disclosure are shown and described with respect to the figures presented herein, in which:

[0017] FIG. 1A illustrates general form of the presently disclosed DC-AC inverter.

[0018] FIGS. 1B and 1C show exemplary choices of the buck converter shown in FIG. 1A.

[0019] FIG. 1D illustrates an example of the presently disclosed DC-AC Inverter with one buck converter and four low frequency switches. [0020] FIG. 1E illustrates comparisons among unidirectional and bidirectional cell configurations.

[0021] FIGS. 2A-2K illustrate respective conversion topologies in the related art.

[0022] FIG. 3A illustrates an example of the presently disclosed DC-AC Inverter with two buck converters and two low frequency switches.

[0023] FIG. 3B depicts exemplary timing diagrams in connection with the modulation strategy of the presently disclosed DC-AC converter for FIG. 3A.

[0024] FIGS. 3C-D illustrate exemplary timing diagrams in connection with modulating timing for the presently disclosed DC-AC converter for FIG. 3A.

[0025] FIGS. 4A-4D illustrate four respective operation modes for the presently disclosed DC-AC converter for FIG. 3A, including exemplary respective timing diagrams associated with four operation modes.

[0026] FIG. 4E illustrates an example of the presently disclosed DC-AC Inverter receiving reactive power flow from a large inductor series or large capacitor parallel with Vac.

[0027] FIG. 4F and 4G illustrate exemplary respective timing diagrams in connection with how the presently disclosed DC-AC Inverter handles reactive power flow from an exemplary inductive load and an exemplary capacitive load.

DETAILED DESCRIPTION

[0028] In the following detailed description of exemplary embodiments of the disclosure in this section, specific exemplary embodiments in which the disclosure may be practiced are described in sufficient detail to enable those skilled in the art to practice the disclosed embodiments. However, it is to be understood that the specific details presented need not be utilized to practice embodiments of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims and equivalents thereof.

[0029] References within the specification to “one embodiment,” “an embodiment,” “embodiments”, or“one or more embodiments” are intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. The appearance of such phrases in various places within the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Further, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms“a”,“an” and“the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Moreover, the use of the terms first, second, etc. do not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another.

[0031] Those of ordinary skill in the art will appreciate that the components and basic configuration depicted in the following figures may vary. Other similar or equivalent components may be used in addition to or in place of the components depicted. A depicted example is not meant to imply limitations with respect to the presently described one or more embodiments and/or the general disclosure.

[0032] The presently disclosed DC-AC converter is illustrated in general form in FIG. 1A, comprising two buck converters and two low frequency switches. Referring to FIG. 1A, the DC source can be photovoltaic arrays, batteries, fuel cells or others. The AC source can be utility grid, single-phase electric motors or others. Each front converter can be any unidirectional converter that can generate half sinusoidal waveform at the frequency of the connected AC source, including but not limited to a classic unidirectional buck converter (shown FIG. 1B) and a three-level bidirectional buck converter (shown in FIG. 1C) or any other kind of buck converter. The two converters can be identical, or combinations of any buck converters.

[0033] FIG. 3A shows a presently disclosed DC-AC converter with classic buck converter configured with bidirectional cell as an example for description. One possible modulation strategy is depicted in FIGS. 3B-D, together with AC voltage and current waveforms. Four possible operation modes of the presently disclosed inverter in unity power generation with the described modulation strategy are respectively demonstrated in FIGS. 4A-4D.

[0034] For reactive power generation mode in connection with the presently disclosed topologies, FIGS. 4E-4G provide an exemplary configuration diagram and examples of reactive power flow associated with the exemplary configuration, respectively.

[0035] Mode 1

[0036] Referring to FIG. 4A and FIG. 3B, during this mode, T3 operates in PWM in generating an AC waveform using known general configurations that involves one or more suitable inductors and one or more suitable capacitors. T2 works as a low frequency switch. The converter generates half wave AC at point“A”, while Tl and T4 are off. Accordingly, power transfers from the DC source to inductors Ll to output capacitor C3 and the AC source. As a result, half wave of the AC sinusoidal is generated crosses AC source. As indicated in the timing diagrams, T5, which works simultaneously with T3 and is coupled to L3, conducts the freewheeling current through forward- biased Dl (otherwise reversed-biased during T3 ON periods) during T3 OFF periods.

[0037] Mode 2

[0038] Referring to FIG. 4B and FIG. 3B, during this mode, which can also be appreciated as a specific sub-mode during Mode 1, T2 and Dl are ON, while Tl, T3 and T4 are OFF and T5 is ON. Power transfers from the inductors Ll, L3. capacitor C3 to the AC source. Dl keeps the freewheeling current flow of the inductor Ll due to T5 being on, with inductor L3, which is coupled to T5, engaging T5 to connect the freewheeling current as well.

[0039] Mode 3

[0040] Referring to FIG. 4C and FIG. 3D, this mode mirrors Mode 1, except for generating the other half wave of the AC sinusoidal. Thus, as a skilled artisan readily appreciate, the operation of Mode 3 corresponds with the operation of Mode 1, except for that the other low-frequency Tl is ON, T4 operates in PWM, while the corresponding switches of Tl and T4, namely, T2 and T3, are off. Thus, power transfers from the DC source to inductor L2 (which corresponds to Ll) to output capacitor C4 (which corresponds to C3) and the AC source. As a result, the other half wave of the AC sinusoidal is generated crosses AC source. As indicated in the timing diagrams, T6 (which corresponds with T5), which works simultaneously with T4 and is coupled to L4, conducts the freewheeling current through forward-biased D2 (otherwise reversed-biased during T4 ON periods) during T4 OFF periods.

[0041] Mode 4

[0042] Referring to FIG. 4D and FIG. 3D, this mode mirrors Mode 2, except for generating the other half wave of the AC sinusoidal. Thus, Mode 4 can also be appreciated as a specific sub-mode during Mode 3. Accordingly, during this mode, Tl and D2 are ON, while T2, T3 and T4 are OFF and T6 is ON. Power transfers from the inductors L2, L4. capacitor C4 to the AC source. D2 keeps the freewheeling current flow of the inductor L2 due to T6 being on, with inductor L4, which is coupled to T6, engaging T6 to connect the freewheeling current as well.

[0043] Reactive power flow mode

[0044] Referring to FIGS. 4E, 4F and 4G, during this mode, load (AC source) is reactive, with either inductive load (lagging) or capacitive load (leading). As indicated in FIGS. 4F and 4G, the output current is out of phase with the output voltage, the coupled inductor Ll and L3, L2 and L4 engage the freewheeling current flow during the intervals when T5 and T4 are on. And with the didoes D1 and D2 of the combination conducting the current, the bidirectional current flow is established. See Iacl and Iac2 in FIGS. 4F and 4G. Those currents travel in two directions, showing the bidirectional current flow.

[0045] In summary, during the positive sinusoidal cycle ( v ac > 0), Tl remains off and T2 remains on. T3, Dl and T5 turn on and off in a complementary way to generate required current i ac \, whereas T4 and D2 remain off. For the negative sinusoidal cycle ( v ac < 0), Tl remains on and T2 remains off. T4, D2 and T6 turn on and off in a complementary way to generate required current iac2, whereas T3 and Dl remain off.

[0046] While the disclosure has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular system, device or component thereof to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the disclosure not be limited to the particular embodiments disclosed for carrying out this disclosure.