Title:
PACKAGED POWER SEMICONDUCTOR AND MOUNTED STRUCTURE OF PACKAGED POWER SEMICONDUCTORS
Document Type and Number:
WIPO Patent Application WO/2016/092938
Kind Code:
A1
Abstract:
This packaged power semiconductor (10) is provided with: a power semiconductor chip (20); a lead frame (31) having a surface on which the power semiconductor chip (20) is mounted; a heat dissipation substrate (50) that is in contact with the back surface of the lead frame (31); and an insulating mold resin (60). The insulating mold resin (60) has a back surface from which the heat dissipation substrate (50) is exposed, and has a shape that covers the power semiconductor chip (20) and a portion where the power semiconductor chip (20) is connected to the lead frame (31). In addition, the insulating mold resin (60) comprises a wall (61) that is at right angles to the back surface of the insulating mold resin (60) and is on the outer side of the back surface of the heat dissipation substrate (50). The front end surface of the wall (61) is provided with a projection (62). The packaged power semiconductor (10) is mounted on a heat dissipation member (80) by means of an insulating bonding member (90) in such a manner that the projection (62) abuts on the heat dissipation member (80).
Inventors:
KASHIURA HIDEAKI (JP)
Application Number:
PCT/JP2015/077656
Publication Date:
June 16, 2016
Filing Date:
September 30, 2015
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01L23/28; H01L23/36; H01L25/07; H01L25/18
Foreign References:
| JPH11220075A | 1999-08-10 | |||
| JP2008251795A | 2008-10-16 | |||
| JPH09260550A | 1997-10-03 |
Attorney, Agent or Firm:
Kaede Patent Attorneys' Office (JP)
Patent business corporation Kaede Patent Attorneys' Office (JP)
Patent business corporation Kaede Patent Attorneys' Office (JP)
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