Title:
PARASITIC CAPACITANCE MEASUREMENT METHOD, AND MEMORY AND READABLE STORAGE MEDIUM
Document Type and Number:
WIPO Patent Application WO/2022/077979
Kind Code:
A1
Abstract:
Provided are a parasitic capacitance measurement method, a memory and a readable storage medium, which relate to the technical field of semiconductors. The measurement method comprises: providing a plurality of semiconductor devices for testing, wherein the numbers of source electrodes, drain electrodes, active layers, gate electrodes and wires in the semiconductor devices and the sectional areas of the wires are the same, and the lengths of the wires in the semiconductor devices are different from each other; according to a plurality of total capacitance values of the plurality of semiconductor devices and the lengths of the plurality of wires, determining the capacitance between a wire of a unit length and the gate electrode in the semiconductor device, wherein the capacitance between the wire of the unit length and the gate electrode is parasitic capacitance of the unit length; determining the length of a corresponding wire in a semiconductor device to be tested; and according to the parasitic capacitance of the unit length and the length of the corresponding wire in said semiconductor device, determining the parasitic capacitance of said semiconductor device. By means of the technical solution of the present application, a parasitic capacitor with relatively high measurement precision can be obtained.
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Inventors:
QIAN SHIBING (CN)
Application Number:
PCT/CN2021/106511
Publication Date:
April 21, 2022
Filing Date:
July 15, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/66; G01R27/26; G11C29/50
Foreign References:
| CN101770965A | 2010-07-07 | |||
| CN107290594A | 2017-10-24 | |||
| CN205749689U | 2016-11-30 | |||
| US20030122123A1 | 2003-07-03 | |||
| US20170242065A1 | 2017-08-24 |
Attorney, Agent or Firm:
BEIJING LINKAW PATENT ATTORNEY LAW FIRM (CN)
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