Title:
PATTERN DEFECT INSPECTING APPARATUS AND METHOD
Document Type and Number:
WIPO Patent Application WO/2010/021214
Kind Code:
A1
Abstract:
In recent years, a semiconductor manufacturing process is required to shorten the inspecting time of a wafer so as to shorten a manufacturing time and to discover a production yield lowering factor early. For this requirement, it is necessary to shorten not only the time period for an actual inspection but also the time period for setting an inspection condition. By using the fluctuation information of the speed or position of a transfer line (2), the storing time or the operation speed of a detector is controlled, or an acquired image is corrected to perform the inspection even at the acceleration and deceleration of the transfer line (2). The display of the observed image of a detected portion is switched for a preset time so that the visibility of the detected portion is improved to confirm the existence of a defect for a short time.
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Inventors:
NISHIYAMA HIDETOSHI (JP)
ITO MASAAKI (JP)
UTO SACHIO (JP)
SHIMURA KEI (JP)
ITO MASAAKI (JP)
UTO SACHIO (JP)
SHIMURA KEI (JP)
Application Number:
PCT/JP2009/062770
Publication Date:
February 25, 2010
Filing Date:
July 08, 2009
Export Citation:
Assignee:
HITACHI HIGH TECH CORP (JP)
NISHIYAMA HIDETOSHI (JP)
ITO MASAAKI (JP)
UTO SACHIO (JP)
SHIMURA KEI (JP)
NISHIYAMA HIDETOSHI (JP)
ITO MASAAKI (JP)
UTO SACHIO (JP)
SHIMURA KEI (JP)
International Classes:
G01N21/956; H01L21/66
Foreign References:
| JP2003329610A | 2003-11-19 | |||
| JPH10275221A | 1998-10-13 | |||
| JPH10274508A | 1998-10-13 |
Attorney, Agent or Firm:
INOUE, Manabu (6-1, Marunouchi 1-chome, Chiyoda-ku, TOKYO 20, JP)
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