Title:
PATTERNING METHOD AND SEMICONDUCTOR STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2022/205739
Kind Code:
A1
Abstract:
A patterning method and a semiconductor structure. The patterning method comprises the following steps: providing a substrate, the substrate comprising an array area (AA) and an adjacent peripheral area (PA); forming on the substrate a pattern transfer layer (100) having a plurality of first hard masks (180), the first hard masks (180) extending along a first direction (D1) and arranged at intervals; forming a barrier layer (200) on the pattern transfer layer (100); forming on the barrier layer (200) a plurality of second hard masks (400) extending along a second direction (D2), the second hard masks (400) being arranged at intervals; a second hard mask (400) is located in the array area (AA) and has a structural defect at a location close to the peripheral area (PA); forming a first buffer layer (310) on the barrier layer (200), the first buffer (310) filling a second hard mask (400) having a structural defect, and an orthographic projection of the first buffer layer (310) coinciding with the peripheral area (PA) and the array area (AA); and patterning the barrier layer (200) and the pattern transfer layer (100) using the first buffer layer (310) and a second hard mask (400) not filled by the first buffer layer (310) as a mask.
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Inventors:
WAN QIANG (CN)
XIA JUN (CN)
ZHAN KANGSHU (CN)
LI SEN (CN)
LIU TAO (CN)
XU PENGHUI (CN)
XIA JUN (CN)
ZHAN KANGSHU (CN)
LI SEN (CN)
LIU TAO (CN)
XU PENGHUI (CN)
Application Number:
PCT/CN2021/112608
Publication Date:
October 06, 2022
Filing Date:
August 13, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/8242; H01L27/108
Foreign References:
CN113097142A | 2021-07-09 | |||
CN109767977A | 2019-05-17 | |||
CN106252507A | 2016-12-21 | |||
CN108597992A | 2018-09-28 | |||
US10395976B1 | 2019-08-27 |
Attorney, Agent or Firm:
BEIJING INTELLEGAL INTELLECTUAL PROPERTY AGENT LTD. (CN)
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