REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Patent Cooperation Treaty Application No. PCT/CN2016/098912 filed September 1 3, 2016, entitled "PHASE NOISE

COMPENSATION FOR SC-FDMA WAVEFORM" and U.S. Provisional Application No. 62/360,043 filed July 8, 2016, entitled "TIME DOMAIN REFERENCE SIGNAL OF OFDM-BASED SINGLE CARRIER WAVEFORMS FOR PHASE NOISE TRACKING AND MITIGATION IN MILLIMETER-WAVE SYSTEMS", the contents of which are herein incorporated by reference in their entirety.

FIELD

[0002] The present disclosure relates to wireless technology, and more specifically to techniques for compensating for phase noise, for example, in millimeter-wave wireless systems.

BACKGROUND

[0003] For 5G system operating in the millimeter-wave range, the phase noise in oscillators can result from frequency synthesizers which can comprise a reference clock, VCO (Voltage Controlled Oscillator), loop filter, PLL (Phase Locked Loop), etc. In millimeter-wave communication systems, the phase noise level of these frequency synthesizers can be significantly higher than that of traditional wireless systems in the UHF and microwave bands.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 is a block diagram illustrating an example user equipment (UE) useable in connection with various aspects described herein.

[0005] FIG. 2 is a diagram illustrating example components of a device that can be employed in accordance with various aspects discussed herein.

[0006] FIG. 3 is a diagram illustrating example interfaces of baseband circuitry that can be employed in accordance with various aspects discussed herein.

[0007] FIG. 4 is a block diagram illustrating a system employable at a UE (User

Equipment) that facilitates phase noise compensation, according to various aspects described herein. [0008] FIG. 5 is a block diagram illustrating a system employable at a BS (Base Station) that facilitates phase noise compensation, according to various aspects described herein.

[0009] FIG. 6 is a pair of diagrams illustrating phase noise power spectral density (PSD) and its impact on constellations, in connection with various aspects discussed herein.

[0010] FIG. 7 is a diagram illustrating a conventional time domain TRS (Tracking

Reference Signal) technique for the SC-FDMA or pure SC waveforms.

[0011] FIG. 8 is a diagram illustrating simultaneous PUCCH (Physical Uplink Control

Channel) and PUSCH (Physical Uplink Shared Channel) transmission in LTE (Long

Term Evolution), in connection with various aspects discussed herein.

[0012] FIG. 9 is a diagram illustrating a first example TRS pattern employing different cyclic shifts for TRS for different users, according to various aspects discussed herein.

[0013] FIG. 10 is a diagram illustrating a first example TRS pattern employing different frequency resources for TRS for different users, according to various aspects discussed herein.

[0014] FIG. 11 is a pair of diagrams illustrating the PAPR (Peak-to-Average Power Ratio) CCDF (Complementary Cumulative Distribution Function) curves of different TRS sequences based on a SC (Single Carrier)-FDMA (Frequency Division Multiple Access) waveform (with TRS and PUSCH contiguous or non-contiguous), according to various aspects discussed herein.

[0015] FIG. 12 is a diagram illustrating three example resource allocations for PDCH and TRS, according to various aspects discussed herein.

[0016] FIG. 13 is a diagram illustrating one example of shared TRS frequency resources for two UEs, according to various aspects described herein.

[0017] FIG. 14 is a diagram illustrating an example of TRS resource allocation in the central RBs (Resource Blocks), according to various aspects discussed herein.

[0018] FIG. 15 is a diagram illustrating BLER (Block Error Rate) for different compensation techniques (or no compensation) in addressing phase noise compared to an ideal scenario involving no phase noise, according to various aspects discussed herein.

[0019] FIG. 16 is a flow diagram of an example method employable at a transmitting communication device that facilitates phase noise compensation based on TRS

(Tracking Reference Signals), according to various aspects discussed herein. [0020] FIG. 17 is a flow diagram of an example method employable at a receiving communication device that facilitates phase noise compensation based on TRS

(Tracking Reference Signals), according to various aspects discussed herein.

[0021] FIG. 18 is a pair of diagrams illustrating two phase noise processes for two distinct models, according to various aspects discussed herein.

[0022] FIG. 19A is a diagram illustrating generation of an OFDM-based single carrier waveform, in connection with various aspects discussed herein.

[0023] FIG. 19B is a diagram illustrating generation of an OFDM-based single carrier waveform comprising samples of a time trackable training sequence, in connection with various aspects discussed herein.

[0024] FIG. 20 is a diagram illustrating a graph comparing the performance of a SC- FDMA waveform in an ideal scenario involving no phase noise to two phase noise compensation techniques according to various aspects discussed herein.

[0025] FIG. 21 is a diagram illustrating a graph comparing the performance of a SC- FDMA waveform in an ideal scenario involving no phase noise to phase noise compensation techniques involving variations in sequence length and spacing for reference symbols, according to various aspects discussed herein.

[0026] FIG. 22 is a flow diagram of an example method employable at a transmitting communication device that facilitates phase noise compensation based on a time- domain training sequence, according to various aspects discussed herein.

[0027] FIG. 23 is a flow diagram of an example method employable at a receiving communication device that facilitates phase noise compensation based on a time- domain training sequence, according to various aspects discussed herein.

DETAILED DESCRIPTION

[0028] The present disclosure will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale. As utilized herein, terms "component," "system," "interface," and the like are intended to refer to a computer-related entity, hardware, software (e.g., in execution), and/or firmware. For example, a component can be a processor (e.g., a microprocessor, a controller, or other processing device), a process running on a processor, a controller, an object, an executable, a program, a storage device, a computer, a tablet PC and/or a user equipment (e.g., mobile phone, etc.) with a processing device. By way of illustration, an application running on a server and the server can also be a component. One or more components can reside within a process, and a component can be localized on one computer and/or distributed between two or more computers. A set of elements or a set of other components can be described herein, in which the term "set" can be interpreted as "one or more."

[0029] Further, these components can execute from various computer readable storage media having various data structures stored thereon such as with a module, for example. The components can communicate via local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network, such as, the Internet, a local area network, a wide area network, or similar network with other systems via the signal).

[0030] As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, in which the electric or electronic circuitry can be operated by a software application or a firmware application executed by one or more processors. The one or more processors can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts; the electronic components can include one or more processors therein to execute software and/or firmware that confer(s), at least in part, the functionality of the electronic components.

[0031] Use of the word exemplary is intended to present concepts in a concrete fashion. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied under any of the foregoing instances. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Furthermore, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term

"comprising." Additionally, in situations wherein one or more numbered items are discussed (e.g., a "first X", a "second X", etc.), in general the one or more numbered items may be distinct or they may be the same, although in some situations the context may indicate that they are distinct or that they are the same.

[0032] As used herein, the term "circuitry" may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. In some embodiments, the circuitry may be implemented in, or functions associated with the circuitry may be implemented by, one or more software or firmware modules. In some embodiments, circuitry may include logic, at least partially operable in hardware.

[0033] Embodiments described herein may be implemented into a system using any suitably configured hardware and/or software. FIG. 1 illustrates an architecture of a system 1 00 of a network in accordance with some embodiments. The system 100 is shown to include a user equipment (UE) 101 and a UE 102. The UEs 101 and 102 are illustrated as smartphones (e.g., handheld touchscreen mobile computing devices connectable to one or more cellular networks), but may also comprise any mobile or non-mobile computing device, such as Personal Data Assistants (PDAs), pagers, laptop computers, desktop computers, wireless handsets, or any computing device including a wireless communications interface.

[0034] In some embodiments, any of the UEs 101 and 102 can comprise an Internet of Things (loT) UE, which can comprise a network access layer designed for low-power loT applications utilizing short-lived UE connections. An loT UE can utilize technologies such as machine-to-machine (M2M) or machine-type communications (MTC) for exchanging data with an MTC server or device via a public land mobile network (PLMN), Proximity-Based Service (ProSe) or device-to-device (D2D) communication, sensor networks, or loT networks. The M2M or MTC exchange of data may be a machine-initiated exchange of data. An loT network describes interconnecting loT UEs, which may include uniquely identifiable embedded computing devices (within the Internet infrastructure), with short-lived connections. The loT UEs may execute background applications (e.g., keep-alive messages, status updates, etc.) to facilitate the connections of the loT network.

[0035] The UEs 101 and 102 may be configured to connect, e.g., communicatively couple, with a radio access network (RAN) 1 10— the RAN 1 10 may be, for example, an Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN), a NextGen RAN (NG RAN), or some other type of RAN. The UEs 101 and 102 utilize connections 103 and 104, respectively, each of which comprises a physical communications interface or layer (discussed in further detail below); in this example, the connections 103 and 104 are illustrated as an air interface to enable communicative coupling, and can be consistent with cellular communications protocols, such as a Global System for Mobile Communications (GSM) protocol, a code-division multiple access (CDMA) network protocol, a Push-to-Talk (PTT) protocol, a PTT over Cellular (POC) protocol, a Universal Mobile Telecommunications System (UMTS) protocol, a 3GPP Long Term Evolution (LTE) protocol, a fifth generation (5G) protocol, a New Radio (NR) protocol, and the like.

[0036] In this embodiment, the UEs 101 and 1 02 may further directly exchange communication data via a ProSe interface 105. The ProSe interface 105 may

alternatively be referred to as a sidelink interface comprising one or more logical channels, including but not limited to a Physical Sidelink Control Channel (PSCCH), a Physical Sidelink Shared Channel (PSSCH), a Physical Sidelink Discovery Channel (PSDCH), and a Physical Sidelink Broadcast Channel (PSBCH).

[0037] The UE 102 is shown to be configured to access an access point (AP) 106 via connection 107. The connection 107 can comprise a local wireless connection, such as a connection consistent with any IEEE 802.1 1 protocol, wherein the AP 106 would comprise a wireless fidelity (WiFi®) router. In this example, the AP 1 06 is shown to be connected to the Internet without connecting to the core network of the wireless system (described in further detail below).

[0038] The RAN 1 1 0 can include one or more access nodes that enable the connections 1 03 and 104. These access nodes (ANs) can be referred to as base stations (BSs), NodeBs, evolved NodeBs (eNBs), next Generation NodeBs (gNB), RAN nodes, and so forth, and can comprise ground stations (e.g., terrestrial access points) or satellite stations providing coverage within a geographic area (e.g., a cell). The RAN 1 1 0 may include one or more RAN nodes for providing macrocells, e.g., macro RAN node 1 1 1 , and one or more RAN nodes for providing femtocells or picocells (e.g., cells having smaller coverage areas, smaller user capacity, or higher bandwidth compared to macrocells), e.g., low power (LP) RAN node 1 12.

[0039] Any of the RAN nodes 1 1 1 and 1 12 can terminate the air interface protocol and can be the first point of contact for the UEs 101 and 102. In some embodiments, any of the RAN nodes 1 1 1 and 1 12 can fulfill various logical functions for the RAN 1 1 0 including, but not limited to, radio network controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management and data packet scheduling, and mobility management.

[0040] In accordance with some embodiments, the UEs 101 and 102 can be configured to communicate using Orthogonal Frequency-Division Multiplexing (OFDM) communication signals with each other or with any of the RAN nodes 1 1 1 and 1 1 2 over a multicarrier communication channel in accordance various communication techniques, such as, but not limited to, an Orthogonal Frequency-Division Multiple Access (OFDMA) communication technique (e.g., for downlink communications) or a Single Carrier Frequency Division Multiple Access (SC-FDMA) communication technique (e.g., for uplink and ProSe or sidelink communications), although the scope of the embodiments is not limited in this respect. The OFDM signals can comprise a plurality of orthogonal subcarriers.

[0041] In some embodiments, a downlink resource grid can be used for downlink transmissions from any of the RAN nodes 1 1 1 and 1 12 to the UEs 101 and 1 02, while uplink transmissions can utilize similar techniques. The grid can be a time-frequency grid, called a resource grid or time-frequency resource grid, which is the physical resource in the downlink in each slot. Such a time-frequency plane representation is a common practice for OFDM systems, which makes it intuitive for radio resource allocation. Each column and each row of the resource grid corresponds to one OFDM symbol and one OFDM subcarrier, respectively. The duration of the resource grid in the time domain corresponds to one slot in a radio frame. The smallest time-frequency unit in a resource grid is denoted as a resource element. Each resource grid comprises a number of resource blocks, which describe the mapping of certain physical channels to resource elements. Each resource block comprises a collection of resource elements; in the frequency domain, this may represent the smallest quantity of resources that currently can be allocated. There are several different physical downlink channels that are conveyed using such resource blocks.

[0042] The physical downlink shared channel (PDSCH) may carry user data and higher-layer signaling to the UEs 101 and 102. The physical downlink control channel (PDCCH) may carry information about the transport format and resource allocations related to the PDSCH channel, among other things. It may also inform the UEs 101 and 102 about the transport format, resource allocation, and H-ARQ (Hybrid Automatic Repeat Request) information related to the uplink shared channel. Typically, downlink scheduling (assigning control and shared channel resource blocks to the UE 102 within a cell) may be performed at any of the RAN nodes 1 1 1 and 1 12 based on channel quality information fed back from any of the UEs 101 and 102. The downlink resource assignment information may be sent on the PDCCH used for (e.g., assigned to) each of the UEs 101 and 1 02.

[0043] The PDCCH may use control channel elements (CCEs) to convey the control information. Before being mapped to resource elements, the PDCCH complex-valued symbols may first be organized into quadruplets, which may then be permuted using a sub-block interleaver for rate matching. Each PDCCH may be transmitted using one or more of these CCEs, where each CCE may correspond to nine sets of four physical resource elements known as resource element groups (REGs). Four Quadrature Phase Shift Keying (QPSK) symbols may be mapped to each REG. The PDCCH can be transmitted using one or more CCEs, depending on the size of the downlink control information (DCI) and the channel condition. There can be four or more different PDCCH formats defined in LTE with different numbers of CCEs (e.g., aggregation level, L=1 , 2, 4, or 8).

[0044] Some embodiments may use concepts for resource allocation for control channel information that are an extension of the above-described concepts. For example, some embodiments may utilize an enhanced physical downlink control channel (EPDCCH) that uses PDSCH resources for control information transmission. The EPDCCH may be transmitted using one or more enhanced the control channel elements (ECCEs). Similar to above, each ECCE may correspond to nine sets of four physical resource elements known as an enhanced resource element groups (EREGs). An ECCE may have other numbers of EREGs in some situations.

[0045] The RAN 1 1 0 is shown to be communicatively coupled to a core network (CN) 1 20— via an S1 interface 1 1 3. In embodiments, the CN 120 may be an evolved packet core (EPC) network, a NextGen Packet Core (NPC) network, or some other type of CN. In this embodiment the S1 interface 1 13 is split into two parts: the S1 -U interface 1 14, which carries traffic data between the RAN nodes 1 1 1 and 1 12 and the serving gateway (S-GW) 122, and the S1 -mobility management entity (MME) interface 1 15, which is a signaling interface between the RAN nodes 1 1 1 and 1 12 and MMEs 121 .

[0046] In this embodiment, the CN 1 20 comprises the MMEs 121 , the S-GW 122, the Packet Data Network (PDN) Gateway (P-GW) 123, and a home subscriber server (HSS) 124. The MMEs 121 may be similar in function to the control plane of legacy Serving General Packet Radio Service (GPRS) Support Nodes (SGSN). The MMEs 121 may manage mobility aspects in access such as gateway selection and tracking area list management. The HSS 124 may comprise a database for network users, including subscription-related information to support the network entities' handling of

communication sessions. The CN 120 may comprise one or several HSSs 124, depending on the number of mobile subscribers, on the capacity of the equipment, on the organization of the network, etc. For example, the HSS 124 can provide support for routing/roaming, authentication, authorization, naming/addressing resolution, location dependencies, etc.

[0047] The S-GW 122 may terminate the S1 interface 1 13 towards the RAN 1 10, and routes data packets between the RAN 1 10 and the CN 120. In addition, the S-GW 122 may be a local mobility anchor point for inter-RAN node handovers and also may provide an anchor for inter-3GPP mobility. Other responsibilities may include lawful intercept, charging, and some policy enforcement.

[0048] The P-GW 123 may terminate an SGi interface toward a PDN. The P-GW 123 may route data packets between the EPC network 123 and external networks such as a network including the application server 130 (alternatively referred to as application function (AF)) via an Internet Protocol (IP) interface 125. Generally, the application server 130 may be an element offering applications that use IP bearer resources with the core network (e.g., UMTS Packet Services (PS) domain, LTE PS data services, etc.). In this embodiment, the P-GW 123 is shown to be communicatively coupled to an application server 130 via an IP communications interface 125. The application server 130 can also be configured to support one or more communication services (e.g., Voice-over-Internet Protocol (VoIP) sessions, PTT sessions, group communication sessions, social networking services, etc.) for the UEs 101 and 102 via the CN 120.

[0049] The P-GW 123 may further be a node for policy enforcement and charging data collection. Policy and Charging Enforcement Function (PCRF) 126 is the policy and charging control element of the CN 120. In a non-roaming scenario, there may be a single PCRF in the Home Public Land Mobile Network (HPLMN) associated with a UE's Internet Protocol Connectivity Access Network (IP-CAN) session. In a roaming scenario with local breakout of traffic, there may be two PCRFs associated with a UE's IP-CAN session: a Home PCRF (H-PCRF) within a HPLMN and a Visited PCRF (V-PCRF) within a Visited Public Land Mobile Network (VPLMN). The PCRF 126 may be communicatively coupled to the application server 130 via the P-GW 123. The application server 130 may signal the PCRF 126 to indicate a new service flow and select the appropriate Quality of Service (QoS) and charging parameters. The PCRF 126 may provision this rule into a Policy and Charging Enforcement Function (PCEF) (not shown) with the appropriate traffic flow template (TFT) and QoS class of identifier (QCI), which commences the QoS and charging as specified by the application server 130.

[0050] FIG. 2 illustrates example components of a device 200 in accordance with some embodiments. In some embodiments, the device 200 may include application circuitry 202, baseband circuitry 204, Radio Frequency (RF) circuitry 206, front-end module (FEM) circuitry 208, one or more antennas 21 0, and power management circuitry (PMC) 21 2 coupled together at least as shown. The components of the illustrated device 200 may be included in a UE or a RAN node. In some embodiments, the device 200 may include less elements (e.g., a RAN node may not utilize application circuitry 202, and instead include a processor/controller to process IP data received from an EPC). In some embodiments, the device 200 may include additional elements such as, for example, memory/storage, display, camera, sensor, or input/output (I/O) interface. In other embodiments, the components described below may be included in more than one device (e.g., said circuitries may be separately included in more than one device for Cloud-RAN (C-RAN) implementations).

[0051] The application circuitry 202 may include one or more application processors. For example, the application circuitry 202 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The processor(s) may include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, etc.). The processors may be coupled with or may include memory/storage and may be configured to execute instructions stored in the memory/storage to enable various applications or operating systems to run on the device 200. In some embodiments, processors of application circuitry 202 may process IP data packets received from an EPC.

[0052] The baseband circuitry 204 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. The baseband circuitry 204 may include one or more baseband processors or control logic to process baseband signals received from a receive signal path of the RF circuitry 206 and to generate baseband signals for a transmit signal path of the RF circuitry 206. Baseband processing circuity 204 may interface with the application circuitry 202 for generation and processing of the baseband signals and for controlling operations of the RF circuitry 206. For example, in some embodiments, the baseband circuitry 204 may include a third generation (3G) baseband processor 204A, a fourth generation (4G) baseband processor 204B, a fifth generation (5G) baseband processor 204C, or other baseband processor(s) 204D for other existing generations, generations in development or to be developed in the future (e.g., second generation (2G), sixth generation (6G), etc.). The baseband circuitry 204 (e.g., one or more of baseband processors 204A-D) may handle various radio control functions that enable communication with one or more radio networks via the RF circuitry 206. In other embodiments, some or all of the functionality of baseband processors 204A-D may be included in modules stored in the memory 204G and executed via a Central Processing Unit (CPU) 204E. The radio control functions may include, but are not limited to, signal modulation/demodulation, encoding/decoding, radio frequency shifting, etc. In some embodiments, modulation/demodulation circuitry of the baseband circuitry 204 may include Fast-Fourier Transform (FFT), precoding, or constellation mapping/demapping functionality. In some embodiments,

encoding/decoding circuitry of the baseband circuitry 204 may include convolution, tail- biting convolution, turbo, Viterbi, or Low Density Parity Check (LDPC) encoder/decoder functionality. Embodiments of modulation/demodulation and encoder/decoder functionality are not limited to these examples and may include other suitable functionality in other embodiments.

[0053] In some embodiments, the baseband circuitry 204 may include one or more audio digital signal processor(s) (DSP) 204F. The audio DSP(s) 204F may be include elements for compression/decompression and echo cancellation and may include other suitable processing elements in other embodiments. Components of the baseband circuitry may be suitably combined in a single chip, a single chipset, or disposed on a same circuit board in some embodiments. In some embodiments, some or all of the constituent components of the baseband circuitry 204 and the application circuitry 202 may be implemented together such as, for example, on a system on a chip (SOC).

[0054] In some embodiments, the baseband circuitry 204 may provide for communication compatible with one or more radio technologies. For example, in some embodiments, the baseband circuitry 204 may support communication with an evolved universal terrestrial radio access network (EUTRAN) or other wireless metropolitan area networks (WMAN), a wireless local area network (WLAN), a wireless personal area network (WPAN). Embodiments in which the baseband circuitry 204 is configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuitry.

[0055] RF circuitry 206 may enable communication with wireless networks using modulated electromagnetic radiation through a non-solid medium. In various embodiments, the RF circuitry 206 may include switches, filters, amplifiers, etc. to facilitate the communication with the wireless network. RF circuitry 206 may include a receive signal path which may include circuitry to down-convert RF signals received from the FEM circuitry 208 and provide baseband signals to the baseband circuitry 204. RF circuitry 206 may also include a transmit signal path which may include circuitry to up-convert baseband signals provided by the baseband circuitry 204 and provide RF output signals to the FEM circuitry 208 for transmission.

[0056] In some embodiments, the receive signal path of the RF circuitry 206 may include mixer circuitry 206a, amplifier circuitry 206b and filter circuitry 206c. In some embodiments, the transmit signal path of the RF circuitry 206 may include filter circuitry 206c and mixer circuitry 206a. RF circuitry 206 may also include synthesizer circuitry 206d for synthesizing a frequency for use by the mixer circuitry 206a of the receive signal path and the transmit signal path. In some embodiments, the mixer circuitry 206a of the receive signal path may be configured to down-convert RF signals received from the FEM circuitry 208 based on the synthesized frequency provided by synthesizer circuitry 206d. The amplifier circuitry 206b may be configured to amplify the down- converted signals and the filter circuitry 206c may be a low-pass filter (LPF) or bandpass filter (BPF) configured to remove unwanted signals from the down-converted signals to generate output baseband signals. Output baseband signals may be provided to the baseband circuitry 204 for further processing. In some embodiments, the output baseband signals may be zero-frequency baseband signals, although this is not a requirement. In some embodiments, mixer circuitry 206a of the receive signal path may comprise passive mixers, although the scope of the embodiments is not limited in this respect.

[0057] In some embodiments, the mixer circuitry 206a of the transmit signal path may be configured to up-convert input baseband signals based on the synthesized frequency provided by the synthesizer circuitry 206d to generate RF output signals for the FEM circuitry 208. The baseband signals may be provided by the baseband circuitry 204 and may be filtered by filter circuitry 206c.

[0058] In some embodiments, the mixer circuitry 206a of the receive signal path and the mixer circuitry 206a of the transmit signal path may include two or more mixers and may be arranged for quadrature downconversion and upconversion, respectively. In some embodiments, the mixer circuitry 206a of the receive signal path and the mixer circuitry 206a of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuitry 206a of the receive signal path and the mixer circuitry 206a may be arranged for direct downconversion and direct upconversion, respectively. In some embodiments, the mixer circuitry 206a of the receive signal path and the mixer circuitry 206a of the transmit signal path may be configured for super-heterodyne operation.

[0059] In some embodiments, the output baseband signals and the input baseband signals may be analog baseband signals, although the scope of the embodiments is not limited in this respect. In some alternate embodiments, the output baseband signals and the input baseband signals may be digital baseband signals. In these alternate embodiments, the RF circuitry 206 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry and the baseband circuitry 204 may include a digital baseband interface to communicate with the RF circuitry 206.

[0060] In some dual-mode embodiments, a separate radio IC circuitry may be provided for processing signals for each spectrum, although the scope of the

embodiments is not limited in this respect.

[0061] In some embodiments, the synthesizer circuitry 206d may be a fractional-N synthesizer or a fractional N/N+1 synthesizer, although the scope of the embodiments is not limited in this respect as other types of frequency synthesizers may be suitable. For example, synthesizer circuitry 206d may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer comprising a phase-locked loop with a frequency divider.

[0062] The synthesizer circuitry 206d may be configured to synthesize an output frequency for use by the mixer circuitry 206a of the RF circuitry 206 based on a frequency input and a divider control input. In some embodiments, the synthesizer circuitry 206d may be a fractional N/N+1 synthesizer.

[0063] In some embodiments, frequency input may be provided by a voltage controlled oscillator (VCO), although that is not a requirement. Divider control input may be provided by either the baseband circuitry 204 or the applications processor 202 depending on the desired output frequency. In some embodiments, a divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the applications processor 202.

[0064] Synthesizer circuitry 206d of the RF circuitry 206 may include a divider, a delay-locked loop (DLL), a multiplexer and a phase accumulator. In some embodiments, the divider may be a dual modulus divider (DMD) and the phase accumulator may be a digital phase accumulator (DPA). In some embodiments, the DMD may be configured to divide the input signal by either N or N+1 (e.g., based on a carry out) to provide a fractional division ratio. In some example embodiments, the DLL may include a set of cascaded, tunable, delay elements, a phase detector, a charge pump and a D-type flip- flop. In these embodiments, the delay elements may be configured to break a VCO period up into Nd equal packets of phase, where Nd is the number of delay elements in the delay line. In this way, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

[0065] In some embodiments, synthesizer circuitry 206d may be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used in conjunction with quadrature generator and divider circuitry to generate multiple signals at the carrier frequency with multiple different phases with respect to each other. In some embodiments, the output frequency may be a LO frequency (fLO). In some embodiments, the RF circuitry 206 may include an IQ/polar converter.

[0066] FEM circuitry 208 may include a receive signal path which may include circuitry configured to operate on RF signals received from one or more antennas 210, amplify the received signals and provide the amplified versions of the received signals to the RF circuitry 206 for further processing. FEM circuitry 208 may also include a transmit signal path which may include circuitry configured to amplify signals for transmission provided by the RF circuitry 206 for transmission by one or more of the one or more antennas 21 0. In various embodiments, the amplification through the transmit or receive signal paths may be done solely in the RF circuitry 206, solely in the FEM 208, or in both the RF circuitry 206 and the FEM 208.

[0067] In some embodiments, the FEM circuitry 208 may include a TX/RX switch to switch between transmit mode and receive mode operation. The FEM circuitry may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuitry may include an LNA to amplify received RF signals and provide the amplified received RF signals as an output (e.g., to the RF circuitry 206). The transmit signal path of the FEM circuitry 208 may include a power amplifier (PA) to amplify input RF signals (e.g., provided by RF circuitry 206), and one or more filters to generate RF signals for subsequent transmission (e.g., by one or more of the one or more antennas 210).

[0068] In some embodiments, the PMC 212 may manage power provided to the baseband circuitry 204. In particular, the PMC 21 2 may control power-source selection, voltage scaling, battery charging, or DC-to-DC conversion. The PMC 212 may often be included when the device 200 is capable of being powered by a battery, for example, when the device is included in a UE. The PMC 21 2 may increase the power conversion efficiency while providing desirable implementation size and heat dissipation

characteristics.

[0069] While FIG. 2 shows the PMC 212 coupled only with the baseband circuitry 204. However, in other embodiments, the PMC 2 12 may be additionally or alternatively coupled with, and perform similar power management operations for, other components such as, but not limited to, application circuitry 202, RF circuitry 206, or FEM 208.

[0070] In some embodiments, the PMC 212 may control, or otherwise be part of, various power saving mechanisms of the device 200. For example, if the device 200 is in an RRC_Connected state, where it is still connected to the RAN node as it expects to receive traffic shortly, then it may enter a state known as Discontinuous Reception Mode (DRX) after a period of inactivity. During this state, the device 200 may power down for brief intervals of time and thus save power.

[0071] If there is no data traffic activity for an extended period of time, then the device 200 may transition off to an RRCJdle state, where it disconnects from the network and does not perform operations such as channel quality feedback, handover, etc. The device 200 goes into a very low power state and it performs paging where again it periodically wakes up to listen to the network and then powers down again. The device 200 may not receive data in this state, in order to receive data, it must transition back to RRC_Connected state.

[0072] An additional power saving mode may allow a device to be unavailable to the network for periods longer than a paging interval (ranging from seconds to a few hours). During this time, the device is totally unreachable to the network and may power down completely. Any data sent during this time incurs a large delay and it is assumed the delay is acceptable.

[0073] Processors of the application circuitry 202 and processors of the baseband circuitry 204 may be used to execute elements of one or more instances of a protocol stack. For example, processors of the baseband circuitry 204, alone or in combination, may be used execute Layer 3, Layer 2, or Layer 1 functionality, while processors of the application circuitry 204 may utilize data (e.g., packet data) received from these layers and further execute Layer 4 functionality (e.g., transmission communication protocol (TCP) and user datagram protocol (UDP) layers). As referred to herein, Layer 3 may comprise a radio resource control (RRC) layer, described in further detail below. As referred to herein, Layer 2 may comprise a medium access control (MAC) layer, a radio link control (RLC) layer, and a packet data convergence protocol (PDCP) layer, described in further detail below. As referred to herein, Layer 1 may comprise a physical (PHY) layer of a UE/RAN node, described in further detail below.

[0074] FIG. 3 illustrates example interfaces of baseband circuitry in accordance with some embodiments. As discussed above, the baseband circuitry 204 of FIG. 2 may comprise processors 204A-204E and a memory 204G utilized by said processors. Each of the processors 204A-204E may include a memory interface, 304A-304E,

respectively, to send/receive data to/from the memory 204G.

[0075] The baseband circuitry 204 may further include one or more interfaces to communicatively couple to other circuitries/devices, such as a memory interface 312 (e.g., an interface to send/receive data to/from memory external to the baseband circuitry 204), an application circuitry interface 314 (e.g., an interface to send/receive data to/from the application circuitry 202 of FIG. 2), an RF circuitry interface 316 (e.g., an interface to send/receive data to/from RF circuitry 206 of FIG. 2), a wireless hardware connectivity interface 31 8 (e.g., an interface to send/receive data to/from Near Field Communication (NFC) components, Bluetooth® components (e.g., Bluetooth® Low Energy), Wi-Fi® components, and other communication components), and a power management interface 320 (e.g., an interface to send/receive power or control signals to/from the PMC 212).

[0076] In various aspects, techniques discussed herein can be employed to facilitate phase noise compensation and detection at a receiving communication device (e.g., BS (a Base Station such as a eNB (evolved Node B) or gNB (next generation Node B)) or a UE (User Equipment)) in a mobile network. A transmitting device in a mobile network can employ one of a first set of techniques discussed herein (e.g., FDM (Frequency Division Multiplexing) based techniques employing TRS (Tracking Reference Signals)) or a second set of techniques (e.g., TDM (Time Division Multiplexing) based techniques employing time-trackable sequences).

[0077] Referring to FIG. 4, illustrated is a block diagram of a system 400 employable at a UE (User Equipment) that facilitates phase noise compensation, according to various aspects described herein. System 400 can include one or more processors 410 (e.g., one or more baseband processors such as one or more of the baseband processors discussed in connection with FIG. 2 and/or FIG. 3) comprising processing circuitry and associated memory interface(s) (e.g., memory interface(s) discussed in connection with FIG. 3), transceiver circuitry 420 (e.g., comprising one or more of transmitter circuitry or receiver circuitry, which can employ common circuit elements, distinct circuit elements, or a combination thereof), and a memory 430 (which can comprise any of a variety of storage mediums and can store instructions and/or data associated with one or more of processor(s) 410 or transceiver circuitry 420). In various aspects, system 400 can be included within a user equipment (UE). As described in greater detail below, system 400 can facilitate phase compensation based on generation or reception of TRS or a time-trackable sequence.

[0078] Referring to FIG. 5, illustrated is a block diagram of a system 500 employable at a BS (Base Station) that facilitates phase noise compensation, according to various aspects described herein. System 600 can include one or more processors 510 (e.g., one or more baseband processors such as one or more of the baseband processors discussed in connection with FIG. 2 and/or FIG. 3) comprising processing circuitry and associated memory interface(s) (e.g., memory interface(s) discussed in connection with FIG. 3), communication circuitry 520 (e.g., which can comprise circuitry for one or more wired (e.g., X2, etc.) connections and/or transceiver circuitry that can comprise one or more of transmitter circuitry (e.g., associated with one or more transmit chains) or receiver circuitry (e.g., associated with one or more receive chains), wherein the transmitter circuitry and receiver circuitry can employ common circuit elements, distinct circuit elements, or a combination thereof), and memory 530 (which can comprise any of a variety of storage mediums and can store instructions and/or data associated with one or more of processor(s) 510 or communication circuitry 520). In various aspects, system 500 can be included within an Evolved Universal Terrestrial Radio Access Network (E-UTRAN) Node B (Evolved Node B, eNodeB, or eNB), next generation Node B (gNodeB or gNB) or other base station in a wireless communications network. In some aspects, the processor(s) 51 0, communication circuitry 520, and the memory 530 can be included in a single device, while in other aspects, they can be included in different devices, such as part of a distributed architecture. As described in greater detail below, system 500 can facilitate phase compensation based on generation or reception of TRS or a time-trackable sequence.

[0079] In various aspects discussed herein, signals and/or messages can be generated and output for transmission, and/or transmitted messages can be received and processed. Depending on the type of signal or message generated, outputting for transmission (e.g., by processor(s) 410, processor(s) 510, etc.) can comprise one or more of the following: generating a set of associated bits that indicate the content of the signal or message, coding (e.g., which can include adding a cyclic redundancy check (CRC) and/or coding via one or more of turbo code, low density parity-check (LDPC) code, tailbiting convolution code (TBCC), etc.), scrambling (e.g., based on a scrambling seed), modulating (e.g., via one of binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), or some form of quadrature amplitude modulation (QAM), etc.), and/or resource mapping (e.g., to a scheduled set of resources, to a set of time and frequency resources granted for uplink transmission, etc.). Depending on the type of received signal or message, processing (e.g., by processor(s) 410, processor(s) 51 0, etc.) can comprise one or more of: identifying physical resources associated with the signal/message, detecting the signal/message, resource element group deinterleaving, demodulation, descrambling, and/or decoding.

[0080] Phase noise in oscillators can have a greater impact on 5G millimeter-wave systems than conventional wireless systems. Referring to FIG. 6, illustrated is a pair of diagrams showing phase noise power spectral density (PSD) at 600 and its impact on constellations at 650, in connection with various aspects discussed herein. As can be seen at 600, the phase noise can increase by approximately 20 dBc/Hz per decade of increase of the carrier frequency. The phase noise can bring in a common phase Error (CPE) in each subcarrier. In various aspects, techniques to track and compensate CPE discussed herein can be employed to reduce phase noise.

[0081] In various aspects, techniques discussed herein can facilitate phase compensation, for example, in 5G (Fifth Generation) millimeter-wave systems. In various aspects, two sets of techniques are discussed herein, either or both of which can be employed (e.g., by system 400 and/or system 500) in various aspects for phase noise compensation. The first set of techniques can relate to FDM (Frequency Division Multiplexing) based TRS techniques, and the second set of techniques can relate to TDM (Time Division Multiplexing) based TRS techniques. The first set of techniques can be employed in most scenarios. Since the phase noise impact can be more significant in scenarios with a high modulation order with high SNR (Signal-to-Noise Ratio), some CM increase from the first set of techniques is not an issue. Conventional time-domain techniques (e.g., as discussed in connection with FIG. 7, below) may not be as effective as techniques discussed herein in large delay spread scenarios or where the time domain correlation of phase noise is not high, and relies on the phase noise model.

Phase Compensation Techniques for FDM (Frequency Division Multiplexing)

[0082] In connection with a first set of techniques, in an OFDMA (or other OFDM (Orthogonal Frequency Division Multiplexing)-based symbol) system, tracking reference signals (TRS) can be added in each symbol (e.g., by processor(s) 510 for transmission by communication circuitry 520) (or each symbol in which data (e.g., PDCH (Physical Data Channel)) is transmitted) with low density in frequency domain so that the CPE can be estimated and compensated (e.g., by processor(s) 410 based on the TRS as received via transceiver circuitry 420). In LTE (Long Term Evolution), the SC (Single Carrier)-FDMA (Frequency Division Multiple Access) waveform is utilized for uplink transmission, which, compared to OFDM, can have lower peak-to-average power ratio (PAPR). In a 5G system, the SC-FDMA waveform can also be used in various aspects. For a SC-FDMA system, it can be more difficult to add the TRS in every N (e.g. A/=4, etc.) RBs as compared with an OFDMA system. Techniques to track and compensate the phase noise impact for systems based on the SC-FDMA waveform and/or the OFDMA waveform are discussed herein.

[0083] Referring to FIG. 7, illustrated is a conventional time domain TRS technique for the SC-FDMA or pure SC waveforms. However, this technique can only work in certain cases wherein the delay speed is relatively small and the subcarrier spacing is large. In contrast, techniques discussed herein can be more robust than that illustrated in connection with FIG. 7, and can work in all scenarios.

[0084] LTE adopted SC-FDMA as its uplink multiple access scheme. Since Rel-10 (LTE Release 10), simultaneous PUCCH (Physical Uplink Control Channel) and PUSCH (Physical Uplink Shared Channel) transmission can be allowed, where the PUCCH can be located in the edge RBs (Resource Blocks) and the PUSCH can be located in the central RBs. Referring to FIG. 8, illustrated is a diagram showing simultaneous PUCCH and PUSCH transmission in LTE, in connection with various aspects discussed herein.

[0085] In various embodiments according to the first set of techniques, the TRS and the PDCH (Physical Data Channel) can be mapped (e.g., by processor(s) 510, for transmission by communication circuitry 520) in a manner similar to simultaneous PUCCH and PUSCH transmission in LTE, wherein the TRS can be located in the edge RB(s) and the PDCH (e.g., for DL (Downlink) and/or UL (Uplink)) can be mapped (e.g., by processor(s) 51 0) to the central RBs.

[0086] In various such aspects, TRS for different UEs or TRS antenna ports (APs) can be multiplexed (e.g., by processor(s) 51 0 for transmission by communication circuitry 520) in a frequency division multiplexing (FDM), a code division multiplexing (CDM) manner, or a combination thereof.

[0087] In various aspects of the first set of techniques, the TRS can be divided (e.g., by processor(s) 51 0) into several TRS groups and some UEs can be configured with the same TRS group (e.g., via configuration signaling, which can be generated by processor(s) 51 0, transmitted by communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 41 0). Each TRS group can be mapped (e.g., by processor(s) 51 0 for transmission by communication circuitry 520) in a

Frequency Division Multiplexing (FDM) manner. In various aspects, the TRS for one antenna port (AP) can occupy each subcarrier in one RB within one TRS group, for example, 1 2 REs per symbol, for example, using a Zadoff-Chu (ZC) sequence (e.g., wherein processor(s) 510 can encode each TRS with an associated ZC sequence, which can be transmitted by communication circuitry 520 and received via transceiver circuitry 51 0, and decoded by processor(s) 41 0). In various such aspects, different UEs can be distinguished by the cyclic shift of the associated ZC sequence (e.g., as configured via configuration signaling). Additionally, different RBs in the edge can belong to different TRS groups (e.g., as configured via configuration signaling). In some aspects, the number of RBs allocated for TRS transmission can be semi-statically configured by higher layers via one of a NR master information block (xMIB), NR system information block (xSIB) or radio resource control (RRC) signaling (e.g., generated by processor(s) 51 0, transmitted by communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 41 0). In other aspects, the number of RBs for TRS transmission can be dynamically indicated in the downlink control information (DCI) (e.g., generated by processor(s) 51 0, transmitted by communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 41 0).

[0088] In various aspects of the first set of techniques, to provide robustness on relatively large delay spread, a cyclic shift separation A _shift can be configured by higher layers via xMIB, xSIB or RRC signaling (e.g., generated by processor(s) 510, transmitted by communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 41 0). As one example, A _shirt = 2 , which indicates 6 cyclic shift values or 6 TRS APs can be multiplexed within one RB.

[0089] In other aspects of the first set of techniques, the TRS of different Antenna Ports (APs) or UEs within one TRS group can be distinguished by different Orthogonal Cover Codes (OCCs) or subcarriers (e.g., which can be configured via configuration signaling generated by processor(s) 51 0, transmitted by communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 41 0).

[0090] Referring to FIG. 9, illustrated is a diagram of a first example TRS pattern employing different cyclic shifts for TRS for different users, according to various aspects discussed herein. Referring to FIG. 10, illustrated is a diagram of a first example TRS pattern employing different frequency resources for TRS for different users, according to various aspects discussed herein. FIGS. 9 and 1 0 illustrate two possible examples for the TRS pattern. In a given subframe, the first and/or last few symbols may be reserved for xPDCCH (NR (New Radio) PDCCH) and/or gaps. For the remaining symbols, the TRS can be mapped (e.g., by processor(s) 510 for transmission by communication circuitry 520) to the RBs at the edge of the bandwidth (e.g., to either side or both).

Additionally, the TRS can be mapped (e.g., by processor(s) 510 for transmission by communication circuitry 520) to each symbol in the subcarriers of those RBs. In FIG. 9, each TRS group contains 1 RB per symbol. Different UEs can be distinguished by the cyclic shift of the ZC sequence. In FIG. 10, each TRS group contains 4 REs per symbol. If 2 RBs are used for TRS, there can be up to 24 UEs co-scheduled in one subframe for both patterns if ZC sequence cyclic shift or OCC-4 for TRS is enabled. In another example, OCC-4 need not be applied, and in such scenarios, a total of 6 UEs can be co-scheduled.

[0091] Referring to FIG. 11 , illustrated is a pair of diagrams 1 100 and 1 150 that show the PAPR (Peak-to- Average Power Ratio) CCDF (Complementary Cumulative

Distribution Function) curves of different TRS sequences (1 1 02-1 106) based on a SC- FDMA waveform (with TRS and PUSCH contiguous at 1 100 or non-contiguous at 1 1 50), according to various aspects discussed herein. For the graphs of FIG. 1 1 , the bandwidth was 80MHz with a subcarrier spacing of 60kHz, comprising a total of 100 RBs. The PAPR results illustrated in FIG. 1 1 were collected from multiple random resource allocation for data cases. In both 1 1 00 and 1 1 50, the PAPR of OCC and ZC sequences are higher than the scenario with no TRS. Additionally, the ZC sequence is slightly better than the OCC method. Furthermore, the PAPR in the scenario with TRS and PUSCH contiguous is slightly better than the non- contiguous scenario.

[0092] In various embodiments associated with the first set of techniques, the TRS (e.g., generated by processor(s) 51 0) can be transmitted (e.g., via communication circuitry 520) on the edge of resources allocated (e.g., by processor(s) 510) for a data channel (e.g., xPDCH). Referring to FIG. 12, illustrated are three example resource allocations 1200-1220 for PDCH and TRS, according to various aspects discussed herein. In example resource allocation 1200, TRS (e.g., generated by processor(s) 510) can be transmitted (e.g., via communication circuitry 520) on both edges of the resources allocated (e.g., by processor(s) 51 0) for PDCH. In example resource allocation 121 0, TRS (e.g., generated by processor(s) 510) can be transmitted (e.g., via communication circuitry 520) on the upper edge of the resources allocated (e.g., by processor(s) 510) for PDCH. In example resource allocation 1220, TRS (e.g., generated by processor(s) 51 0) can be transmitted (e.g., via communication circuitry 520) on the lower edge of the resources allocated (e.g., by processor(s) 510) for PDCH.

[0093] In scenarios wherein resource allocation of the PDCH transmission for multiple UEs are multiplexed (e.g., by processor(s) 510 for transmission by

communication circuitry 520) in a FDM manner and are contiguous (to PDCH), TRS for multiple UEs can be located in the same resources (e.g., as scheduled by processor(s) 51 0 and transmitted by communication circuitry 520) and multiplexed (e.g., by processor(s) 510) in a FDM manner, a CDM manner or a combination thereof (e.g., similar to that described above in connection with FIGS. 9 and 10). Referring to FIG. 13, illustrated is one example of shared TRS frequency resources for two UEs, according to various aspects described herein. In scenarios when 12 REs are used for TRS transmission (e.g., by communication circuitry 520 of TRS generated by processor(s) 51 0), different cyclic shift values can be used for TRS APs for two UEs (e.g., wherein processor(s) 510 can encode each TRS with an associated ZC sequence having an associated cyclic shift, which can be transmitted by communication circuitry 520 and received via transceiver circuitry 510, and decoded by processor(s) 410).

[0094] In various embodiments associated with the first set of techniques, TRS (e.g., generated by processor(s) 510) can be transmitted (e.g., via communication circuitry 520 for reception by transceiver circuitry 420) in the central N RBs. Similarly to embodiments discussed above, TRS for multiple UEs or TRS APs can be multiplexed in a FDM or CDM manner or a combination thereof (e.g., by processor(s) 510 for transmission by communication circuitry 520). Further, the number of RBs (e.g., N) can be configured by higher layers via xMIB, xSIB, or RRC signaling (e.g., generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410). Referring to FIG. 14, illustrated is a diagram showing an example of TRS resource allocation in the central RBs, according to various aspects discussed herein.

[0095] In various embodiments associated with the first set of techniques, the TRS group index for a UE can be configured via higher layer signaling or Downlink Control Information (DCI) (e.g., generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410). Alternatively the TRS group index can be determined (e.g., by processor(s) 410 and processor(s) 510) by the antenna port index and the starting RB index. In various aspects, there can be a TRS group index indicator in the DCI (e.g., generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410) which comprises [log ₂ (iVg + 1)] bits, where N _g indicates the total number of TRS groups which can be pre-defined or configured via higher layer signaling (e.g., generated by processor(s) 51 0, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 41 0). In various aspects, one particular TRS group index, for example 0, can be used to indicate there is no TRS for current UE.

[0096] In various aspects, the TRS AP index for one UE within a TRS group can be configured (e.g., via higher layer signaling or DCI generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410) or can be determined (e.g., by processor(s) 410 and processor(s) 510) by the antenna port index and/or scramble ID.

[0097] In various embodiments associated with the first set of techniques, the TRS resource index (including allocated RB, group index, cyclic shift value, or OCC value) can be configured by higher layers via dedicated RRC signaling or dynamically indicated in the DCI format or a combination thereof (e.g., with the higher layer signaling or DCI message(s) generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410). Further, one or more TRS APs or TRS resource indexes can be configured for a given UE (e.g., via configuration signaling generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410) to further improve the phase noise compensation performance.

[0098] Similarly, in scenarios wherein a UE is equipped with multiple antenna panels, for dual beam transmission, multiple TRS resource indexes can be configured for one UE, wherein one or more resource indexes can be configured for one panel (e.g., via configuration signaling generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410).

[0099] In one example associated with the first set of techniques, the cyclic shift index can be based on a combination of one or more of cell specific, UE specific and AP specific parameters, wherein a cell specific cyclic shift can be determined (e.g., by processor(s) 410 and/or processor(s) 510) as a function of at least one of the following parameters: a physical cell ID, a virtual cell ID, a symbol/slot/subframe index, or a RB index. A UE specific cyclic shift value can be indicated in the DCI format (e.g., generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410). An AP specific cyclic shift value can be determined (e.g., by processor(s) 410 and/or processor(s) 510) as a function of a TRS AP index.

[00100] Additionally, for different OFDM symbols, the same or different cyclic shift values or OCC values can be applied (e.g., by processor(s) 510) for TRS sequence generation. In the latter case, cyclic shift or OCC hopping can be defined (e.g., and implemented by processor(s) 510 and/or processor(s) 410) to further randomize the inter-cell interference. The hopping pattern (e.g., employed by processor(s) 410 and/or processor(s) 510) can be defined as a function of at least one of the following parameters: physical cell ID, virtual cell ID, symbol/slot/subframe index, or

subcarrier/sub-band/PRB index for TRS transmission.

[00101 ] In various aspects associated with the first set of techniques, the TRS pattern can also be extended to the OFDM waveform. Since the TRS for all UEs can be concentrated on the edge RBs, the BS (e.g., eNB, gNB, etc.) can schedule (e.g., via processor(s) 510) all of them at the same time. In another option, the TRS group can be mapped (e.g., by processor(s) 510) to some other RBs that are pre-defined or configured by higher layer signaling (e.g., generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 41 0).

[00102] In various aspects associated with the first set of techniques, one or more TRS APs for PDCH transmission for one UE can be implicitly or explicitly indicated in the DCI (e.g., generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410). In the former case, one to one association or one or many association between TRS AP and DM-RS AP can be predefined or configured by higher layers via xMIB, xSIB or RRC signaling (e.g., generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410).

[00103] In aspects, a UE can determine (e.g., via processor(s) 41 0) characteristics of a TRS design (e.g., at least one of a presence of the set of TRS, a time density of the set of TRS, or a frequency density of the set of TRS, etc.) based at least in part on one of: higher layer signaling (e.g., generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410), a Modulation and Coding Scheme (MCS), an allocated bandwidth, or a subcarrier spacing. [00104] For TRS patterns as described herein, symbol level channel estimation can be employed. Referring to FIG. 15, illustrated is a diagram showing BLER (Block Error Rate) for different compensation techniques (or no compensation) in addressing phase noise compared to an ideal scenario involving no phase noise, according to various aspects discussed herein. As seen in FIG. 15, the gap between performance with phase noise (PN) and without PN is about 4dB. When using TRS compensation, the performance is better than without compensation. As the SNR grows, this gap increases. In high SNR scenarios (larger than 25dB), this gap can be up to 3dB or more. Additionally, as seen in FIG. 15, PN compensation using 4 TRS per symbol for one AP provides approximately 1 dB gain over using 1 TRS. Also shown in FIG. 15, employing 12 TRS can provide additional gains over the 4 TRS scenario, but of a lesser degree than the improvement of the 4 TRS scenario over the 1 TRS scenario.

[00105] In a first example scenario implementing aspects of the first set of techniques, a User Equipment (UE) can comprise circuitry to receive (e.g., transceiver circuitry 420) control signaling of Tracking Reference Signal (TRS) (e.g., generated by processor(s) 51 0 and transmitted via communication circuitry 520) and to determine (e.g.,

processor(s) 410) a resource design pattern for TRS for a single carrier frequency division multiplex access (SC-FDMA) waveform and/or a OFDM (Orthogonal Frequency Division Multiplexing) waveform.

[00106] In aspects of the first example scenario associated with the first set of techniques, the resource design pattern for TRS can be one of multiple predefined TRS design methods (e.g., predefined in a specification), which can vary, for example, in the time and/or frequency density of TRS associated with the TRS design(s). In various such aspects, the TRS can be mapped (e.g., by processor(s) 510 for transmission by communication circuitry 520) to subcarriers in the edge resource block(s) of a bandwidth. Alternatively, in various such aspects, the TRS can be mapped (e.g., by processor(s) 510 for transmission by communication circuitry 520) to consecutive subcarriers above or below subcarriers to which data is mapped. In various such aspects, the transform precoding used to generate the single carrier wave (e.g., by processor(s) 510) is not applied to the TRS. In various such aspects, the TRS can be divided into several TRS groups and two or more UEs can be configured with the same TRS group (e.g., via configuration signaling generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 41 0). [00107] In various aspects of the first example scenario associated with the first set of techniques, the number of RBs for TRS transmission can be dynamically indicated in the downlink control information (DCI) (e.g., generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 41 0). In various such aspects, the TRS of different groups can be mapped (e.g., by processor(s) 510 for transmission by communication circuitry 520) in a Frequency Division Multiplexing (FDM) manner. In various such aspects, the TRS for different antenna ports (AP) within one TRS group can be distinguished by different subcarrier, orthogonal cover code or cyclic shift. In various such aspects, different sequences can be applied (e.g., by processor(s) 410) to the TRS in the same group to ensure the multiplexing of different UEs or TRS AP. In various such aspects, the TRS can be selected (e.g., by processor(s) 510) as one of the TRS sequences from a plurality of predefined sequences to generate the TRS, which can be configured in higher layer signaling or Downlink Control Information (DCI) (e.g., generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410).

[00108] In various aspects of the first example scenario associated with the first set of techniques, the TRS can be an indicated TRS pattern of a plurality of predefined TRS patterns, wherein the indicated TRS pattern can be configured in higher layer signaling or Downlink Control Information (DCI) (e.g., generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 41 0).

[00109] In various aspects of the first example scenario associated with the first set of techniques, the TRS group index for a UE can be configured in higher layer signaling or Downlink Control Information (DCI) (e.g., generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 41 0).

[00110] Referring to FIG. 16, illustrated is a flow diagram of an example method 1 600 employable at a transmitting communication device that facilitates phase noise compensation based on TRS (Tracking Reference Signals), according to various aspects discussed herein. In other aspects, a machine readable medium can store instructions associated with method 1 600 that, when executed, can cause a transmitting communication device to perform the acts of method 1600.

[00111 ] At 1610, a PDCH can be generated.

[00112] At 1620, a set of TRS can be generated. [00113] At 1630, the PDCH and the set of TRS can each be mapped to a plurality of symbols (e.g., of an OFDM waveform), wherein the PDCH and the set of TRS can be frequency multiplexed (e.g., with the set of TRS mapped to various RBs as discussed herein, depending on the embodiment).

[00114] Additionally or alternatively, method 1600 can include one or more other acts described herein in connection with a transmitting communication device employing system 400 or system 500 and the first set of techniques.

[00115] Referring to FIG. 17, illustrated is a flow diagram of an example method 1 700 employable at a receiving communication device that facilitates phase noise

compensation based on TRS (Tracking Reference Signals), according to various aspects discussed herein. In other aspects, a machine readable medium can store instructions associated with method 1 700 that, when executed, can cause a receiving communication device to perform the acts of method 1700.

[00116] At 1710, a PDCH can be demodulated.

[00117] At 1720, a set of TRS can be decoded.

[00118] At 1730, a phase noise associated with the set of TRS can be estimated.

[00119] At 1740, phase noise associated with the PDCH can be compensated for based on the estimated phase noise associated with the set of TRS.

[00120] Additionally or alternatively, method 1700 can include one or more other acts described herein in connection with a receiving communication device employing system 400 or system 500 and the first set of techniques.

Phase Compensation Techniques for TDM (Time Division Multiplexing)

[00121 ] Phase noise is a fast changing random process to be tracked in the time domain, even within a symbol block or an OFDMA (Orthogonal Frequency Division Multiple Access) symbol. Traditional frequency domain pilots are not suitable for time domain tacking of phase noise. In aspects discussed herein associated with the second set of techniques, 'time-trackable' training samples (e.g., reference symbols of a time domain training sequence) can be employed (e.g., by processor(s) 510) for OFDM (Orthogonal Frequency Division Multiplexing)-based single carrier waveforms such as DFT (Discrete Fourier Transform)-s (spread)-OFDMA (also referred to as SC-FDMA), ZT (Zero-Tail)-DFT-s-OFDMA, Gl (Guard lnterval)-DFT-s-OFDMA, etc., to track and compensate fast changing phase noise within an OFDM symbol block time duration. Additionally, aspects of the second set of techniques can be employed to determine the density of the time tracking training samples based on some system/user parameters and capabilities.

[00122] In aspects of the second set of techniques, 'time-trackable' training sequences (e.g., time domain training sequences) can be employed (e.g., by processor(s) 510 and/or processor(s) 410) for OFDM-based single carrier waveforms such as DFT-s-OFDMA (also referred to as SC-FDMA), ZT-DFT-s-OFDMA, GI-DFT-s- OFDMA, etc., to track and compensate fast changing phase noise within an OFDM symbol block time duration. Additionally, in various aspects associated with the second set of techniques, the base station or access point of a system can allocate (e.g., via processor(s) 510) a variable number of time-trackable training symbols in each symbol/block for each UE, depending on one or more of the following associated with that UE: aa UE category, feedback, allocated bandwidth, and/or SNR regime. In addition, the position of the transmitted training samples within each symbol/block can also be configured (e.g., via configuration signaling generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410) for each UE based on one or more of the following for that UE: a UE category, feedback, allocated bandwidth, and/or SNR regime.

[00123] Conventional pilots for the OFDM-based single carrier waveform are defined in frequency domain. However, these frequency domain pilots are not able to track fast changing phase noise processes over the time domain. Using frequency domain pilots, only the average of a phase noise process can be estimated and compensated for. This can lead to large performance degradation for millimeter-wave networks. Aspects employing the second set of techniques discussed herein can comprise special time trackable training sequences for phase noise time tracking for OFDM-based single carrier waveforms. These techniques can provide noticeable performance improvement for millimeter-wave systems.

[00124] Current RFICs (Radio Frequency Integrated Circuits) for millimeter-wave systems show phase noise levels that are significantly higher than those for

conventional wireless systems in the UHF (Ultra High Frequency) and microwave bands. The oscillator PSD level increases by approximately 20 dBc/Hz per decade of increase of the carrier frequency. As a result, the center frequency tolerance for current millimeter-wave standards is quite high (± 20 ppm maximum for IEEE (Institute of Electrical and Electronics Engineers) standard 802.1 1 ad, for example) when compared to lower-frequency systems. Referring to FIG. 18, illustrated is a pair of diagrams showing two phase noise processes for two distinct models 1800 and 1 850, according to various aspects discussed herein. As seen in FIG. 18, in the time-domain, the phase noise is a time varying but correlated process, and the phase noise process can present noticeable variation in the reception of a symbol. The time-correlation of the phase noise among samples, as well as their variance, depends in part on the system numerology used.

[00125] Given conventional limits in constructing millimeter-wave PLL synthesizers with low-level phase noise, millimeter-wave devices can compensate by employing tracking and compensation techniques that are robust to high phase noise levels. This is true for both multi-carrier (e.g., OFDM-based) and single-carrier millimeter-wave systems. In OFDM systems (i.e., systems employing an OFDM or OFDM-based waveform) with frequency domain pilots, only the common phase error (common phase shift for all subcarriers) can be estimated and compensated for every OFDM symbol. However, single-carrier systems with time trackable training samples can potentially provide the capability to track and compensate instantaneous phase noise random process(es) within every symbol block of the single carrier waveform. Thus, in various aspects of the second set of techniques, time trackable training sequences can be employed (e.g., by processor(s) 51 0 and/or processor(s) 410) for OFDM-based single carrier waveforms, such as DFT-s-OFDM (or SC-FDMA), ZT-DFT-s-OFDMA, GI-DFT-s- OFDM, etc.

[00126] Referring to FIG. 19A, illustrated is a block diagram showing generation of an OFDM-based single carrier waveform, in connection with various aspects discussed herein. As shown in FIG. 19A, optional pre- and/or post- fix zeros can be attached (e.g., by processor(s) 51 0 and/or processor(s) 410) to a data sequence to form a time-domain sequence of length M. A DFT spreading (e.g., by processor(s) 510 and/or processor(s) 41 0) of size M, which can be followed by application of an IFFT (Inverse Fast Fourier Transform) of size N (e.g., by processor(s) 510 and/or processor(s) 410) to form a new time domain sequence of length N. This process is equivalent to upsampling and plus pulse shaping of the original data sequence to form an OFDM-based single carrier waveform. Optionally, one or more of a cyclic prefix (CP), zero post-fix (ZP), or guard interval (Gl) sequence can be attached to or inserted into (e.g., by processor(s) 510 and/or processor(s) 410) the resulted time domain block for easier mitigation of channel delay spread.

[00127] Depending on the optional choices, a specific OFDM-based (e.g., DFT-S- OFDM (SC-FDMA), ZT-DFT-s-OFDM, or GI-DFT-s-OFDM, etc.) waveform can be generated (e.g., by processor(s) 51 0 and/or processor(s) 41 0) via the process shown in FIG. 1 7A.

[00128] Since fast changing phase noise can lead to significant performance degradation, in various aspects of the second set of techniques, millimeter-wave systems can employ a time trackable training sequences to track and compensate for phase noise. Referring to FIG. 19B, illustrated is a block diagram showing generation of an OFDM-based single carrier waveform comprising samples of a time trackable training sequence, in connection with various aspects discussed herein. As seen in FIG. 1 9B, samples of a time domain training sequence can be inserted (e.g., by processor(s) 51 0 and/or processor(s) 41 0) among original time domain data symbols. Reference symbols can be distributed uniformly (e.g., with equal space between adjacent reference symbols) among data symbols. The reference sequence and its configuration can be known between a transmitter and receiver (e.g., via configuration signaling generated by processor(s) 51 0, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 41 0).

[00129] At the receiver (e.g., UE or BS), after channel equalization (e.g., by processor(s) 51 0 and/or processor(s) 41 0) the phase noise can be estimated and compensated for (e.g., by processor(s) 51 0 and/or processor(s) 41 0) as follows: (a) the equalized time-domain data plus reference symbols are available; (b) the phase noise can be estimated (e.g., by processor(s) 51 0 and/or processor(s) 41 0) at the reference symbols by measuring (e.g., by processor(s) 51 0 and/or processor(s) 41 0) the phase shifts; (c) as the phase noise samples are correlated (e.g., by processor(s) 51 0 and/or processor(s) 41 0), interpolation (e.g., mean estimation, MMSE (Minimum Mean-Square Error)-based interpolation, linear interpolation, etc.) can be employed (e.g., by processor(s) 51 0 and/or processor(s) 41 0) to estimate and track the phase noise process over time at the time location of data samples (statistical properties (autocorrelation or power spectral density (PSD)) of phase noise can be estimated (e.g. , by processor(s) 51 0 and/or processor(s) 41 0) for MMSE interpolation of phase noise); and (d) the phase noise can be compensated for at the data symbols (e.g., by processor(s) 51 0 and/or processor(s) 41 0) using the estimated phase noise sequence.

[00130] Referring to FIG. 20, illustrated is a graph comparing the performance of a SC-FDMA waveform in an ideal scenario involving no phase noise to two phase noise compensation techniques according to various aspects discussed herein. In the scenario illustrated in FIG. 20, the carrier frequency was 70 GHz, the frequency spacing was 480 KHz, the FFT size (N) was 1 024, and the number of allocated tones (M) was 600. The length of the time domain training sequence was P = 50. The training symbols were uniformly distributed among data symbols. The space between training samples was M/P = 12 samples.

[00131 ] Upon estimation of phase noise at the reference symbols (e.g., by

processor(s) 510 and/or processor(s) 410), the phase noise sequence can be interpolated over time (e.g., by processor(s) 510 and/or processor(s) 410), for example, using a MMSE interpolator. The PSD of the phase noise can be assumed to be available at the receiver (e.g., employing system 400 or system 500). As can be seen in FIG. 18, time-domain tracking can provide improved performance over simple common phase compensation (e.g., mean compensation).

[00132] The length of the training sequence (e.g., employed by processor(s) 410 and/or processor(s) 510) can depend on the PSD and other characteristics of phase noise. In various aspects, the position of training symbols within the data symbols and also the length of the training sequence can be adaptively changed according to one or more of: a UE category, phase noise characteristics, and/or UE feedback. Adaptive change of training sequence (e.g., by processor(s) 410 and/or processor(s) 51 0)can help to control overhead and/or improve performance for the compensation of phase noise.

[00133] Assuming a specific phase noise, n training samples per second can be employed (e.g., by processor(s) 41 0 and/or processor(s) 510) to effectively estimate and compensate phase noise impact. As discussed above, n depends on phase noise characteristics such as PSD. For an OFDM-based single carrier waveform with carrier spacing Af, the duration of an OFDM block (without CP or ZP) is T = 1/Af, hence the number of training symbols (e.g., employed by processor(s) 410 and/or processor(s) 51 0) for phase noise tracking is P = nT = ^. The overhead of the training sequence is nT/M, where M is the allocated bandwidth (or number of tones) to a UE. If training symbols are uniformly distributed, the space between adjacent ones is P/M (or less for ZT(GI)-DFT-s-OFDM). Therefore, the overhead of a training sequence can depend on the allocated bandwidth.

[00134] Referring to FIG. 21 , illustrated is a graph comparing the performance of a

SC-FDMA waveform in an ideal scenario involving no phase noise to phase noise compensation techniques involving variations in sequence length and spacing for reference symbols, according to various aspects discussed herein. In the scenario of

FIG. 21 , the allocated bandwidth M is reduced from 600 (as in FIG. 20) to 150 for the

.ςρ.-ΡΠ Δ waveform. The four curves illustrating phase noise compensation in FIG. 19 correspond to variations in the following options: (a) same step of training sequence (step=12) but shorter length of the sequence (P = 12) for both mean and MMSE interpolation, and (b) same length of the training sequence (P = 50) but with smaller spacing for reference symbols (step=3) for both mean and MMSE interpolation. As can be seen in FIG. 19, significant performance improvement results from MMSE if the original length of the training sequence is maintained, at increased overhead for this smaller allocated bandwidth (1 50 vs. 600).

[00135] In addition to phase noise characteristics and UE capabilities, the length of the training sequence can vary according to the allocated MCS (Modulation and Coding Scheme) of a UE. For example, for a very low MCS level where AWGN (Additive White Gaussian Noise) noise and interference are the dominant sources of error, phase noise compensation can be limited to common phase compensation which can be estimated by phase noise averaging. In such a scenario, a wider spacing of training symbols can be enough to estimate the common phase noise and time tracking of a phase noise random sequence can be avoided.

[00136] In a first example technique, a time domain training sequence (e.g., time- trackable sequence) as described herein can be inserted (e.g., by processor(s) 41 0 and/or processor(s) 510) within a data sequence (e.g., generated by processor(s) 410 and/or processor(s) 510) of an OFDM-based (e.g., DFT-s-OFDM, ZT-DFT-s-OFDM, Gl- DFT-s-OFDM, etc.) waveform (e.g., which can be transmitted via transceiver circuitry 420 and/or communication circuitry 520). In various such aspects, the time trackable sequence can be employed (e.g., via processor(s) 410 and/or processor(s) 510 of a receiving entity) for phase noise tracking and compensation. In various such aspects, time trackable sequence can be employed (e.g., by processor(s) 410 and/or

processor(s) 510) for residual CFO (Carrier Frequency Offset) estimation and compensation. In various such aspects, symbols of the time domain training sequence can be distributed uniformly among data symbols (e.g., processor(s) 410 and/or processor(s) 510 can insert the symbols of the time domain training sequence uniformly among the data symbols). In various such aspects, symbols of the time domain training sequence can be distributed non-uniformly (e.g., or in a trunk-based pattern, etc.) among data symbols (e.g., processor(s) 410 and/or processor(s) 510 can insert the symbols of the time domain training sequence non-uniformly (e.g., or in a trunk-based pattern, etc.) among the data symbols). As discussed herein, a trunk-based pattern can be an alternating pattern of data and reference signal(s), for example, [d d d r r d d d r r d d...], where r indicates a reference signal and d indicates data. In various such aspects the pilot configuration can be used in the downlink (e.g., generated by processor(s) 510, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410) and/or uplink (e.g., generated by processor(s) 410, transmitted via transceiver circuitry 420, received via communication circuitry 520, and processed by processor(s) 510).

[00137] In various aspects of the first example scenario associated with the second set of techniques, the training sequence can be configured (e.g., by processor(s) 410 and/or 510 configuring one or more of a length, subcarrier spacing, etc.) independently for each UE according to one or more of that UE's individual phase noise level and characteristics, a symbol duration, an allocated bandwidth, and/or a modulation-coding level. In various such aspects, the training sequence configuration of each UE can be determined (e.g., by processor(s) 410 and/or 510) based at least in part on one or more of: that UE's category or feedback from that UE. In various such aspects, the configuration (e.g., as indicated via configuration signaling generated by processor(s) 51 0, transmitted via communication circuitry 520, received via transceiver circuitry 420, and processed by processor(s) 410) of the training sequence used for phase noise estimation for each UE can comprise one or more of: setting and/or changing the length of training sequence for that UE, setting and/or changing the position of transmitted training sequence for that UE, or setting and/or changing the number and/or position of training symbols.

[00138] Referring to FIG. 22, illustrated is a flow diagram of an example method 2200 employable at a transmitting communication device that facilitates phase noise compensation based on a time-domain training sequence, according to various aspects discussed herein. In other aspects, a machine readable medium can store instructions associated with method 2200 that, when executed, can cause a transmitting

communication device to perform the acts of method 2200.

[00139] At 2210, a plurality of reference symbols of a time-domain training sequence can be generated.

[00140] At 2220, the plurality of reference symbols of the time domain training sequence can be inserted into a data sequence to generate a combined sequence comprising the data sequence and the plurality of reference symbols.

[00141 ] At 2230, an OFDM-based waveform can be gneated from the combined sequence. [00142] Additionally or alternatively, method 2200 can include one or more other acts described herein in connection with a transmitting communication device employing system 400 or system 500 and the second set of techniques.

[00143] Referring to FIG. 23, illustrated is a flow diagram of an example method 2300 employable at a receiving communication device that facilitates phase noise

compensation based on a time-domain training sequence, according to various aspects discussed herein. In other aspects, a machine readable medium can store instructions associated with method 2300 that, when executed, can cause a receiving

communication device to perform the acts of method 2300.

[00144] At 2310, an OFDM-based waveform can be demodulated to obtain a sequence of symbols comprising a data sequence and a plurality of reference symbols of a time-domain training sequence.

[00145] At 2320, an associated phase shift can be measured for each reference symbol of the plurality of reference symbols.

[00146] At 2330, an associated phase noise for each reference symbol can be estimated based on the associated phase shift(s).

[00147] At 2340, a time-dependent phase noise sequence can be estimated based on the estimated associated phase noise(s) for each reference symbol.

[00148] At 2350, an associated phase noise for the data sequence can be

compensated for based on the estimated time-dependent phase noise sequence.

[00149] Additionally or alternatively, method 2300 can include one or more other acts described herein in connection with a receiving communication device employing system 400 or system 500 and the second set of techniques.

Additional Example Embodiments

[00150] Examples herein can include subject matter such as a method, means for performing acts or blocks of the method, at least one machine-readable medium including executable instructions that, when performed by a machine (e.g., a processor with memory, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like) cause the machine to perform acts of the method or of an apparatus or system for concurrent communication using multiple communication technologies according to embodiments and examples described.

[00151 ] Example 1 is an apparatus configured to be employed in a communication device, comprising: a memory interface; and processing circuitry configured to:

generate a plurality of reference symbols of a time domain training sequence; insert the plurality of reference symbols into a data sequence to generate a combined sequence comprising the data sequence and the plurality of reference symbols; generate an OFDM (Orthogonal Frequency Division Multiplexing)-based waveform from the combined sequence; and send the plurality of reference symbols to a memory via the memory interface.

[00152] Example 2 comprises the subject matter of any variation of any of example(s) 1 , wherein the combined sequence comprises the plurality of reference symbols uniformly distributed among the data sequence.

[00153] Example 3 comprises the subject matter of any variation of any of example(s) 1 , wherein the combined sequence comprises the plurality of reference symbols nonuniform^ distributed among the data sequence or distributed in a trunk based pattern among the data sequence.

[00154] Example 4 comprises the subject matter of any variation of any of example(s) 1 -3, wherein the OFDM-based waveform is one of a DFT-s-OFDM waveform, a ZT- DFT-s-OFDM waveform, or a GI-DFT-s-OFDM waveform.

[00155] Example 5 comprises the subject matter of any variation of any of example(s) 1 -3, wherein the communication device is a gNB (next Generation Node B), wherein the time domain training sequence is associated with a UE (User Equipment), wherein the processing circuitry is further configured to generate configuration signaling that indicates one or more parameters associated with the time domain training sequence, and wherein the one or more parameters comprise at least one of a length of the time domain training sequence, a positioning of the reference symbols of the reference symbols of the time domain training sequence among the data sequence, or a number of the reference symbols of the time domain training sequence.

[00156] Example 6 comprises the subject matter of any variation of any of example(s) 5, wherein the processing circuitry is configured to generate the configuration signaling based at least in part on one or more of a category of the UE or feedback from the UE.

[00157] Example 7 comprises the subject matter of any variation of any of example(s) 5, wherein the processing circuitry is configured to generate the configuration signaling based at least in part on one or more of: a phase noise level associated with the UE, phase noise characteristics associated with the UE, a symbol duration associated with the OFDM-based waveform, an allocated bandwidth, or a MCS (Modulation and Coding Scheme) associated with the UE.

[00158] Example 8 comprises the subject matter of any variation of any of example(s) 1 -3, wherein the communication device is a UE (User Equipment), wherein the processing circuitry is further configured to process configuration signaling that indicates one or more parameters associated with the time domain training sequence, wherein the configuration signaling is based at least in part on one or more of a category of the UE or feedback the processing circuitry is configured to generate, and wherein the one or more parameters comprise at least one of a length of the time domain training sequence, a positioning of the reference symbols of the reference symbols of the time domain training sequence among the data sequence, or a number of the reference symbols of the time domain training sequence.

[00159] Example 9 comprises the subject matter of any variation of any of example(s) 1 -2, wherein the OFDM-based waveform is one of a DFT-s-OFDM waveform, a ZT- DFT-s-OFDM waveform, or a GI-DFT-s-OFDM waveform.

[00160] Example 10 comprises the subject matter of any variation of any of example(s) 1 -2 or 9, wherein the communication device is a gNB (next Generation Node B), wherein the time domain training sequence is associated with a UE (User Equipment), wherein the processing circuitry is further configured to generate configuration signaling that indicates one or more parameters associated with the time domain training sequence, and wherein the one or more parameters comprise at least one of a length of the time domain training sequence, a positioning of the reference symbols of the reference symbols of the time domain training sequence among the data sequence, or a number of the reference symbols of the time domain training sequence.

[00161 ] Example 1 1 comprises the subject matter of any variation of any of example(s) 10, wherein the processing circuitry is configured to generate the

configuration signaling based at least in part on one or more of a category of the UE or feedback from the UE.

[00162] Example 12 comprises the subject matter of any variation of any of example(s) 10-1 1 , wherein the processing circuitry is configured to generate the configuration signaling based at least in part on one or more of: a phase noise level associated with the UE, phase noise characteristics associated with the UE, a symbol duration associated with the OFDM-based waveform, an allocated bandwidth, or a MCS (Modulation and Coding Scheme) associated with the UE.

[00163] Example 13 comprises the subject matter of any variation of any of example(s) 1 -2 or 9-12, wherein the communication device is a UE (User Equipment), wherein the processing circuitry is further configured to process configuration signaling that indicates one or more parameters associated with the time domain training sequence, wherein the configuration signaling is based at least in part on one or more of a category of the UE or feedback the processing circuitry is configured to generate, and wherein the one or more parameters comprise at least one of a length of the time domain training sequence, a positioning of the reference symbols of the reference symbols of the time domain training sequence among the data sequence, or a number of the reference symbols of the time domain training sequence.

[00164] Example 14 is an apparatus configured to be employed in a communication device, comprising: a memory interface; and processing circuitry configured to:

demodulate an OFDM (Orthogonal Frequency Division Multiplexing)-based waveform to obtain a sequence of symbols comprising a data sequence and a plurality of reference symbols of a time domain training sequence; measure an associated phase shift for each reference symbol of the plurality of reference symbols; estimate an associated phase noise for each reference symbol based on the associated phase shift; estimate a time-dependent phase noise sequence based on the associated phase noise for each reference symbol; compensate for an associated phase noise for the data sequence based on the time-dependent phase noise sequence; and send the plurality of reference symbols to a memory via the memory interface.

[00165] Example 15 comprises the subject matter of any variation of any of example(s) 14, wherein the processing circuitry is further configured to: estimate a residual CFO (Carrier Frequency Offset) associated with the data sequence based on the time-dependent phase noise sequence; and compensate for the residual CFO associated with the data sequence based on the time-dependent phase noise sequence.

[00166] Example 16 comprises the subject matter of any variation of any of example(s) 14, wherein the sequence of symbols comprises the plurality of reference symbols distributed among the data sequence uniformly, non-uniformly, or in a trunk- based pattern.

[00167] Example 17 comprises the subject matter of any variation of any of example(s) 14-16, wherein the OFDM-based waveform is one of a DFT-s-OFDM waveform, a ZT-DFT-s-OFDM waveform, or a GI-DFT-s-OFDM waveform.

[00168] Example 18 comprises the subject matter of any variation of any of example(s) 14-16, wherein the communication device is a gNB (next Generation Node B), wherein the time domain training sequence is associated with a UE (User

Equipment), wherein the processing circuitry is further configured to generate configuration signaling that indicates one or more parameters associated with the time domain training sequence, and wherein the one or more parameters comprise at least one of a length of the time domain training sequence, a positioning of the reference symbols of the reference symbols of the time domain training sequence among the data sequence, or a number of the reference symbols of the time domain training sequence.

[00169] Example 19 comprises the subject matter of any variation of any of example(s) 14-16, wherein the communication device is a UE (User Equipment), wherein the processing circuitry is further configured to process configuration signaling that indicates one or more parameters associated with the time domain training sequence, and wherein the one or more parameters comprise at least one of a length of the time domain training sequence, a positioning of the reference symbols of the reference symbols of the time domain training sequence among the data sequence, or a number of the reference symbols of the time domain training sequence.

[00170] Example 20 comprises the subject matter of any variation of any of example(s) 14-18, wherein the communication device is a gNB (next Generation Node B), wherein the time domain training sequence is associated with a UE (User

Equipment), wherein the processing circuitry is further configured to generate configuration signaling that indicates one or more parameters associated with the time domain training sequence, and wherein the one or more parameters comprise at least one of a length of the time domain training sequence, a positioning of the reference symbols of the reference symbols of the time domain training sequence among the data sequence, or a number of the reference symbols of the time domain training sequence.

[00171 ] Example 21 comprises the subject matter of any variation of any of example(s) 14-18 or 20, wherein the communication device is a UE (User Equipment), wherein the processing circuitry is further configured to process configuration signaling that indicates one or more parameters associated with the time domain training sequence, and wherein the one or more parameters comprise at least one of a length of the time domain training sequence, a positioning of the reference symbols of the reference symbols of the time domain training sequence among the data sequence, or a number of the reference symbols of the time domain training sequence.

[00172] Example 22 is an apparatus configured to be employed in a gNB (next Generation Node B), comprising: a memory interface; and processing circuitry configured to: generate a PDCH (Physical Data Channel); generate a set of TRS (Tracking Reference Signals); map the PDCH and the set of TRS to each symbol of a plurality of symbols, wherein the PDCH and the set of TRS are multiplexed in the frequency domain; and send the set of TRS to a memory via the memory interface. [00173] Example 23 comprises the subject matter of any variation of any of example(s) 22, wherein the processing circuitry is configured to map the set of TRS to each symbol of the plurality of symbols based on an associated TRS design of a plurality of pre-defined TRS designs, wherein a first pre-defined TRS design of the plurality of pre-defined TRS designs has at least one of a distinct time density of TRS from a second pre-defined TRS design of the plurality of pre-defined TRS designs or a distinct frequency density of TRS from the second pre-defined TRS design.

[00174] Example 24 comprises the subject matter of any variation of any of example(s) 22, wherein the processing circuitry is configured to map the set of TRS to a set of edge RBs (Resource Blocks) of a bandwidth.

[00175] Example 25 comprises the subject matter of any variation of any of example(s) 22, wherein the processing circuitry is configured to map the PDCH to a first set of RBs (Resource Blocks) and to map the set of TRS to a second set of RBs that is contiguous with the first set of RBs.

[00176] Example 26 comprises the subject matter of any variation of any of example(s) 22-25, wherein the processing circuitry is configured to generate the set of

TRS without applying transform precoding to the set of TRS.

[00177] Example 27 comprises the subject matter of any variation of any of example(s) 22-25, wherein the set of TRS comprises a plurality of TRS groups, wherein each TRS group is associated with one or more UEs (User Equipments) of a plurality of

UEs.

[00178] Example 28 comprises the subject matter of any variation of any of example(s) 27, wherein the processing circuitry is configured to multiplex the plurality of TRS groups via FDM (Frequency Division Multiplexing).

[00179] Example 29 comprises the subject matter of any variation of any of example(s) 27, wherein a first TRS group of the plurality of TRS groups is associated with a plurality of APs (Antenna Ports), and wherein the processing circuitry is configured to distinguish between distinct APs of the plurality of APs via employing one of: distinct subcarriers for the distinct APs, distinct OCCs (Orthogonal Cover Codes) for the distinct APs, or distinct cyclic shifts for the distinct APs.

[00180] Example 30 comprises the subject matter of any variation of any of example(s) 27, wherein the processing circuitry is configured to generate higher layer signaling that indicates one or more of a presence of the set of TRS, a time density of the set of TRS, or a frequency density of the set of TRS. [00181 ] Example 31 is an apparatus configured to be employed in a UE (User Equipment), comprising: a memory interface; and processing circuitry configured to: demodulate a PDCH (Physical Data Channel); decode a set of TRS (Tracking

Reference Signals); estimate a phase noise associated with the set of TRS;

compensate for a phase noise associated with the PDCH based on the estimated phase noise associated with the set of TRS; and send the set of TRS to a memory via the memory interface.

[00182] Example 32 comprises the subject matter of any variation of any of example(s) 31 , wherein the processing circuitry is further configured to process configuration signaling that indicates one or more characteristics associated with the set of TRS, wherein the configuration signaling comprises higher layer signaling or one or more DCI (Downlink Control Information) messages.

[00183] Example 33 comprises the subject matter of any variation of any of example(s) 32, wherein the one or more characteristics associated with the TRS comprise a TRS pattern of a plurality of pre-defined TRS patterns, wherein a first predefined TRS design of the plurality of pre-defined TRS designs has at least one of a distinct time density of TRS from a second pre-defined TRS design of the plurality of pre-defined TRS designs or a distinct frequency density of TRS from the second predefined TRS design.

[00184] Example 34 comprises the subject matter of any variation of any of example(s) 32, wherein the one or more characteristics associated with the TRS comprise a TRS sequence of a plurality of pre-defined TRS sequences.

[00185] Example 35 comprises the subject matter of any variation of any of example(s) 32, wherein the one or more characteristics associated with the TRS comprise a TRS group of a plurality of TRS groups.

[00186] Example 36 comprises the subject matter of any variation of any of example(s) 31 -35, wherein the PDCH and the set of TRS are associated with an OFDM (Orthogonal Frequency Division Multiplexing)-based waveform.

[00187] Example 37 comprises the subject matter of any variation of any of example(s) 31 -35, wherein the processing circuitry is configured to determine at least one of a presence of the set of TRS, a time density of the set of TRS, or a frequency density of the set of TRS, based at least in part on one of: higher layer signaling, a Modulation and Coding Scheme (MCS), an allocated bandwidth, or a subcarrier spacing. [00188] Example 38 comprises an apparatus comprising means for executing any of the described operations of examples 1 -37.

[00189] Example 39 comprises a machine readable medium that stores instructions for execution by a processor to perform any of the described operations of examples 1 - 37.

[00190] Example 40 comprises an apparatus comprising: a memory interface; and processing circuitry configured to: perform any of the described operations of examples 1 -37.

[00191 ] The above description of illustrated embodiments of the subject disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various modifications are possible that are considered within the scope of such embodiments and examples, as those skilled in the relevant art can recognize.

[00192] In this regard, while the disclosed subject matter has been described in connection with various embodiments and corresponding Figures, where applicable, it is to be understood that other similar embodiments can be used or modifications and additions can be made to the described embodiments for performing the same, similar, alternative, or substitute function of the disclosed subject matter without deviating therefrom. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in breadth and scope in accordance with the appended claims below.

[00193] In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a "means") used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations. In addition, while a particular feature may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.