Title:
PIPELINED MULTIPLEXING FOR A MULTIPORT MEMORY
Document Type and Number:
WIPO Patent Application WO1996041485
Kind Code:
A3
Abstract:
A multiport interface for digital communication systems having pipelined multiplexing of port instructions for increased throughput. The multiport interface includes an analog delay for independent timing of asynchronous operations, such as memory accesses. The multiport interface also has an instruction pipeline and multiplexer to coordinate a number of port instructions.
Inventors:
THOMANN MARK R
VO HUY THANH
VO HUY THANH
Application Number:
PCT/US1995/015861
Publication Date:
February 13, 1997
Filing Date:
December 07, 1995
Export Citation:
Assignee:
MICRON TECHNOLOGY INC (US)
International Classes:
H04Q3/00; G06F9/38; H04Q11/04; H04L12/56; (IPC1-7): H04Q/
Foreign References:
| GB2077965A | 1981-12-23 | |||
| EP0399762A2 | 1990-11-28 |
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