Title:
POLYPHASE FILTER
Document Type and Number:
WIPO Patent Application WO/2019/202685
Kind Code:
A1
Abstract:
A first input terminal (11) is connected at the connection point of a drain terminal of a first transistor (1) and a gate terminal of a fourth transistor (4). A second input terminal (12) is connected at the connection point of a drain terminal of a third transistor (3) and a gate terminal of a second transistor. A first output terminal (21) through a fourth output terminal (24) are respectively connected to the source terminals of the first transistor (1) through the fourth transistor (4). A gate terminal of the first transistor (1) is connected to a drain terminal of the second transistor (2), and a gate terminal of the third transistor (3) is connected to a drain terminal of the fourth transistor (4).
Inventors:
TSURU MASAOMI (JP)
Application Number:
PCT/JP2018/016014
Publication Date:
October 24, 2019
Filing Date:
April 18, 2018
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H03H11/22
Foreign References:
| JP2001526868A | 2001-12-18 | |||
| JPH06104675A | 1994-04-15 | |||
| JP2017073632A | 2017-04-13 | |||
| JP2013509096A | 2013-03-07 |
Other References:
See also references of EP 3761507A4
Attorney, Agent or Firm:
TAZAWA, Hideaki et al. (JP)
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