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Title:
POWER SUPPLY OUTPUT DEVICE
Document Type and Number:
WIPO Patent Application WO/2021/019216
Kind Code:
A1
Abstract:
This application relates to a power supply output device. The power supply output device converts an input from a DC-DC convertor into a bipolar voltage output for a gate driver circuit driving a power switch. The power output supply device contains an adjusting circuit which measures the output of the gate driver circuit at the gate of the power switch, and adjusts the bipolar voltage output in order to maintain the output of the gate driver circuit at a predetermined voltage. The power supply output device provides a cost effective technique to regulate the peak positive voltage input into the gate of the power switch at a required voltage, regardless of any fluctuations or losses.

Inventors:
WARNES FRANK (GB)
Application Number:
PCT/GB2020/051768
Publication Date:
February 04, 2021
Filing Date:
July 23, 2020
Export Citation:
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Assignee:
MURATA MANUFACTURING CO (JP)
MURATA POWER SOLUTIONS MILTON KEYNES LTD (GB)
International Classes:
H02M1/08; H03K17/06
Domestic Patent References:
WO2019030516A12019-02-14
Foreign References:
EP2797233A22014-10-29
US20080123382A12008-05-29
Attorney, Agent or Firm:
REDDIE & GROSE LLP (GB)
Download PDF:
Claims:
CLAIMS

1. A power supply output device for a DC-DC convertor configured to provide a supply voltage, the power supply output device comprising:

a supply input for receiving a supply voltage from the DC-DC converter; a voltage dividing element configured to convert the supply voltage into a bipolar voltage output for supply to a gate driver circuit, the bipolar voltage output having first and second output voltage values;

a voltage clamping element configured to initially set one of the first or second output voltage values of the bipolar voltage output to a first

predetermined voltage;

an output for supplying the bipolar voltage output to a gate driver circuit, the gate driver circuit outputting an output based on the bipolar output voltage to drive the gate of a switch; and

an adjustment circuit configured to adjust the one of the first or second output voltage values of the bipolar voltage output based on the output of the gate driver circuit, in order to maintain the output of the gate driver circuit at a second predetermined voltage.

2. The power supply output device of claim 1 wherein the device comprises a direct gate sense input configured to receive the output of the gate driver circuit.

3. The power supply output device of claim 2 wherein the direct gate sense input is connected to the adjustment circuit.

4. The power supply output device of claims 2 or 3 wherein the device comprises an output return input configured to receive a feedback voltage signal from the switch driven by the gate driver circuit.

5. The power supply output device of claim 4 wherein the output return input is connected to the intermediate point of the voltage dividing element.

6. The power supply output device of claims 4 or 5 wherein the output return input is connected to the adjustment circuit.

7. The power supply output device of any of claims 4 to 6 wherein the supply input and the output comprise an upper supply rail and a lower supply rail, between which the voltage dividing element and the adjustment circuit are connected.

8. The power supply output device of claim 7 wherein the adjustment circuit

comprises:

a peak detection element configured to receive the output of the gate driver circuit and output a signal based on the peak positive value of the output of the gate driver circuit.

9. The power supply output device of claim 8 wherein the peak detection element is a diode or a P-channel MOSFET or a Schottky diode or a sample and hold circuit.

10. The power supply output device of claim 8 or 9 wherein the adjustment circuit further comprises:

a reference diode connected between the upper supply rail and the output return input;

a first capacitor connected between the reference terminal of the reference diode and the cathode of the reference diode;

a second capacitor connected between the output of the peak detection element and the output return input;

a resistor connected between the output return input and the lower supply rail; and

a potential divider connected between the output of the peak detection element and the output return input;

wherein the reference terminal of the reference diode is connected to the midpoint of the potential divider.

11. The power supply output device of claim 10 wherein the reference diode is

configured to allow current to flow when the output of the gate driver circuit is above the second predetermined voltage.

12. The power supply output device of claim 8 or 9 wherein the adjustment circuit further comprises:

a first switching element connected between the upper supply rail and the output return input; a capacitor connected between the output of the peak detection element and the output return input;

a first resistor connected between the output return input and the lower supply rail; and

a Zener diode and a second resistor connected in series between the output of the peak detection element and the output return input;

wherein the first switching element is connected to a point between the Zener diode and the second resistor.

13. The power supply output device of claim 12 wherein the first switching element is a transistor.

14. The power supply output device of claims 12 or 13 wherein the first switching element is configured to switch on when the output of the gate driver circuit is above the second predetermined voltage.

15. The power supply output device of claim 8 or 9 wherein the adjustment circuit further comprises:

an operational amplifier connected to the upper supply rail via the positive power supply terminal of the operational amplifier, and connected to the output return input via the negative power supply terminal of the operational amplifier;

a capacitor connected between the output of the peak detection element and the output return input;

a first resistor connected between the output return input and the lower supply rail; and

a Zener diode and a second resistor connected in series between the upper supply rail and the output return input; and

a potential divider connected between the output of the peak detection element and the output return input;

wherein the inverting input of the operational amplifier is connected to the midpoint of the potential divider, the non-inverting input of the operational amplifier is connected to a point between the Zener diode and the second resistor, and the output of the operational amplifier is connected to the positive power supply terminal of the operational amplifier.

16. The power supply output device of any of claims 7 to 15 wherein the voltage clamping element is connected between the output return input and the upper supply rail.

17. The power supply output device of claim 16 wherein the voltage clamping

element comprises one or more Zener diodes, and wherein the first

predetermined voltage is determined by the breakdown voltage of the one or more Zener diodes.

18. The power supply output device of claim 17 wherein the voltage clamping

element further comprises one or more switching elements configured to disconnect the one or more Zener diodes when a signal is received at the direct gate sense input.

19. The power supply output device of claim 18 wherein the first predetermined

voltage and the second predetermined voltage are equal.

20. The power supply output device of claims 10 or 11 wherein the reference diode is the voltage clamping element, and wherein the adjustment circuit further comprises a second resistor connected between the output of the peak detection element and the upper supply rail.

21. The power supply output device of any of claims 12 to 14 wherein:

the adjustment circuit further comprises a third resistor connected between the output of the peak detection element and the upper supply rail; the Zener diode, the second resistor and the third resistor are the voltage clamping element; and

the first predetermined voltage is determined in part by the breakdown voltage of the Zener diode.

22. The power supply output device of claim 15 wherein the operational amplifier is the voltage clamping element, and wherein the adjustment circuit further comprises a third resistor connected between the output of the peak detection element and the upper supply rail.

23. The power supply output device of any preceding claim wherein the voltage

dividing element comprises a first capacitor and a second capacitor in series.

24. A DC-DC convertor including the power supply output device of any preceding claim.

25. A power switch gate drive system comprising:

a DC-DC convertor;

a gate driver circuit;

a switch configured to receive an output of the gate driver circuit; and the power supply output device of any of claims 1 to 23.

Description:
POWER SUPPLY OUTPUT DEVICE

TECHNICAL FIELD

This application relates to a power supply output device, and in particular to a power supply output device suitable for bipolar gate drive applications.

BACKGROUND ART

The gate drive voltage requirements for power switches, including but not limited to Insulated-gate bipolar transistors (IGBT), Silicon Carbide MOSFETs (SIC) and standard Silicon MOSFETs (MOS), are varied and numerous, especially with the newer emerging technologies such as SIC and Gallium Nitride (GaN). Increasingly in fields with power switch gate drive applications, such as those in motor drives, inverters, uninterruptible power sources (UPS), solar power, electric vehicles and so on, an accurate positive and negative (bipolar) voltage is required from a supply voltage, typically 9V, 12V, or 25V. One problem specific to GaN switches is the need for strict accuracy of the positive voltage at the gate terminal of the switch. Generally this requires a more expensive DC-DC convertor with good regulation.

Figure 1 shows a typical configuration of a gate drive system 100 of the prior art for driving the gate terminal of a power switch. In Figure 1 , a DC-DC convertor 102 provides a voltage supply to an output unit 104. The output unit 104 could be a built in component of the DC-DC convertor 102, or could be a separate unit. The output unit 104 outputs a bipolar voltage, +V gate and -V gate, to a gate driver circuit 106. The gate driver circuit 106 outputs a signal, V gate, to drive the gate terminal of a power switch 108. The power switch 108 may be an IGBT, SIC, MOS, GaN, or the like. The power switch 108 is connected by an output return line 110 to the output unit 104.

Figure 2a shows the configuration of the gate drive system 100 of Figure 1 in more detail. In the gate drive system 100 of Figure 2a the DC-DC convertor 102 supplies a voltage to the output unit 104. This supply from the DC-DC converter 102 is an isolated supply. The exact topology is not important. It could be a push pull, flyback or forward converter, for example. In Figure 2a the DC-DC convertor 102 supplies a voltage of 9V as an example. An example of the circuitry of the output unit 104 is shown in Figure 2a, and will be discussed further in Figure 2b. The output unit 104 outputs a bipolar voltage, +V gate and -V gate, to the gate driver circuit 106. The bipolar voltages are not necessarily equal in magnitude. They may, for example, be +6V and -3V respectively. The gate driver circuit 106 outputs to the gate terminal of a power switch 108 a signal, V gate, alternating between +V gate and -V gate as a Pulse Width Modulation (PWM) signal. An example of a possible circuit for the gate driver circuit 106 is shown. An IGBT is shown in Figure 2a as an example of the power switch 108. The source or emitter terminal of the power switch 108 is connected back to the output unit 104, via the output return line 110. If the output unit is a built in component of the DC-DC convertor 102, the DC-DC convertor has a connection point for the output return line 110, as well as two connection points for the gate driver circuit 106 to connect to the output voltages +V gate and -V gate.

A simple and inexpensive way to achieve the bipolar gate voltages +V gate and -V gate is to use an output unit 104 containing a resistor and Zener diode in series, each with a parallel capacitor. One such output unit 104 is shown in Figure 2b.

Figure 2b shows a typical configuration of an output unit of the prior art. The output unit 104 consists of a first capacitor 152 in parallel with a resistor 154, and in series with a second capacitor 156. The second capacitor 156 is in parallel with a Zener diode 158. The first capacitor 152 and the resistor 154 are connected to an upper power rail 160, and the second capacitor 156 and the anode of the Zener diode 158 are connected to a lower power rail 170. The centre divider point 180 is positioned between the resistor 154 and the Zener diode 158, and is connected to ground in this example. When the output unit 104 is used in the gate drive system 100 of Figure 2a, the output return line 110 is connected to the centre divider point 180 of the output unit 104, the voltage supplied by the DC-DC convertor is supplied between the upper and lower power rails 160,170, and the gate driver circuit is connected to the upper and lower power rails 160,170.

In most applications the first capacitor 152 and second capacitor 156 are equal in capacitance, which means that when using the output unit 104 in the gate drive system of Figure 2a, the voltage across each capacitor will be half the supply voltage at start up. The resistor 154 and Zener diode 158 will then shunt current from one capacitor to the other in order to set the required gate voltages +V gate and -V gate at the respective +V gate and - V gate terminals. At start up the second capacitor 156 discharges rapidly through the Zener diode 158 as the Zener diode 158 is above its breakdown voltage. This causes the voltage over second capacitor 156 to decrease, therefore increasing the voltage over the first capacitor 152. When the voltage over the second capacitor 156 becomes equal to the Zener breakdown voltage of the Zener diode 158, the circuit is balanced with -V gate clamped at the Zener breakdown voltage.

Alternatively, an output unit such as in Figure 2c could be used. The output unit 104 of Figure 2c is similar to the output unit 104 of Figure 2b, except that the positions of the Zener diode and the resistor are swapped. In other words, in the output unit 104 of Figure 2c the first capacitor 152 is in parallel with a Zener diode 194 and the second capacitor 156 is in parallel with a resistor 198. The first capacitor 152 and the cathode of the Zener diode 194 are connected to the upper power rail 160, and the second capacitor 156 and the resistor 198 are connected to the lower power rail 170.

The output unit 104 of Figure 2c operates in a similar way to the output unit 104 of Figure 2b, except that at start up the Zener diode 194 is below its breakdown voltage, therefore no current flows through the Zener diode 194. This means the second capacitor 156 discharges through the resistor 198, increasing the voltage over the first capacitor 152. When the voltage over the first capacitor 152 becomes equal to the Zener breakdown voltage of the Zener diode 194, current is allowed through the Zener diode 194, and the circuit is balanced with +V gate clamped at the Zener breakdown voltage.

Another example of a gate drive system of the prior art is shown in Figure 3. In this gate drive system 200, a gate driver circuit 106 is again used to drive the gate terminal of a power switch 108, with the same examples as in Figure 2a being used in Figure 3. However, instead of the DC-DC convertor and output unit configuration of Figure 2a, a flyback DC-DC convertor 202 is used to supply the bipolar output voltage to the gate driver circuit 106 in Figure 3. The flyback convertor uses a multicoil transformer to produce +V gate and -V gate as two separate outputs, with respect to the output return line 110. Although a flyback DC- DC convertor has been used as an example in Figure 3, any isolated topology DC-DC convertor that produces two separate outputs can be used.

Figure 4 shows a disadvantage of both the system of Figure 2a with either output unit alternative, and the system of Figure 3. Figure 4 is a graph showing the signal V gate output to the gate terminal of the power switch 108 by the gate driver circuit 106. In this example, the output unit 104 or the flyback convertor 202 are set to produce +V gate and -V gate at +6V and -3V respectively, so as to provide the signal V gate between exactly +6V and -3V to the gate of the power switch 108. However, due to voltage drops in the gate driver circuit 106 of, for example, about 1V, the gate of the power switch 108 only sees about +5.5V and - 2.5V. GaN devices require +6V±0.25V and -3V±1V, so the voltage seen by the gate of the power switch 108 is outside the limit in this example.

Furthermore, for the system of Figure 3 and the system of Figure 2a using the output unit 104 of Figure 2b, if the DC-DC convertor 102 or flyback convertor 202 were a non- regulated supply with, for example, a ±10% variation on the input supply, it would be difficult to keep the voltage input to the gate of the power switch 108 within the specified

requirements. This is true even if the output was increased to compensate for the gate driver circuit 106 voltage drop.

Previous attempts to achieve tight accuracy of the positive gate voltage include using a tightly regulated DC-DC convertor to compensate for input changes, or connecting an unregulated DC-DC convertor to a tightly regulated input supply. Both of these solutions are expensive. Further attempts include measuring or estimating the voltage drop in the gate driver circuit, and adding extra voltage to the gate drive DC-DC convertor output to compensate. However, this cannot be done for all gate drive circuits. Another solution involves adding a linear regulator to the input or output of the DC-DC convertor. Again this adds complexity and therefore cost.

We have appreciated that it would be desirable to provide a solution to the problems discussed above.

SUMMARY OF THE INVENTION

The invention is defined by the independent claims, to which reference should now be made. Advantageous features are set out in the dependent claims.

The invention provides a method to regulate the gate voltage by sensing directly from the gate. This not only allows the use of a low cost unregulated DC-DC convertor but also compensates for voltage drops in the gate driver integrated circuit.

The power supply output device allows the peak positive voltage input into a power switch to be regulated at the required voltage. The power supply output device is able to keep the peak positive voltage of V gate at the desired, correct voltage even when there are losses or fluctuations in the gate driver circuit. Furthermore, the power supply output device is able to keep the peak positive voltage of V gate at the correct voltage when there are fluctuations in the power supply. The power supply output device provides an inexpensive solution to the problems presented by the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described in relation to the accompanying drawings, in which:

Figure 1 shows a configuration of a gate drive system of the prior art;

Figure 2a shows a configuration of a gate drive system of the prior art;

Figure 2b shows an output unit of the prior art;

Figure 2c shows an alternative output unit of the prior art;

Figure 3 shows a configuration of a gate drive system of the prior art;

Figure 4 is a graph showing the disadvantage of gate drive systems such as that in Figures 2a and 3.

Figure 5 shows a configuration of a gate drive system of the first exemplary embodiment; Figure 6 shows a configuration of a power supply output device of the first exemplary embodiment;

Figure 7 is a graph showing the advantages of the first exemplary embodiment;

Figure 8 shows a configuration of a power supply output device of the second exemplary embodiment;

Figure 9a is a graph showing the advantages of the second exemplary embodiment;

Figure 9b is a graph showing the advantages of the second exemplary embodiment;

Figure 10 shows a configuration of a power supply output device of the third exemplary embodiment;

Figure 11 shows a configuration of a power supply output device of the fourth exemplary embodiment;

Figure 12a is a graph showing the advantages of the fourth exemplary embodiment;

Figure 12b is a graph showing the advantages of the fourth exemplary embodiment;

Figure 13 shows a configuration of a power supply output device of the fifth exemplary embodiment;

Figure 14 shows a configuration of a power supply output device of the sixth exemplary embodiment;

Figure 15a is a graph showing the advantages of the sixth exemplary embodiment;

Figure 15b is a graph showing the advantages of the sixth exemplary embodiment;

Figure 16 shows a configuration of a power supply output device of the seventh exemplary embodiment;

Figure 17 shows a configuration of a power supply output device of the eighth exemplary embodiment;

Figure 18 shows a configuration of a power supply output device of the ninth exemplary embodiment;

Figure 19 shows a configuration of a power supply output device of the tenth exemplary embodiment;

DETAILED DESCRIPTION

This application relates to a power supply output device. The power supply output device converts an input from a DC-DC convertor into a bipolar voltage output for a gate driver circuit driving a power switch. The power output supply device contains a circuit which measures the output of the gate driver circuit at the gate of the power switch, and adjusts the bipolar voltage output in order to maintain the output of the gate driver circuit at a

predetermined voltage. The power supply output device provides a cost effective technique to regulate the peak positive voltage input into the gate of the power switch at a required voltage, regardless of any fluctuations or losses.

First Exemplary Embodiment

Figure 5 shows an example of a configuration of a gate drive system of the first exemplary embodiment. In the gate drive system 300 of Figure 5 a DC-DC convertor 302 provides a voltage supply to an output unit 304. This supply from the DC-DC converter 302 is an isolated supply. The exact topology is not important. It could be a push pull, flyback or forward converter, for example. The output unit 304 could be a built in component of the DC- DC convertor 302, or could be a separate unit. The output unit 304 outputs a bipolar voltage, +V gate and -V gate, to a gate driver circuit 306. These voltages are not necessarily equal in magnitude. For example, for a 9V supply from the DC-DC convertor, +V gate and -V gate may be +6V and -3V respectively, with respect to the output return line voltage. The gate driver circuit drives the gate terminal of a power switch 308. The gate driver circuit 304 outputs to the gate terminal of a power switch 306 a signal, V gate, alternating between +V gate and -V gate, as a Pulse Width Modulation (PWM) signal. The power switch 308 may be an IGBT, SIC, MOS, GaN, or the like. The source or emitter of the power switch 308 is connected by an output return line 310 to the output unit 304.

Furthermore, the configuration of the gate drive system 300 of Figure 5 includes a Direct Gate Sense (DGS) line 312. The DGS line 312 connects the gate terminal 314 of the power switch 308 or the output terminal of the gate driver circuit 306 directly to the output unit 304. Therefore, the signal, V gate, produced by the gate driver circuit 306 and input into the gate terminal of the power switch is also input into the output unit 304.

Throughout this specification, the voltage values of the poles of the bipolar gate voltages are given with respect to the voltage of the output return line 310. The output return line is connected to the source or emitter of the power switch 308, and therefore +V gate and -V gate are given with respect to the voltage of the source or emitter of the power switch 308. Throughout this specification the convention used is that the output return line is at zero volts. However the output return line does not have to be at zero volts. Any other convention could be used.

Figure 6 shows an example of a power supply output device of the first exemplary embodiment, which can be used as the output unit 304. The power supply output device 400 includes a voltage dividing element 402, a voltage clamping element 404 and an adjusting circuit 406. The voltage dividing element 402 is connected between an upper supply rail 408 and a lower supply rail 410. The upper supply rail 408 and lower supply rail 410 are suitable for connection to the output of a DC-DC convertor, such as the DC-DC convertor 302 of Figure 5. The voltage dividing element 402 is also connected to an output return line 412.

The adjusting circuit 406 is connected between the upper supply rail 408 and the lower supply rail 410, and is connected to the output return line 412 and a DGS line 414. The voltage clamping element 404 is connected between the upper supply rail 408 and the output return line 412, and is also connected to the adjusting circuit 406.

When the power supply output device 400 is used as the output unit 304, a voltage is supplied to the power supply output device 400 from the DC-DC convertor 302 between the upper supply rail 408 and lower supply rail 410. The gate driver circuit 306 is connected to the upper supply rail 408 and the lower supply rail 410, and uses the output of the power supply output device 400 to produce the signal, V gate, to be input into the gate terminal 314 of the power switch 308. The output return line 412 of the power supply output device 400 is connected to the source or emitter of the power switch 308, via the output return line 310 of Figure 5. The DGS line 414 of the power supply output device 400 is connected directly to the output of the gate driver circuit 306 at the gate terminal 314 of the power switch 308, via the DGS line 312 of Figure 5. If the power supply output device 400 is a built in component of the DC-DC convertor 302, the DC-DC convertor has a connection point for the output return line 310 to connect to the output return line 412 of the power supply output device 400, a connection point for the DGS line 312 to connect to the DGS line 414 of the power supply output device 400, and two connection points for the gate driver circuit 306 to connect to the upper power rail 408 and the lower power rail 410 of the power supply output device 400.

At switch on, the voltage supplied by the DC-DC convertor 302 is divided by the voltage dividing element 402. The voltage clamping element 404 then adjusts this voltage division, and clamps the voltages in order to set the gate voltages +V gate and -V gate at an initial value. For example, for a 9V supply from the DC-DC convertor, +V gate and -V gate may be initially set at +6V and -3V respectively. In the first exemplary embodiment, before a signal is input into the DGS line 514, the power supply output device 500 starts with the positive gate voltage +V gate supply within the specifications for the power switch 308, for example +6V here. However the peak positive voltage of the driver circuit 306 output V gate is likely to be lower due to losses in the gate driver circuit 306.

When the gate signal, V gate, produced by the gate driver 306 is input to the DGS line 414, the adjusting circuit 406 measures the actual peak positive voltage seen by the power switch 308. For example, due to voltage drops in the gate driver circuit 306 of about 1 V, the gate terminal 314 of the power switch 308 may only see about +5.5V as the peak positive voltage, rather than the +6V output through +V gate. The voltage clamping element 404 is configured to switch off when a signal is input into adjusting circuit 406 via the DGS line 414. The adjusting circuit 406 then adjusts and re-clamps the voltage division such that an accurate positive peak voltage is seen at the power switch 308. For example, if the adjusting circuit 406 detects that the power switch 308 only received a peak positive voltage of +5.5V, then the adjusting circuit 406 will adjust and clamp the voltage division such that +V gate is, for example, +6.5V. This means that the power switch 308 will see a peak positive voltage of +6V at the gate terminal 314 after the losses through the gate driver circuit 306.

In the first embodiment, the Direct Sense Gate connection made between the actual power switch gate terminal 314 and the output unit 304 allows the power supply output device to sense the signal V gate, and adjust the positive gate voltage +V gate with respect to the output return voltage so that the peak positive voltage of V gate is always at the desired level, for example, +6V.

Figure 7 demonstrates this advantage of the first exemplary embodiment. Figure 7 shows the signal V gate seen by the power switch 308. The operation of the first

embodiment results in a peak positive voltage of +6V, which is the voltage desired in this example. The voltage of +V gate and -V gate is also shown. These have been appropriately set by the adjusting circuit 406 at +6.5V and -2.5V, in order to compensate for any losses in the driver circuit. This means an accurate positive voltage required for power switches such as GaN devices can be achieved.

The power supply output device 400 would also compensate for other effects. For example, the circuit would adjust the output voltages +V gate and -V gate to maintain the positive peak voltage of V gate in the event of random fluctuations or changes in the power supply voltage.

Accurate control of the peak positive voltage of V gate in this way results in the peak negative voltage of V gate becoming reduced, being reduced to about -2.2V in the example in Figure 7. However, the peak negative voltage does not have to be as accurate as the peak positive voltage in power switch applications.

Even with a ±10% variation on the input supply, the peak positive voltage of V gate will stay the same. Furthermore, this does not affect the under voltage and overvoltage lock out sensing often found in gate drive controllers, because the 9V total supply to the controller remains the same, only the positive and negative gate voltages +V gate and -V gate with respect to the output return (mid-divider) voltage are adjusted.

This invention could be applied to any power switch gate drive application, including but not limited to those in motor drives, inverters, uninterruptible power sources (UPS), solar power, electric vehicles and so on.

Although in this embodiment the adjusting circuit 406 is configured to clamp the positive gate voltage +V gate, the positive and negative sides could be reversed so that the adjusting circuit 406 clamps the negative gate voltage -V gate instead, if accurate control of the negative gate voltage -V gate was desired.

The voltage values used in this embodiment are for exemplary reasons only and are not limiting.

Second Exemplary Embodiment

A power supply output device of the second exemplary embodiment is shown in Figure 8. The power output supply of the second exemplary embodiment is a specific example of a power output supply such as in the first exemplary embodiment. The power supply output device 500 of Figure 8 includes a voltage dividing element 502, a voltage clamping element 504 and an adjusting circuit 506. The voltage dividing element 502 is connected between an upper supply rail 508 and a lower supply rail 510. The upper supply rail 508 and lower supply rail 510 are suitable for connection to the output of a DC-DC convertor, such as the DC-DC convertor 302 of Figure 5. The voltage dividing element 502 is also connected to an output return line 512. The voltage clamping element 504 is connected between the upper supply rail 508 and the output return line 512, and is also connected to the adjusting circuit 506. The adjusting circuit 506 is connected between the upper supply rail 508 and the lower supply rail 510, is connected to an output return line 512 and the voltage clamping element 504, and is also connected to a DGS line 514.

The voltage dividing element 502 includes a first capacitor 550 and a second capacitor 552 connected in series between the upper supply rail 508 and the lower supply rail 510. The output return line 512 is connected to the voltage dividing element 502 between the first capacitor 550 and a second capacitor 552. The first and second capacitors 550,552 may have different capacitance values, or equal capacitance values. Preferably, the capacitance values of the first and second capacitor are equal for simplicity and cost reduction.

The voltage clamping element 504 includes one or more Zener diodes 554 connected in series and in the same direction, a first switching element 556, a first resistor 558, and a second switching element 560. Each of the first switching element 556 and second switching element 560 can be a transistor, for example, a bipolar transistor or a field effect transistor such as a MOSFET. N channel MOSFETs have been used as an example in the second exemplary embodiment. The one or more Zener diodes 554 in series are connected between the upper supply rail 508 and a drain of the first switching element 556.

A Zener diode cathode is connected to the upper power supply rail 508 and a Zener diode anode is connected to the drain of the first switching element 556. The first resistor 558 is connected between the upper supply rail 508 and the gate of the first switching element 556. The gate of the first switching element is connected to the drain of the second switching element 560. The sources of the first switching element 556 and the second switching element 560 are connected to the output return line 512. In an alternative embodiment, the one or more Zener diodes 554 could be replaced with one or more reference diodes.

The adjusting circuit 506 includes a reference diode 562 with the cathode connected to the upper supply rail 508 and the anode connected to the output return line 512. A second resistor 564 is connected between the output return line 512 and the lower supply rail 510. A third capacitor 566 is connected between the cathode terminal and the reference terminal of the reference diode 562. The adjusting circuit 506 includes a peak detection element 568 which is connected to the DGS line 514. The peak detection element 568 may be a peak rectifier, for example a diode, a P channel MOSFET, a Schottky diode, or the like. In the second exemplary embodiment, a diode has been used as the peak detection element 568.

A fourth capacitor 570 is connected between the output of the peak detection element 568 and the output return line 512. A third resistor 572 and a fourth resistor 574 in series are also connected between the output of the peak detection element 568 and the output return line 512, in parallel with the fourth capacitor 570. The reference terminal of the reference diode 562 is connected to a point in-between the third resistor 572 and the fourth resistor 574. The output of the peak detection element 568 is connected to the gate of the second switching element 560 of the voltage clamping element 504. In an alternative embodiment, rather than peak rectifying the signal from the DGS line 514 and inputting the peak rectified signal into the fourth capacitor 570, a sample and hold circuit could be used. The advantage of a sample and hold circuit is that there would be no voltage drop over a diode such as in the case where a diode is used as the peak detection element 568.

The power supply output device 500 of Figure 8 can be used as the output unit 304 in a system configured as in Figure 5. A voltage is supplied from the DC-DC convertor 302 between the upper supply rail 508 and the lower supply rail 510 of the power supply output device 500. This supply from the DC-DC converter 302 is an isolated supply. The exact topology is not important, it could be a push pull, flyback or forward converter, for example. The power supply output device 500 may be built into the DC-DC convertor 302, or may be a separate entity.

The gate driver circuit 306 is connected over the upper and lower supply rails 508,510 and uses the output of the power supply output device 500 to produce the signal V gate to be input into the gate terminal 314 of the power switch 308. The signal V gate is also input into the DGS line 514 of the power supply output device 500 via the DGS line 312. The source or emitter of the power switch 308 is connected to the output return line 512 of the power supply output device 500 via the output return line 310. If the power supply output device 500 is a built in component of the DC-DC convertor 302, the DC-DC convertor has a connection point for the output return line 110 to connect to the output return line 522 of the power supply output device 500, a connection point for the DGS line 312 to connect to the DGS line 514 of the power supply output device 500, and two connection points for the gate driver circuit 306 to connect to the upper power rail 508 and the lower power rail 510.

In the second exemplary embodiment, the peak detection element 568 is contained within the adjusting circuit 506 of the power supply output device 500. However in some embodiments, the peak detection element 568 could be contained in a separate unit positioned between the power supply output device and the DGS line 312.

At switch on the voltage supplied by the DC-DC convertor 302 appears across the voltage dividing element, +V supply with respect to -V supply in Figure 8. The voltage dividing element 502 then divides the voltage between the first capacitor 550 and the second capacitor 552. The first capacitor 550 and second capacitor 552 have equal capacitance so that the voltage is initially split equally between them. For example, if a 9V supply is used, the voltage drop across each of the capacitors would be 4.5V.

When no signal is input into the DGS line 514, there is no voltage at the gate of second switching element 560, and the second switching element 560 remains off. This allows the voltage at the gate terminal of the first switching element 556 to rise through the first resistor 558, which is acting as a pull up resistor. The first switching element 556 therefore turns on.

Because the second capacitor 552 has the second resistor 564 in parallel with it, the second capacitor 552 starts to discharge through the second resistor 564 and therefore the voltage across the first capacitor 550 starts to increase. When the voltage across the first capacitor 550 reaches the total Zener breakdown voltage of the one or more Zener diodes 554, the one or more Zener diodes 554 start to conduct. In the second exemplary embodiment, this total Zener breakdown voltage is chosen to be equal to the peak positive voltage required for the power switch 308, for example +6V if the switch specification is +6V. At the point where the Zener diodes conduct, the positive and negative gate voltages reach a balance where, in this case, +V gate is +6V with respect to the output return line 512, and -V gate is -3V with respect to the output return line 512. The reference diode 562 does not allow any current to flow through it when there is no signal input into the DGS line 514.

In the second exemplary embodiment, before a signal is input into the DGS line 514, the power supply output device 500 starts with the positive gate voltage +V gate supply within the specifications for the power switch 308, for example +6V here. However the peak positive voltage of the driver circuit 306 output V gate is likely to be lower due to losses in the gate driver circuit 306. Next, a signal V gate produced by the gate driver circuit 306 is input to the DGS line 514 via the DGS line 312. The pulse waveform of V gate is input into the peak detection element 568. As an example, the peak detection element 568 in the second exemplary embodiment is a diode which peak rectifies the signal V gate. This charges the fourth capacitor 570 to the peak positive value of V gate minus the voltage drop over the peak detection element 568. For example, in this case the peak positive voltage of V gate is +6V minus the losses in the gate driver circuit, and the voltage drop over the diode of the peak detection element 568 is 0.6V, therefore the fourth capacitor 570 charges to +5.4V minus the losses in the gate driver circuit 306. The second switching element 560 now has a positive voltage at its gate terminal and is therefore turned fully on. This causes the first switching element 556 to be turned off, which disconnects the one of more Zener diodes 554 of the voltage clamping element 504.

Once the first switching element 556 is switched off, the voltage across the first capacitor 550, and therefore the positive gate voltage +V gate, is no longer clamped to the Zener breakdown voltage of the one or more Zener diodes 554. The second capacitor 552 will then shunt current through the second resistor 564, causing the voltage over the first capacitor 550 to increase. This in turn causes an increase in the positive peak voltage of the pulse waveform of V gate, which is input into the peak detection element 568 via the DGS line 514. This further charges the fourth capacitor 570. The voltage over the fourth capacitor 570 is sensed by the adjustable reference diode 562 through the potential divider of the third and fourth resistors 572,574. The resistances of the third and fourth resistors 572,574 are selected so that when the voltage across the third and fourth resistors 572,574 reaches the required positive peak voltage of V gate, minus the voltage drop over the peak detection element 568, the reference diode 562 starts to shunt current. This clamps the voltage across the first capacitor 550. At this point the circuit is balanced with the voltage across the first capacitor 550 held at the required positive peak voltage of V gate plus the voltage to compensate for the losses in the gate driver circuit 306.

For example if +6V is required as the peak positive voltage of the gate driver circuit 305 output V gate, and the voltage drop over the diode of the peak detection element 568 is 0.6V, then the third and fourth resistors 572,574 are selected so that the reference diode 562 starts to shunt current when the voltage across the third and fourth resistors 572,574 reaches +6V-0.6V=5.4V. If only +5.5V is seen via the DGS line 514 at the gate of the power switch 308, the fourth capacitor will charge to +5.5V-0.6V=4.9V, and the reference diode will not shunt current. The first capacitor 550 will charge up until it reaches +6V+0.5V=6.5V, at which point the voltage across the third and fourth resistors 572,574 reaches +5.4V and the reference diode 562 will shunt current. Now the reference diode 562 is regulating the positive voltage +V gate such that the peak positive voltage of V gate is always +6V, by sensing the gate of the power switch 308 directly. The voltage values used here are for exemplary reasons only and are not limiting. Various alternatives are possible, for example if a Schottky diode is used as the peak detection element 568, the voltage drop over the peak detection element 568 would be lower. In this case, a different selection of third and fourth resistors 572,574 is needed to make the reference diode 562 shunt current when peak positive voltage of V gate is +6V.

The third capacitor 566 provides negative feedback, to prevent any input noise at the reference terminal of the reference diode 562 causing rapid fluctuations in the output at the cathode of the reference diode 562.

The power supply output device 500 of the second exemplary embodiment allows the peak positive voltage of V gate input into the power switch 108 to be held at the required voltage. The power supply output device 500 is able to keep the peak positive voltage of V gate at the correct voltage even when there are losses or fluctuations in the gate driver circuit 306. Furthermore, the power supply output device 500 is able to keep the peak positive voltage of V gate at the correct voltage when there are fluctuations in the power supply. The power supply output device 500 provides an inexpensive solution to the problems presented by the prior art.

The resulting gate voltage waveform V gate from the gate driving circuit 306 using the power supply output device 500 is shown in Figures 9a and 9b. To produce these graphs a 9V supply from the DC-DC convertor was used, and the components used were first and second capacitors 550,552 with a 4.7uF capacitance, two BZX84-3V0 Zener diodes as the one or more Zener diodes 554, two 2N7000 N channel MOSFETs as the first and second switching elements 556,560, a 10kQ first resistor 558, a TL431 reference diode 562, a 1 kQ second resistor 564, a 1 nF third capacitor 566, a 31 kQ third resistor 572, a 25kQ fourth resistor 574, a 10nF fourth capacitor 570, and a BAS70-06 diode as the peak detection element 568. Specific components and values given here are for exemplary purposes only. Various alternatives could be used, as would be understood by those skilled in the art.

Figure 9a shows the operation of the system when there is a voltage drop of 1 V in the gate driver circuit 306. The voltage clamping element 504 holds +V gate at +6V initially. At 2ms the DGS line 514 is connected to gate of the power switch 308. Initially the peak positive voltage seen at the gate of the power switch 308 is only +5.5V. The power output supply device 500 then increases +V gate until the peak positive voltage of V gate reaches +6V as desired in this example. The peak positive voltage of V gate is then kept at +6V by the circuit, even if there are fluctuations in the power supply or gate driver circuit 306 output.

Accurate control of the peak positive voltage of V gate in this way results in the peak negative voltage of V gate becoming reduced, being reduced to about -2V in the example in Figure 9a. However, the peak negative voltage does not have to be as accurate as the peak positive voltage in power switch applications.

Figure 9b is a similar graph to Figure 9a except that Figure 9b is the case where there is no voltage loss in the gate driver circuit 306. The voltage clamping element 504 holds +V gate at +6V initially. When the DGS line 514 is connected to the gate of the power switch 308, and the first switching element 556 is switched off, the peak positive voltage of V gate is already on specification for the power switch 308 being driven, in this case +6V. The reference diode 562 then maintains +V gate to keep the peak positive voltage of V gate at +6V. Both of Figures 9a and 9b demonstrate the advantage over the output of the prior art systems of Figures 2a to 3.

The slight deviations of the peak positive voltage of V gate in Figures 9a and 9b are a result of the peak rectification of the signal V gate. The fourth capacitor 570 will only be charged 50% of the time when a 50% duty cycle square wave is used for the PWM signal, V gate. This results in the fourth capacitor 570 being charged on average to slightly below the peak positive voltage of V gate minus the voltage drop over the peak detection element. This reduction can be compensated for by careful selection of the reference diode 562 and third and fourth resistors 572,574.

This invention could be applied to any power switch gate drive application, including but not limited to those in motor drives, inverters, uninterruptible power sources (UPS), solar power, electric vehicles and so on.

Although in this embodiment the positive gate voltage +V gate is regulated, to hold the peak positive voltage of the gate driver circuit output V gate at the required value, the power rails could be reversed so that accurate control of the peak negative voltage of V gate was performed, if accurate control of the peak negative voltage of V gate was desired.

Third Exemplary Embodiment

Figure 10 shows an example of a configuration of a gate drive system 600 of the third exemplary embodiment. The third exemplary embodiment is the same as the first exemplary embodiment except that the voltage clamping element 604 is not connected directly to the adjusting circuit 606, other than via the upper power supply rail 608 and the output return line 612.

Furthermore, the power output supply 600 of the third exemplary embodiment differs from the first and second exemplary embodiments in that the power supply output device 600 starts, before V gate is input into the DGS line 312, with the positive gate voltage +V gate above the specifications for the power switch 308. For example, the power supply output device 600 of the third exemplary embodiment would start with a positive gate voltage +V gate of +7V for example, if +6V was required at the gate of the power switch 308. In the first and second exemplary embodiments, when a +6V peak positive voltage of V gate was required at the gate of the power switch 308, the power supply output device 500 started with +V gate on specification, at +6V, before the DGS line 514 was connected.

In the third exemplary embodiment, when the gate signal, V gate, produced by the gate driver 306 is input to the DGS line 614, the voltage clamping element 604 is configured to deactivate. This deactivation does not rely on a direct link to the voltage clamping element 604 in addition to the upper power supply rail 608 and the output return line 612, unlike the deactivation in the first exemplary embodiment. Instead in the third exemplary embodiment the deactivation of the voltage clamping element 604 happens automatically because the voltage set by the voltage clamping element is overridden by a lower voltage set by the adjusting circuit, as detailed below.

When the gate signal, V gate, produced by the gate driver 306 is input to the adjusting circuit 606 via the DGS line 614, the adjusting circuit 606 measures the actual peak positive voltage seen by the power switch 308. For example, due to voltage drops in the gate driver circuit 306 of about 1 V, the gate of the power switch 308 may only see about +6.5V as the peak positive voltage of V gate, rather than the +7V output through +V gate. The adjusting circuit 606 then adjusts and re-clamps the voltage division at a lower voltage, such that an accurate positive peak voltage is seen at the power switch 308. For example, if the adjusting circuit 606 detects that the power switch 308 received a peak positive voltage of +6.5V, then the adjusting circuit 606 will adjust and clamp the voltage division such that +V gate is, for example, +6.5V rather than +7V. This means that the power switch 308 will see a peak positive voltage of +6V after the loss through the gate driver circuit 306.

Fourth Exemplary Embodiment

A power supply output device of the fourth exemplary embodiment is shown in Figure 11. The power output supply of the fourth exemplary embodiment is a specific example of a power output supply such as in the third exemplary embodiment. The power supply output device 700 of Figure 11 includes a voltage dividing element 702, a voltage clamping element 704 and an adjusting circuit 706, connected as in the third exemplary embodiment. In the fourth exemplary embodiment the voltage clamping element 704 is connected to the adjusting circuit 706 via the output return line 712 only, and not via an additional connection as in the first and second exemplary embodiments. The voltage dividing element 702 and the adjusting circuit 706 are the same as the corresponding components of the second exemplary embodiment. The voltage dividing element 702 includes a first capacitor 750 and a second capacitor 752. The adjusting circuit 706 includes a reference diode 762, a first resistor 764, a third capacitor 766, a peak detection element 768, a fourth capacitor 770, a second resistor 772, and a third resistor 774. Similar alternatives described in the second exemplary embodiment are also possible in the fourth exemplary embodiment.

The voltage clamping element 704 of the fourth exemplary embodiment includes one or more Zener diodes 754 connected in series and in the same direction, between the upper supply rail 708 and the output return line 712. In an alternative embodiment, the one or more Zener diodes 754 could be replaced with one or more reference diodes.

The power supply output device 700 of Figure 11 can be used as the output unit 304 in a system configured as in Figure 5, in the same way as the power supply device 500 of the second exemplary embodiment.

At switch on the voltage supplied by the DC-DC convertor 302 appears across the voltage dividing element, +V supply with respect to -V supply in Figure 11. The voltage dividing element 702 then divides the voltage between the first capacitor 750 and the second capacitor 752. The first capacitor 750 and second capacitor 752 have equal capacitance so that the voltage is initially split equally between them. For example, if a 9V supply is used, the voltage drop across each of the capacitors would be 4.5V.

Because the second capacitor 752 has the second resistor 764 in parallel with it, the second capacitor 752 starts to discharge through the second resistor 764 and therefore the voltage across the first capacitor 750 starts to increase. The reference diode 762 does not allow any current to flow through it when there is no signal input into the DGS line 714.

When the voltage across the first capacitor 750 reaches the total Zener breakdown voltage one or more Zener diodes 754, the one or more Zener diodes 754 start to conduct. In the fourth exemplary embodiment, this total Zener breakdown voltage is chosen to be above the peak positive voltage required for the power switch 308, for example +6.6V if the switch specification is +6V. At the point where the Zener diodes conduct, the positive and negative gate voltages reach a balance where, in this case, +V gate is +6.6V with respect to the output return line 712, and -V gate is -2.4V with respect to the output return line 712.

Next, a signal V gate produced by the gate driver circuit 306 is input to the DGS line 714 via the DGS line 312. The pulse waveform of V gate is input into the peak detection element 768. As an example, the peak detection element 768 in the fourth exemplary embodiment is a diode which peak rectifies the signal V gate. This charges the fourth capacitor 770 to the peak positive voltage of V gate minus the voltage drop over the peak detection element 768. For example, in this case the peak positive voltage of V gate is +6.6V minus the losses in the gate driver circuit, and the voltage drop over the diode of the peak detection element 768 is 0.6V, therefore the fourth capacitor charges to +6V minus the losses in the gate driver circuit 306. The voltage across the fourth capacitor 770 is sensed by the adjustable reference diode 762 through the potential divider of the second and third resistors 772,774. The resistances of the second and third resistors 772,774 are selected so that when the voltage across the second and third resistors 772,774 is above the required positive peak voltage of V gate minus the voltage drop over the peak detection element 768, the reference diode 762 shunts current. This causes the first capacitor 750 to discharge through the reference diode 762. In this case, the voltage drop over the diode is 0.6V, so the reference diode 762 will shunt current from the first capacitor 750 when the voltage across the second and third resistors 772,774 is above +6V-0.6V=5.4V.

The decreasing voltage over the first capacitor 750 causes +V gate to decrease, and therefore causes the peak positive voltage of V gate to decrease, and thus the voltage over the second and third resistors 772,774 to decrease. The Zener diodes of the voltage clamping element 704 are now below their breakdown voltage, so current no longer flows through the voltage clamping element 704. When the voltage across the second and third resistors 772,774 reaches the required positive peak voltage of V gate minus the voltage drop over the peak detection element 768, the reference diode 762 clamps the voltage across the first capacitor 750. At this point the circuit is balanced with the voltage across the first capacitor 750 held at the required positive peak voltage of V gate plus the voltage to compensate for the losses in the gate driver circuit 306.

For example, here +6V is required as the peak positive voltage of the gate driver circuit 305 output, but in fact +6.2V is seen via the DGS line 714 at the gate of the power switch 308 from the initial +6.6V of +V gate. Therefore when V gate is input into the DGS line, the fourth capacitor charges to +6.2V-0.6V=5.6V and the voltage across the second and third resistors 772,774 is above +5.4V. The reference diode 762 therefore shunts current until the voltage over the first capacitor 750 reaches +6.6V-0.2V=6.4V. Now the reference diode 762 regulates the positive voltage +V gate such that the peak positive voltage of V gate is always +6V, by sensing the gate of the power switch 308 directly. The voltage values used here are for exemplary reasons only and are not limiting. Various alternatives are possible.

The third capacitor 766 provides negative feedback, to prevent any input noise at the reference terminal of the reference diode 762 causing rapid fluctuations in the output at the cathode of the reference diode 762.

The advantages of the fourth exemplary embodiment are similar to those of the first and second exemplary embodiments. The resulting gate voltage waveform V gate from the gate driving circuit 306 using the power supply output device 700 of the fourth exemplary embodiment is shown in Figures 12a and 12b. To produce these graphs a 9V supply from the DC-DC convertor was used, and the components used were first and second capacitors 750,752 with a 4.7uF capacitance, two BZX84-3V3 Zener diodes as the one or more Zener diodes 754, a TL431 reference diode 762, a 1kQ first resistor 764, a 1nF third capacitor 766, a 31 kQ second resistor 772, a 25kQ third resistor 774, a 10nF fourth capacitor 770, and a BAS70-06 diode as the peak detection element 768. Specific components and values given here are for exemplary purposes only. Various alternatives could be used, as would be understood by those skilled in the art.

Figure 12a shows the operation of the system when there is a voltage drop of 1 V in the gate driver circuit 306. The voltage clamping element 704 holds +V gate at +6.6V initially. At 2ms the DGS line 714 is connected to gate of the power switch 308. The peak positive voltage seen at the gate of the power switch 308 is +6V and is therefore already on specification. The peak positive voltage of V gate is then kept at +6V by the circuit, even if there are fluctuations in the power supply or gate driver circuit 306 output.

Accurate control of the peak positive voltage of V gate in this way means that the peak negative voltage of V gate is about -2V in the example in Figure 12a. However, the peak negative voltage does not have to be as accurate as the peak positive voltage in power switch applications.

Figure 12b is a similar graph to Figure 12a except that Figure 12b is the case where there is no voltage loss in the gate driver circuit 306. The voltage clamping element 704 holds +V gate at +6.6V initially. When the DGS line 714 is connected to the gate of the power switch 308, a peak positive voltage of V gate equal to +6.6V is detected by the reference diode 762. The power output supply device 700 then rapidly decreases +V gate until the peak positive voltage of V gate reaches +6V as desired in this example. The peak positive voltage of V gate is then kept at +6V by the circuit, even if there are fluctuations in the power supply or gate driver circuit 306 output. Both of Figures 12a and 12b demonstrate the advantage over the output of the prior art systems of Figures 2a to 3.

A similar effect as described in the second exemplary embodiment causes the slight deviations of the peak positive voltage of V gate in Figures 12a and 12b.

This invention could be applied to any power switch gate drive application, including but not limited to those in motor drives, inverters, uninterruptible power sources (UPS), solar power, electric vehicles and so on.

Although in this embodiment the positive gate voltage +V gate is regulated, to hold the peak positive voltage of the gate driver circuit output V gate at the required value, the power rails could be reversed so that accurate control of the peak negative voltage of V gate was performed, if accurate control of the peak negative voltage of V gate was desired. Fifth Exemplary Embodiment

Figure 13 shows an example of a configuration of a gate drive system 800 of the fifth exemplary embodiment. The fifth exemplary embodiment is the same as the third exemplary embodiment except that there is not a separate voltage clamping element such as the voltage clamping element 604 of the third exemplary embodiment, but instead the voltage clamping element is incorporated into the adjusting circuit 806.

As with the third exemplary embodiment, the power supply output device 800 starts, before V gate is input into the DGS line 312, with the positive gate voltage +V gate above the specifications for the power switch 308. When the gate signal, V gate, produced by the gate driver 306 is input to the DGS line 814, the adjusting circuit 806 transitions from clamping the voltage +V gate at the initial predetermined value, to adjusting and re-clamping the voltage division such that an accurate positive peak voltage is seen at the power switch 308.

Sixth Exemplary Embodiment

A power supply output device of the sixth exemplary embodiment is shown in Figure 14. The power output supply of the sixth exemplary embodiment is a specific example of a power output supply such as in the fifth exemplary embodiment. The power supply output device 900 of Figure 14 includes a voltage dividing element 902 and an adjusting circuit 906, connected as in the fifth exemplary embodiment. In the sixth exemplary embodiment the voltage clamping element 904 is incorporated into the adjusting circuit 906.

The voltage dividing element 902 includes a first capacitor 950 and a second capacitor 952 connected in series between the upper supply rail 908 and the lower supply rail 910. The output return line 912 is connected to the voltage dividing element 902 between the first capacitor 950 and the second capacitors 952.

The adjusting circuit 906 includes the voltage clamping element 904 in the sixth exemplary embodiment. The voltage clamping element 904 is a reference diode 962 with the cathode connected to the upper supply rail 908 and the anode connected to the output return line 912. A first resistor 964 is connected between the output return line 912 and the lower supply rail 910. A third capacitor 966 is connected between the cathode terminal and the reference terminal of the reference diode 962. The adjusting circuit 906 includes a peak detection element 968 which is connected to the DGS line 914. The peak detection element 968 may be a peak rectifier, for example a diode, a P channel MOSFET, a Schottky diode, or the like. A second resistor 976 is connected between the output of the peak detection element 968 and the upper supply rail 908. A fourth capacitor 970 is connected between the output of the peak detection element 968 and the output return line 912. A third resistor 972 and a fourth resistor 974 in series are also connected between the output of the peak detection element 968 and the output return line 912, in parallel with the fourth capacitor 970. The reference terminal of the reference diode 962 is connected to a point in-between the third resistor 972 and the fourth resistor 974.

Similar alternatives described in the second exemplary embodiment are also possible in the sixth exemplary embodiment.

The power supply output device 900 of Figure 14 can be used as the output unit 304 in a system configured as in Figure 5, in a the same way as the power supply devices of the previous exemplary embodiments.

At switch on the voltage supplied by the DC-DC convertor 302 appears across the voltage dividing element, +V supply with respect to -V supply in Figure 14. The voltage dividing element 902 then divides the voltage between the first capacitor 950 and the second capacitor 952. The first capacitor 950 and second capacitor 952 have equal capacitance so that the voltage is initially split equally between them. For example, if a 9V supply is used, the voltage drop across each of the capacitors would be 4.5V.

Because the second capacitor 952 has the first resistor 964 in parallel with it, the second capacitor 952 starts to discharge through the first resistor 964 and therefore the voltage across the first capacitor 950 starts to increase. The first capacitor 950 could also discharge through the second, third and fourth resistors 976,972,974. However, the resistance of the first resistor 964 is chosen to be much lower than the total resistance of the second, third and fourth resistors 976,972,974, so that the second capacitor 952 discharges more rapidly than the first capacitor 950, causing the first capacitor 950 to charge up.

With no signal input into the DGS line 914 the reference diode 962 is controlled by the potential divider of the second, third and fourth resistors 976,972,974. In the sixth exemplary embodiment, the resistances of the second, third and fourth resistors

976,972,974 are chosen so that the potential divider sets the reference diode 962 to start to regulate +V gate at a voltage above the peak positive voltage required for the power switch 308, for example +6.6V if the switch specification is +6V. When the voltage across the first capacitor 950 reaches +6.6V, the reference diode 962 starts to conduct. At this point the positive and negative gate voltages reach a balance where, in this case, +V gate is +6.6V with respect to the output return line 912, and -V gate is -2.4V with respect to the output return line 912. The reference diode 962 is therefore initially acting as the voltage clamping element 904 before any pulses appear at the DGS input. The reference diode 962 clamps the positive gate voltage +V gate in a similar fashion to the voltage clamping elements of the first, second, third and fourth exemplary embodiments. Next, a signal V gate produced by the gate driver circuit 306 is input to the DGS line 914 via the DGS line 312. The pulse waveform of V gate is input into the peak detection element 968. As an example, the peak detection element 968 in the sixth exemplary embodiment is a diode which peak rectifies the signal V gate. This charges the fourth capacitor 970 to the peak positive voltage of V gate minus the voltage drop over the diode. For example, in this case the peak positive voltage of V gate is +6.6V minus the losses in the gate driver circuit, and the voltage drop over the diode of the peak detection element 968 is 0.6V, therefore the fourth capacitor charges to +6V minus the losses in the gate driver circuit 306. The voltage across the fourth capacitor 970 is sensed by the adjustable reference diode 962 through the two lower potential divider resistors, the third and fourth resistors 972,974. The resistances of the third and fourth resistor are chosen so that when the voltage across the third and fourth resistors 972,974 is above the required positive peak voltage of V gate, minus the voltage drop over the peak detection element 968, the reference diode 962 shunts current. This causes the first capacitor 950 to discharge through the reference diode 962. The reference diode 962 therefore has a dual purpose, initially acting as the voltage clamping element 904, and then adjusting and re-clamping +V gate once a DGS line signal is input.

The decreasing voltage over the first capacitor 950 causes +V gate to decrease, and therefore causes the peak positive voltage of V gate to decrease, and thus the voltage over the third and fourth resistors 972,974 to decrease. When the voltage across the third and fourth resistors 972,974 reaches the required positive peak voltage of V gate minus the voltage drop over the peak detection element 968, the reference diode 962 clamps the voltage across the first capacitor 950. At this point the circuit is balanced with the voltage across the first capacitor 950 held at the required positive peak voltage of V gate plus the voltage to compensate for the losses in the gate driver circuit 306.

The third and fourth resistors 972,974 are selected to allow the reference diode 962 to shunt current when the voltage input into the DGS line is above the required voltage for the power switch 308, for example +6V. In this example, +6V is required as the peak positive voltage of the gate driver circuit 305 output, but in fact +6.2V is seen via the DGS line 914 at the gate of the power switch 308 from the initial +6.6V of +V gate. Therefore when V gate is input into the DGS line, the fourth capacitor charges to +6.2V-0.6V=5.6V and the voltage across the third and fourth resistors 972,974 is above +5.4V. The reference diode 962 therefore shunts current until voltage over the third and fourth resistors 972,974 reaches +5.4V. Now the reference diode 962 regulates the positive voltage +V gate such that the peak positive voltage of V gate is always +6V, by sensing the gate of the power switch 308 directly. The voltage values used here are for exemplary reasons only and are not limiting. Various alternatives are possible. The third capacitor 966 provides negative feedback, to prevent any input noise at the reference terminal of the reference diode 962 causing rapid fluctuations in the output at the cathode of the reference diode 962.

The advantages of the sixth exemplary embodiment are similar to those of the previous exemplary embodiments. The resulting gate voltage waveform V gate from the gate driving circuit 306 using the power supply output device 900 of the sixth exemplary embodiment is shown in Figures 15a and 15b. To produce these outputs a 9V supply from the DC-DC convertor was used, and the components used were first and second capacitors 950,952 with a 4.7uF capacitance for each capacitor, a TL431 reference diode 962, a 1 kQ first resistor 964, a 1nF third capacitor 966, a 12kQ second resistor 976, 29kQ third resistor 972, a 25kQ fourth resistor 974, a 10nF fourth capacitor 970, and a BAS70-06 diode as the peak detection element 968. Specific components and values given here are for exemplary purposes only. Various alternatives could be used, as would be understood by those skilled in the art.

Figure 15a shows the operation of the system when there is a voltage drop of 1V in the gate driver circuit 306. The voltage clamping element 904 holds +V gate at +6.6V initially. At 2ms the DGS line 914 is connected to gate of the power switch 308. The peak positive voltage seen at the gate of the power switch 308 is +6V and is therefore already on specification for the power switch 308. The peak positive voltage of V gate is then kept at +6V by the circuit, even if there are fluctuations in the power supply or gate driver circuit 306 output.

Accurate control of the peak positive voltage of V gate in this way means that the peak negative voltage of V gate is about -2.4V in the example in Figure 15a. However, the peak negative voltage does not have to be as accurate as the peak positive voltage in power switch applications.

Figure 15b is a similar graph to Figure 15a except that Figure 15b is the case where there is no voltage loss in the gate driver circuit 306. The voltage clamping element 904 holds +V gate at +6.6V initially. When the DGS line 914 is connected to the gate of the power switch 308, a peak positive voltage of V gate equal to +6.6V is detected by the reference diode 762. The power output supply device 700 then rapidly decreases +V gate until the peak positive voltage of V gate reaches +6V as desired in this example. The peak positive voltage of V gate is then kept at +6V by the circuit, even if there are fluctuations in the power supply or gate driver circuit 306 output. Both of Figures 15a and 15b demonstrate the advantage over the output of the prior art systems of Figures 2a to 3.

A similar effect as described in the second exemplary embodiment causes the slight deviations of the peak positive voltage of V gate in Figures 15a and 15b. This invention could be applied to any power switch gate drive application, including but not limited to those in motor drives, inverters, uninterruptible power sources (UPS), solar power, electric vehicles and so on.

Although in this embodiment the positive gate voltage +V gate is regulated, to hold the peak positive voltage of the gate driver circuit output V gate at the required value, the power rails could be reversed so that accurate control of the peak negative voltage of V gate was performed, if accurate control of the peak negative voltage of V gate was desired.

Seventh Exemplary Embodiment

Figure 16 shows a seventh exemplary embodiment of the power supply output device. The power supply output device 1000 of the seventh exemplary embodiment differs from the power supply output device 500 of the second exemplary embodiment through the removal of the reference diode 562, third capacitor 566, third resistor 572 and a fourth resistor 574 of the second exemplary embodiment. These components have been replaced in the seventh exemplary embodiment with a third switching element 1080, a Zener diode 1082 and a third resistor 1084.

The seventh exemplary embodiment includes a first capacitor 1050, a second capacitor 1052, one or more Zener diodes 1054, a first switching element 1056, a second switching element 1060, a first resistor 1058, a third switching element 1080, a second resistor 1064, a third capacitor 1070, a third resistor 1084, a Zener diode 1082, and a peak detection element 1068.

The third switching element 1080 can be a transistor, for example, a bipolar transistor or a field effect transistor such as a MOSFET. In the seventh exemplary embodiment an N- type bipolar transistor has been used as an example.

The voltage clamping element 1004 and the voltage dividing element 1002 in the seventh exemplary embodiment are the same as in the second exemplary embodiment.

In the adjusting circuit 1006 the collector of the N-type transistor is connected to the upper supply rail 1008 and the emitter of the transistor is connected to the output return line 1012. The cathode of the Zener diode 1082 is connected to the output of the peak detection element 1068, and the anode of the Zener diode 1082 is connected to the output return line 1012 via the third resistor 1084. The base of the third switching element 1080 is connected to a point between the Zener diode 1082 and the third resistor 1084.

The power supply output device 1000 of the seventh exemplary embodiment operates in the same way as the power supply output device 500 of the second exemplary embodiment up until the point when the voltage clamping element 1004 is switched off. At this point, when a signal is input into the DGS line 1014, the third capacitor 1070 is charged to the peak positive voltage of V gate minus the voltage drop over the peak detection element 1068. Initially, the Zener diode 1082 remains below its breakdown voltage.

Therefore no current flows through the Zener diode 1082 initially. This means that the third switching element 1080 remains turned off, as no current flows into the base terminal of the third switching element 1080.

The voltage across the first capacitor 1050, and therefore the positive gate voltage +V gate, is no longer clamped to the Zener breakdown voltage of the one or more Zener diodes 1054, as the input into the DGS line 1014 switches the voltage clamping element 1004 off. The second capacitor 1052 will then shunt current through the second resistor 1064, causing the voltage over the first capacitor 1050 to increase. The increasing voltage over the first capacitor 1050 causes +V gate to increase, and therefore causes the peak positive voltage of V gate to increase, and thus the voltage over Zener diode 1082 and the third resistor 1084 to increase. When the voltage across Zener diode 1082 is at its Zener breakdown voltage, the Zener diode 1082 starts to allow current to flow. This switches on the third switching element 1080, through which the first capacitor 1050 can discharge. At this point the circuit is balanced with the voltage across the first capacitor 1050 held at the required positive peak voltage of V gate plus the voltage to compensate for the losses in the gate driver circuit 306.

In the seventh exemplary embodiment, the third switching element 1080 shunts current from the first capacitor 1050 and the Zener diode 1082 acts as a voltage detection device, measuring the voltage input into the DGS line 1014 with respect to the output return line 1012. In this exemplary embodiment, the Zener diode 1082 passes as little current as possible.

An example of the components used for the seventh exemplary embodiment to maintain a positive gate voltage +V gate of +6V from a 9V supply from a DC-DC convertor are first and second capacitors 1050,1052 with a 4.7uF capacitance, two BZX84-3V0 Zener diodes as the one or more Zener diodes 1054, two 2N7000 N channel MOSFETs as the first and second switching elements 1056,1060, a 10kQ first resistor 1058, a Q2N2222 N-type bipolar transistor as the third switching element 1080, a 1 kQ second resistor 1064, a 10nF third capacitor 1070, a 1 kQ third resistor 1084, a BZX84C5V1 Zener diode 1082, and a BAS70-06 diode as the peak detection element 1068. Specific components and values given here are for exemplary purposes only. Various alternatives could be used, as would be understood by those skilled in the art.

The Zener diode used in this example has a Zener breakdown voltage of 5.1V. When the Zener diode reaches this voltage, it allows a small amount of current to flow, typically 1 to 5mA. In this example, the third resistor 1084 is chosen to have a voltage drop of about 0.6V at this current, and therefore the base emitter voltage of the third switching element 1080 is 0.6V, which is enough voltage to switch on the third switching element. The total voltage over Zener diode 1082 and third resistor 1084 at this point is 5.1V+0.6V=5.7V.

Therefore it appears that before the 0.6V drop over the peak detection element 1068, V gate must be +6.3V when the third switching element 1080 is switched on and the voltage is clamped. However as discussed in the second exemplary embodiment, the third capacitor 1070 is charged on average to slightly below the peak positive voltage of V gate minus the voltage drop over the peak detection element. Furthermore, the Zener diode 1082 may first start conducting at a lower current than 1mA, meaning the voltage over the Zener diode 1082 at which the third switching element 1080 is switched on will therefore be slightly lower than 5.1V specified on the data sheet for the Zener diode. The combination of these two effects results in the selected components clamping the peak positive voltage of V gate not at +6.3V, but at the +6V as required. Similar allowances can be made when different components, other than the ones listed above, are used.

The advantages of the seventh exemplary embodiment are the same as the second exemplary embodiment.

Eighth Exemplary Embodiment

Figure 17 shows a eighth exemplary embodiment of the power supply output device. The power supply output device 1100 of the eighth exemplary embodiment differs from the fourth exemplary embodiment by the same alterations as made in the seventh exemplary embodiment.

The eighth exemplary embodiment includes a first capacitor 1150, a second capacitor 1152, one or more Zener diodes 1154, a first switching element 1180, a first resistor 1164, a third capacitor 1170, a second resistor 1184, a Zener diode 1182, and a peak detection element 1168.

The power supply output device 1100 of the eighth exemplary embodiment operates in the same way as the power supply output device 700 of the fourth exemplary embodiment up until the point when the signal V gate produced by the gate driver circuit 306 is input to the DGS line 1114. At this point the third capacitor 1170 is charged to the peak positive voltage of V gate minus the voltage drop over the peak detection element 1168. The Zener diode 1182 is above its breakdown voltage due to the initial voltage of +V gate being set by the voltage clamping element 1154 above the switch specification, for example +6.6V, and therefore the peak positive voltage of V gate being above the required voltage. Current therefore flows through the Zener diode 1182 which turns on the first switching element 1180.

The first switching element 1180 therefore shunts current allowing the first capacitor 1150 to discharge. The decreasing voltage over the first capacitor 1150 causes +V gate to decrease, and therefore causes the peak positive voltage of V gate to decrease. The Zener diodes 1154 of the voltage clamping element 1104 are now below their breakdown voltage, so current no longer flows through the voltage clamping element 1104. As the peak positive voltage of V gate to decreases the voltage over the Zener diode 1182 drops below its breakdown voltage, and the Zener diode 1182 therefore stops allowing current to flow, which switches the first switching element 1180 off. At this point the circuit is balanced with the voltage across the first capacitor 1150 held at the required positive peak voltage of V gate plus the voltage to compensate for the losses in the gate driver circuit 306.

In the eighth exemplary embodiment, the first switching element 1180 shunts current from the first capacitor 1150 and the Zener diode 1182 acts as a voltage detection device, measuring the voltage input into the DGS line 1114 with respect to the output return line 1112. In this exemplary embodiment, the Zener diode 1182 passes as little current as possible.

An example of the components used for the eighth exemplary embodiment to maintain a positive gate voltage +V gate of +6V from a 9V supply from a DC-DC convertor are first and second capacitors 1150,1152 with a 4.7uF capacitance, two BZX84-3V3 Zener diodes as the one or more Zener diodes 1154, a Q2N2222 N-type bipolar transistor as the first switching element 1180, a 1 kQ first resistor 1164, a 10nF third capacitor 1170, a 1 kQ second resistor 1184, a BZX84C5V1 Zener diode 1182, and a BAS70-06 diode as the peak detection element 1168. Specific components and values given here are for exemplary purposes only. Various alternatives could be used, as would be understood by those skilled in the art.

Similar comments as discussed in the seventh exemplary embodiment relating to the clamping the peak positive voltage of V gate at +6V not +6.3V hold analogously for this example of the eighth exemplary embodiment. Similar allowances can be made when different components, other than the ones listed above, are used.

The advantages of the eighth exemplary embodiment are the same as the fourth exemplary embodiment. Figure 18 shows a ninth exemplary embodiment of the power supply output device. The power supply output device 1200 of the ninth exemplary embodiment differs from the sixth exemplary embodiment by the same alterations as made in the seventh and eighth exemplary embodiments.

The ninth exemplary embodiment includes a first capacitor 1250, a second capacitor 1252, a first switching element 1280, a first resistor 1264, a third capacitor 1270, a second resistor 1284, a Zener diode 1282, a third resistor 1276, and a peak detection element 1268.

In the power supply output device 1200 of the ninth exemplary embodiment, the Zener diode 1282, in combination with the second resistor 1284 and the third resistor 1276, acts as the voltage clamping element initially. The second capacitor 1252 discharges through the first resistor 1264, charging the first capacitor 1250 and increasing +V gate until the voltage clamping element 1204 allows current to flow. Current flowing through the Zener diode 1282 switches on the first switching element 1280, which prevents the first capacitor from charging further. The voltage over the first capacitor 1250, +V gate, is therefore clamped at the voltage at which the voltage clamping element 1204 allows current to flow. In the ninth exemplary embodiment +V gate is clamped above the specification for the power switch 308 initially, for example at +6.4V.

When the signal V gate produced by the gate driver circuit 306 is input to the DGS line 1214, the third capacitor 1270 is charged to the peak positive voltage of V gate minus the voltage drop over the peak detection element 1268. The Zener diode 1282 is above its breakdown voltage due to the initial voltage of +V gate being set above the switch specification, for example +6.4V, and therefore the peak positive voltage of V gate being above the required voltage. Current therefore flows through the Zener diode 1282 which turns on the first switching element 1280.

The first switching element 1280 therefore shunts current allowing the first capacitor 1250 to discharge. The decreasing voltage over the first capacitor 1250 causes +V gate to decrease, and therefore causes the peak positive voltage of V gate to decrease. This causes the voltage across the Zener diode 1282 to drop below its breakdown voltage, and therefore the Zener diode 1282 stops allowing current to flow, which switches the first switching element 1280 off. At this point the circuit is balanced with the voltage across the first capacitor 1250 held at the required positive peak voltage of V gate plus the voltage to compensate for the losses in the gate driver circuit 306.

In the ninth exemplary embodiment, the first switching element 1280 shunts current from the first capacitor 1250. The Zener diode 1282 acts as a voltage detection device, measuring the voltage +V gate through the third resistor 1276 initially, and then measuring the voltage input into the DGS line 1214 with respect to the output return line 1212. In this exemplary embodiment, the Zener diode 1282 passes as little current as possible.

An example of the components used for the ninth exemplary embodiment to maintain a positive gate voltage +V gate of +6V from a 9V supply from a DC-DC convertor are first and second capacitors 1250,1252 with a 4.7uF capacitance, a Q2N2222 N-type bipolar transistor as the first switching element 1280, a 1kQ first resistor 1264, a 10nF third capacitor 1270, a 1 kQ second resistor 1284, a BZX84C5V1 Zener diode 1282, a 1.5kQ third resistor 1276, and a BAS70-06 diode as the peak detection element 1268. Specific components and values given here are for exemplary purposes only. Various alternatives could be used, as would be understood by those skilled in the art.

Similar comments as discussed in the seventh exemplary embodiment relating to the clamping the peak positive voltage of V gate at +6V not +6.3V hold analogously for this example of the ninth exemplary embodiment. Similar allowances can be made when different components, other than the ones listed above, are used.

The advantages of the ninth exemplary embodiment are the same as the sixth exemplary embodiment.

Tenth Exemplary Embodiment

Figure 19 shows a tenth exemplary embodiment of the power supply output device. The power supply output device 1300 of the tenth exemplary embodiment differs from the power supply output device 500 of the second exemplary embodiment through the removal of the reference diode 562 and third capacitor 566 of the second exemplary embodiment. These components have been replaced in the tenth exemplary embodiment with an operational amplifier (op amp) 1390, a Zener diode 1388 and a fifth resistor 1386.

The tenth exemplary embodiment includes a first capacitor 1350, a second capacitor 1352, one or more Zener diodes 1354, a first switching element 1356, a second switching element 1360, a first resistor 1358, an op amp 1390, a second resistor 1364, a third capacitor 1370, a third resistor 1372, a fourth resistor 1374, a fifth resistor 1386, a Zener diode 1388, and a peak detection element 1368.

The voltage clamping element 1304 and the voltage dividing element 1302 in the tenth exemplary embodiment are the same as in the second exemplary embodiment.

In the adjusting circuit 1306 the positive power supply terminal of the op amp 1390 is connected to the upper supply rail 1308, and the negative power supply terminal of the op amp 1390 is connected to the output return line 1312. The output of the op amp 1390 is connected to the positive power supply rail of the op amp 1390. The fifth resistor 1386 is connected between the upper supply rail 1308 and the cathode of the Zener diode 1388.

The anode of the Zener diode 1388 is connected to the output return line 1312. The non inverting input of the op amp 1390 is connected to a point between the fifth resistor 1386 and the Zener diode 1388. The inverting input of the op amp 1390 is connected to the midpoint of the potential divider formed by the third resistor 1372 and the fourth resistor 1374.

The power supply output device 1300 of the tenth exemplary embodiment operates in the same way as the power supply output device 500 of the second exemplary

embodiment up until the point when the voltage clamping element 1304 is switched off. Namely, the second capacitor 1352 discharges through the second resistor 1364, causing the first capacitor 1350 to charge up until +V gate is clamped on specification for the power switch 308 being driven, in this case +6V, by the voltage clamping element 1304. The current through the fifth resistor 1386 and Zener diode 1388 is very low compared to the current through the second resistor 1364. This means that the second capacitor 1352 discharges more rapidly than the first capacitor 1350, causing the first capacitor 1350 to charge up.

When a signal is input into the DGS line 1314, the voltage clamping element 1304 is switched off, and the third capacitor 1370 is charged to the peak positive voltage of V gate minus the voltage drop over the peak detection element 1368. The Zener diode 1388 regulates at its breakdown voltage, and therefore the non-inverting input of op amp 1390 is held at the breakdown voltage of the Zener diode 1388. The breakdown voltage of the Zener diode 1388 can be any value less than +V gate minus the loss over the peak detection element 1368. The third and fourth resistors 1372, 1374 are then chosen so that the midpoint of the potential divider formed will be equal to the Zener diode breakdown voltage when the peak positive voltage of the signal V gate input into the DGS line 1314 is at the required voltage for driving the gate of the power switch 308. For example, if the peak positive voltage of V gate is on specification for the power switch 308, for example at +6V, and the loss over the peak detection element 1368 is 0.6V, the third capacitor 1370 will charge to +5.4V, and the voltage over the potential divider of the third and fourth resistors 1372,1374 will be +5.4V. If the Zener diode 1388 is chosen with a breakdown voltage of +2.7V, then third and fourth resistors 1372,1374 with equal resistances are chosen, so that the midpoint will also be at +2.7V when the peak positive voltage of V gate is +6V.

The midpoint of the potential divider is connected to the inverting input of the op amp 1390. The op amp 1390 acts as a voltage comparator. When the voltage at the inverting input is higher than the voltage at the non-inverting input, the peak positive voltage of V gate is higher than the voltage required for the power switch 308. In this case the output of the op amp 1390 is driven towards its negative power supply terminal voltage, the voltage of the output return line 1312. Because the output is connected to the positive power supply terminal of the op amp 1390 the op amp shunts current through to the negative power supply terminal. Therefore the first capacitor 1350 discharges, causing +V gate to decrease.

On the other hand, when the voltage at the inverting input is lower than the voltage at the non-inverting input, the peak positive voltage of V gate is lower than the voltage required for the power switch 308. In this case the output of the op amp 1390 is driven towards the positive power supply voltage, the voltage of the upper supply rail 1308. As the output is already connected to the positive power supply terminal of the op amp 1390, no current is shunted by the op amp 1390. Therefore the first capacitor 1350 charges up as the second capacitor discharges through the second resistor 1364, causing +V gate to increase.

When the inverting and non-inverting terminals reach an equal voltage the circuit is balanced, with +V gate clamped at the voltage required for the power switch 308, for example +6V, minus any losses in the gate driver circuit 306.

An example of the components used for the tenth exemplary embodiment to maintain a positive gate voltage +V gate of +6V from a 9V supply from a DC-DC convertor are first and second capacitors 1350,1352 with a 4.7uF capacitance, two BZX84-3V0 Zener diodes as the one or more Zener diodes 1354, two 2N7000 N channel MOSFETs as the first and second switching elements 1356,1360, a 10kQ first resistor 1358, a TLC2272 as the op amp 1390, a 1 kQ second resistor 1364, a 10nF third capacitor 1370, a 54kQ third resistor 1372, a 27kQ fourth resistor 1374, a BZX84-2V7 Zener diode 1388, a 3.3kQ fifth resistor 1386 and a BAS70-06 diode as the peak detection element 1068. Specific components and values given here are for exemplary purposes only. Various alternatives could be used, as would be understood by those skilled in the art. For example, in an alternative embodiment the Zener diode 1388 could be replaced with a reference diode.

The advantages of the tenth exemplary embodiment are the same as the advantages of the previous exemplary embodiments.

In the tenth exemplary embodiment, the alterations, namely the use of the op amp 1388, the fifth resistor 1386 and the Zener diode 1388, have been made to the second exemplary embodiment as an example. The alterations made in the tenth exemplary embodiment could also be made to the fourth and sixth exemplary embodiments. The alterations would be made in exactly the same way, by replacing the reference diode 762 or 962 and the third capacitor 766 or 966 with an op amp, resistor and Zener diode, connected as in the tenth embodiment.

The embodiments described above are not limited to power supplies for IGBT, SIC, MOS, and GaN power switches and may readily be used in other power switching technologies. Examples physical values, including voltages, resistances, capacitances, breakdown voltages and the like, as well as examples of specific model numbers of components given throughout the embodiments are for exemplary purposes only. Various alternatives could be used, as would be understood by those skilled in the art.

Although described separately, the features of the embodiments outlined above may be combined in different ways where appropriate. Various modifications to the embodiments described above are possible and will occur to those skilled in the art without departing from the scope of the invention which is defined by the following claims.