Title:
PRESCALER FOR A FREQUENCY DIVIDER
Document Type and Number:
WIPO Patent Application WO/2023/014459
Kind Code:
A3
Abstract:
A hybrid true single-phase clock (H-TSPC) circuit includes a first logic circuit comprising non-ratio (NR) logic, a first mode switching device coupled to an output of the first logic circuit, a second logic circuit comprising ratio (R) logic, the second logic circuit configured to receive an output of the first logic circuit, a second mode switching device coupled to an output of the second logic circuit, a third logic circuit comprising non-ratio (NR) logic, the third logic circuit configured to receive an output of the second logic circuit, and a third mode switching device coupled to an output of the third logic circuit, wherein the first logic circuit, second logic circuit, and third logic circuit are configured in a ring.
More Like This:
| WO/2016/007552 | EDGE CORRECTION TO MITIGATE TOTAL HARMONIC DISTORTION IN CLASS D AMPLIFIER |
| JPS58150127 | [Title of the device] Timing electric supply structure |
| JP6387896 | Divider |
Inventors:
HAO, Shilei (US)
ZHU, Yunliang (US)
TANG, Yiwu (US)
PARK, Dongmin (US)
ZHU, Yunliang (US)
TANG, Yiwu (US)
PARK, Dongmin (US)
Application Number:
PCT/US2022/036192
Publication Date:
March 16, 2023
Filing Date:
July 06, 2022
Export Citation:
Assignee:
QUALCOMM INCORPORATED (US)
International Classes:
H03K21/10; H03K23/40; H03K23/44; H03L7/193
Attorney, Agent or Firm:
TEMPEL, Michael J. et al. (US)
Download PDF:
Previous Patent: ANISOTROPIC SIGE:B EPITAXIAL FILM GROWTH FOR GATE ALL AROUND TRANSISTOR
Next Patent: AGING MITIGATION
Next Patent: AGING MITIGATION