CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority of U.S. Patent Application No. 13/409,828, filed on March 1, 2012, and entitled Programmable Slew Rate Power Switch (Attorney Docket No. SNDKP632/MSA-1408-US), the entire disclosure of which is incorporated herein by reference in its entirety for all purposes.

BACKGROUND OF THE INVENTION

[0002] This invention relates generally to electrical circuits, and more particularly to apparatus and methods for providing an increasing power supply voltage.

[0003] Several different types of electronic devices can utilize an increasing voltage supply. One such example is a one-time programmable electric fuse, which is a type of non-volatile memory. An electric fuse can be used to provide memory for chip ID, configuration settings, feature selection, etc.

[0004] One type of voltage supply switch for providing an increasing voltage supply is based on a digital approach. Figure 1 is a diagrammatic representation of a digital voltage supply switch 150. In general, a circuit that implements this approach includes an oscillator (CLK), counter 122, decoder 124, and resistive network 1 12 for normal operation.

[0005] According to a required ramp-up slew rate, a time period is determined by a counter 122 and a decoder 124. In every such period, the proper switch 112, e.g., selected from switches RNO-RNn, is closed and an appropriate gate voltage, e.g., VGO-VGn, is imposed on a corresponding power transistor. Module 106 contains a system of power transistors PO-Pn. In summary, each of the power transistors corresponds to a different switch (RNO-RNn) path. An output voltage VDD OUT is then supplied to load 104.

[0006] The output voltage VDD OUT profile for this circuit has a staircase shape as illustrated in the graph 200 of Figure 2. The lowest voltage stair is obtained when all the power transistors are switched off. Every pulse that is provided by the decoder (124) turns on a successive power transistor, which each yield a new voltage stair, e.g., BUFO-BUFn. Eventually, the voltage output staircase wave, VDD_OUT, reaches its target peak voltage, VDD IN-IR drop. Although this digital approach achieves a particular voltage output slew rate, such implementation is very sensitive to the process parameters, temperature, output load 104 and resistive network 112, as well as requiring a clock (CLK). [0007] Improved voltage switch devices for providing an increasing output voltage rise with a programmable slew rate would be beneficial.

SUMMARY OF THE INVENTION

[0008] In general, apparatus and techniques for supplying an accurate ramping up of power supply voltage with programmed slew rates are provided. In one embodiment, an apparatus is configured to provide a voltage output with a programmable slew rate. The apparatus comprises a Ramp-Up Control circuit module for supplying an increasing output voltage that is output to a load circuit. The Ramp-Up Control circuit comprises an amplifier that receives the output of a plurality of selectable mirrored current sources for programming a selected linear slew rate for the increasing output voltage. The apparatus further comprises a glitch filter circuit for stabilizing the increasing output voltage so as to minimize glitches, including current and voltage stress, in the output voltage.

[0009] In a specific implementation, the amplifier has a low threshold voltage and is a three port device having a first port coupled to a supply voltage, a second port for receiving a voltage and a third port for substantially copying the voltage from the second port, and the ramp-up control circuit further comprises a capacitor Cc that is coupled to the first port, wherein selection of one or more of the selectable mirrored current mirrors and a capacitance value for the capacitor Cc results in the selected linear slew rate. In a further aspect, the amplifier is a CD (common drain) voltage follower transistor in the form of an n-channel metal oxide semiconductor field effect transistor (NMOSFET) or a CC (common collector) transistor in the form of a BJT (bipolar junction transistor), and the capacitor Cc and the one or more of the selectable current sources are coupled with the NMOSFET's gate or the BJT's base to cause an increasing input voltage having the selected linear slew rate, which increases from zero to a maximum voltage corresponding to the supply voltage. [0010] In another embodiment, the selected linear slew rate is equal to a sum of one or more current values from the one or more selected mirrored current sources divided by the capacitance value of the capacitor Cc, and any of the above described devices can be used with this slew selection technique. In yet another feature, the apparatus further comprises a voltage sensor circuit for sensing that the output voltage has reached a predefined threshold value, enabling and disabling of the glitch filter circuit, and finalizing ramp up of such output voltage according to the selected linear slew rate. In a further aspect, the apparatus further comprises a power switch transistor that is arranged to be turned on by the voltage sensor circuit and provide an additional load current as the output voltage approaches a predefined threshold value. This voltage sensor may be implemented with any combination of the above specified voltage followers, three-port devices, power switch transistor, and linear slew rate selection features. The power switch transistor may be implemented with any combination of the above specified voltage followers, three-port devices, voltage sensor, and linear slew rate selection features.

[0011] In yet a further embodiment, the voltage sensor further comprises a first transistor for receiving the output voltage and turning off when the output voltage reaches the maximum value (e.g., when the output voltage reaches some upper-threshold value set by the size of this transistor and the current force by the mirror at the drain of this transistor, such as 75% of the final nominal voltage value, and after the signal propagates to the power transistor and slowing draws it from cut-off region); a Schmitt trigger for receiving a decreasing input voltage as the first transistor turns off and outputting an inversion of the input voltage when it reaches the Schmitt trigger's lower threshold; a second transistor for receiving the inversion of the input voltage and, in response, turning off. The power transistor has an input coupled to an output of the second transistor to receive the inversion, a sensor network of mirrored current sources and a capacitor Cys that charges and decreases a sensor voltage in correlation with a current of the sensor network to thereby turn on the power transistor at the selected slew rate, ramping up to the additional load current (e.g., so that now the voltage ramp up is finalized by this power transistor and an output voltage at its maximum value that is equal to VIN minus the IR drop of all the power switch is achieved). This specific voltage sensor embodiment may be implemented with any combination of the above specified voltage followers, three-port devices, power switch transistor, voltage sensor features, and linear slew rate selection features. In another aspect, the glitch filter circuit comprises a first transistor coupled to an RC circuit that is coupled to the increasing output voltage and is configured to filter high frequencies, which are > and a second transistor for receiving the

27TR discharge ^ B

sensed voltage caused by high frequencies that are being filtered and for conducting all other frequencies until the "glitch" is over. The glitch filter can remain active until the sensor voltage causes the power transistor M _P to turn on and the output voltage has ramped up to its maximum level. The glitch filter can be operable to prevent undesirable phenomenon that affects the proper linear rise of the output voltage from the ramp-up control switch. This specific glitch filter embodiment may be implemented with any combination of the above specified voltage followers, three-port devices, and power switch transistor, voltage sensor features, and linear slew rate selection features. [0012] In an alternative embodiment, the ramp-up control circuit may further comprise a decoupling capacitor Cdecoupie coupled to the amplifier for reducing any high frequency rises in the increasing output voltage. In another embodiment, the apparatus further includes a pull down network for discharging the output voltage after the ramp-control circuit is disabled and a break-before-make circuit for enabling the ramp-up control circuit while disabling the pull-down circuit and for disabling the ramp-up control circuit while then enabling the pull down network to discharge the output voltage. This decoupling capacitor, and/or pull down network and break-before-make circuit embodiments may be implemented with any combination of the above specified voltage followers, three-port devices, and power switch transistor, voltage sensor features, and linear slew rate selection features. [0013] In another embodiment, an apparatus comprises a voltage follower device receiving an increasing gate voltage from a plurality of selectable mirrored current sources and a capacitor so as that the increasing gate voltage has a linear slew rate that is defined by a current value sum for the selectable mirrored current sources divided by a capacitance value of the capacitor, wherein the voltage follower transistor is configured to output an increasing output voltage that follows the increasing gate voltage. This apparatus also comprises a Glitch Filter circuit coupled to the increasing output voltage to filter sharp rises in the increasing output voltage caused by parasitic capacitance between terminals of the voltage follower transistor or instantaneous current demands of the load. The apparatus also includes a Voltage Sensor circuit for outputting a slowly decreasing Voltage Sensor output and a power transistor for receiving the slowly decreasing Voltage Sensor and slowly turning on so as to finalize ramping up of the increasing voltage at the linear slew rate to provide a full drive current. This specific apparatus embodiment may be implemented with any combination of the above specified voltage followers, three-port devices, power switch transistor, voltage sensor, glitch filter, decoupling capacitor, pull-down network, break- before -make circuit features, and linear slew rate selection features. [0014] In other embodiments, the invention pertains to a method of operating any one or more of the above described apparatus component combinations. In one embodiment, a particular linear slew rate for supplying an increasing output voltage that is output from a ramp-up control circuit to a load circuit is determined. One or more of a plurality of selectable mirrored current sources of the ramp-up control circuit are selected so as to program the particular linear slew rate, which is based on the one or more selected mirrored current sources and a capacitance value of a capacitor Cc of the ramp-up control circuit.

[0015] In a specific implementation, the increasing output voltage is stabilized with a glitch filter circuit so as to minimize glitches in the increasing output voltage if caused by rapid switching of the one or more selected current sources. The particular linear slew rate is equal to a sum of one or more current values from the one or more selected mirrored current sources divided by the capacitance value of the capacitor Cc of the ramp-up control circuit. In a further aspect, a sensor circuit is used to sense that the output voltage has reached a predefined threshold value, and enabling the glitch filter circuit, and finalizing ramp up of such output voltage according to the particular linear slew rate [0016] These and other features of the present invention will be presented in more detail in the following specification of embodiments of the invention and the accompanying figures, which illustrate by way of example the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS [0017] Figure 1 is a diagrammatic representation of a digital voltage supply switch.

[0018] Figure 2 is a timing diagram for a digital voltage switch.

[0019] Figure 3 is a diagrammatic representation of a high-level system in which a programmable power switch of the present invention may be implemented. [0020] Figure 4 is a schematic diagram of a programmable power switch in accordance with a specific implementation of the present invention.

[0021] Figure 5 is a schematic diagram of a Glitch Filter circuit in accordance with one embodiment of the present invention. [0022] Figure 6 is a graph of the linear output voltage's ramping profile from a programmable power switch in accordance with one embodiment of the present invention.

[0023] Figure 7 is a schematic diagram of a decoupling capacitor C _decoup i _e attached to the drain of transistor MQ.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0024] Reference will now be made in detail to a specific embodiment of the invention. An example of this embodiment is illustrated in the accompanying drawings. While the invention will be described in conjunction with this specific embodiment, it will be understood that it is not intended to limit the invention to one embodiment. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.

[0025] The following embodiments are directed towards a power switch that is based on an analog approach. In general, a current reference, IREF, is selectively mirrored to the gate of one or more suitably sized transistors that form part of an I-C network that yields a linear output voltage as described further below. [0026] Before turning to the details of programmable power switch embodiments of the present invention, exemplary system architectures will first be described. Figure 3 is a diagrammatic representation of a high-level system 300 in which a programmable power switch of the present invention may be implemented. As shown, a bandgap current reference 306 can be used to provide one or more current sources, such as a current reference, IREF, to a programmable power switch 302. In general, a bandgap reference (voltage or current) may be used to provide a current reference to switch 302, and the switch can be configured to implement current mirrors that mirror any desired current, based on such reference current, for use inside the switch. Any suitable current source device may be utilized and ideally such device provides a consistent current source with a low sensitivity to power supply and temperature changes. Although a bandgap current reference is illustrated, one or more alternative devices (e.g., transistor current and LED current sources, transistor and diode current sources, op-amp current sources, voltage regulator current sources, etc.) may be used to provide one or more reference currents to the power switch 302.

[0027] The programmable power switch 302 can be arranged to receive one or more current sources, IREF, from bandgap current reference 306 and also receive input voltages Vcc and VIN from any suitable power source (not shown). The power switch is configured to supply a linearly increasing voltage VOUT to a load circuit 304. The load circuit can take the form of any electronic circuitry that is arranged to receive a voltage supply having a linear slew rate. By way of example, the load circuit 304 may be in the form of a one-time programmable electric fuse (eFuse) that forms part of a high density array of eFuses (e.g., 32-bit by 8 onetime programmable eFuses).

[0028] Figure 4 is a schematic diagram of a programmable power switch 400 in accordance with a specific implementation of the present invention. As shown, the programmable power switch 400 may include a Ramp-Up Control circuit 402 for controlling the slew rate of an output voltage VOUT supplied to load circuit 412, a Glitch Filter 410 for minimizing glitches in the output voltage VOUT, a Voltage Sensor 404 for sensing that the output voltage VOUT has reached a predefined threshold value (e.g., 75% of nominal final voltage) and finalizing the ramp up of such output voltage according to the programmed slew rate by turning on M _P transistor, and one or more enable and discharge circuits (e.g., break-before make circuit 406 and Pull Down Network 408).

[0029] In general, the Ramp-Up Control circuit 402 may include a plurality of selectable current mirrors, IREFI-IREF _II - Each of the current mirrors, IREFI-IREF _II , is connected to an input voltage VIN. One or more of the current mirror sources are selectable by closing one or more switches Si-S _n . When an enable signal (PUN_EN) is applied (logic 1) to switch Sci, a summation of the selected current sources begins to flow and the voltage on the gate of Mc increases.

[0030] In one embodiment, before applying the enable signal PUN EN to the Ramp-Up Control circuit 402, the Break-Before-Make circuit 406 can be configured to settle the signal PDN EN to a logical "low" value in order to disable Pull Down Network 408 and prevent short circuits. To turn off the switch, the Break-Before-Make circuit can be configured to first disable the PUN_EN (settling logic "low"). Only after PUN_EN is disabled, the Break- Before-Make circuit 406 may then enable PDN EN also to prevent a short circuit from VI to Vss- The role of Break-Before-Make is to close PDN_EN before enabling PUN_EN for enabling the process and to close PUN_EN before enabling PDN_EN for disabling the process. That is, there is a delay between the transitions of the PDN_EN and the PUN_EN signals.

[0031] Without the Break-Before-Make circuit 406, short circuit may take place between VIN and Vss- During operation, the Pull-Up-Network (PUN) is enabled (e.g., Ramp-Up-Control and the M _P transistor are enabled) while Pull-Down-Network (PDN) is disabled. Next the switch is turned off by turning off the Enable signal. If there is no Break-Before-Make circuit 406, the PDN is enabled now (to discharge the output) and the PUN is disabled (so as to not consume current from VIN). The process of changing between an enable and disable mode takes time. For example, after 10ns have passed, the signals may be in an intermediate halfway state between their initial value and their final value. As such, the PUN is not fully closed now and the PDN is not fully opened (they are "half-enabled"). In effect, the transistors of PUN and PDN operate and conduct current from the source VIN to the ground Vss- As a result, a short circuit current may occur from VIN to Vss for about a 10ns-20ns of duration of the signal, which would immediately burn the device. The description of turn-on case is similar. To protect the device, signals PUN_EN and PDN_EN are selected to be distant in time for the time it takes to signal to propagate and fully close the PUN (in case of disable) or PDN (in case of enable).

[0032] Mc may take the form of any suitable amplifier, such as the illustrated low threshold transistor or a low threshold operational amplifier or native transistor. In certain embodiments, Mc is a three-port device with a first port coupled to a power supply, a second port for receiving a voltage, and a third port for substantially copying ("following") the voltage from the second port (and enabling high current capability at the third port). Mc may be a common drain (CD), in case of MOSFET, or common collector (CC) voltage follower transistor, in case of Bipolar Junction Transistor (BJT). In certain embodiments, the transistor Mc has a threshold voltage V _t that is negative (depletion mode) or substantially close to 0 (native mode). The drain of the illustrated transistor Mc is also coupled to VIN when enabled by enable signal (e.g., PUN_EN on switch S _c2 ), and the source of Mc is coupled to the output voltage VOUT, which follows the increasing gate voltage Vc since the threshold voltage is kept low.

[0033] Although an n-channel MOSFET (metal oxide semiconductor field-effect transistor) depletion or native mode type transistor Mc is used in the illustrated example, one would appreciate that other types of transistors could be readily implemented. For example, any other type of insulated gate FET, besides a MOSFET, transistor can be used. By way of another example, a common collector npn type BJT voltage follower can be used for Mc. Additionally, the transistor may be enhancement mode, for which different relative Vc and VI may be chosen to account for a positive threshold voltage. A plurality of transistors may also be used in place of M _c , and such transistors can be controlled by a plurality of selectable current sources to thereby yield an output voltage VOUT that is an accumulation of the individual output voltages of the multiple transistors.

[0034] In the illustrated embodiment, the gate of Mc is also connected to a capacitor, Cc, which along with selection of the current mirrors (IREFI -IREF _I forms an I-C network that yields linear voltage growth at a particular slew rate on the gate of Mc via switches Si - S _n , as described further below. Since the voltage amplification of the common drain topology is substantially equal to 1 , the output voltage on the source (VOUT) follows the gate voltage Vc with a corresponding change of I _D s current according to the connected load. Thus, a particular slew rate of VOUT can be programmed by the selection of one or more current mirrors and a particular capacitance value of the capacitor Cc.

[0035] In one embodiment, the slew rate determination and programming is based on a very simple I-C analysis. Once IREF is instated, a slew rate (SR) can be determined by:

[0036] V _c = [0037] Time integration over both sides will yield:

[0039] One can assume Vco = 0 since during proper operation, either when enabled or disabled, this branch is fully charged or discharged. With Vco = 0, the following equation results:

[0041] Although, the capacitor Cc may be dependent on voltage applied across it, this effect is negligible. Since I _RE F and Cc can be considered independent of time, the following equation can be derived:

[0042] V _c (t = T) = - ¹ ^

[0043] While the upper boundary for Vc is VIN, the transistor inside the switch Sci of Ramp- Up Control 402 enters into the linear region, then VDS across it approaches "0", and therefore,

[0044] V _m - ^

[0045] Finally, the slew rate can be expressed as:

— ^ ^w — ^KEF — I KEFl

[0046] + · · · + 1 REFn

[0047] Since a high current is to be conducted through Mc in order to compensate current consumable by the load 412, Mc will tend to be large. When the switch is implemented on silicon, a 1mA current can be a really high current. A transistor that is capable of handling such a large current or higher, as well as compensating Glitch Filter demands and load demands with current will be large. Each MOSFET transistor has W (width) and L (length). When the ratio W/L » 1 , for example, this transistor may be considered to have a large size. However, the actual size of the transistor would be determined based on a simulation using the particular physics of the particular fabrication process. The transistor size would also depend on the noise on Vcc- If voltage Vcc is noisy, high harmonies may penetrate through a very small parasitic capacitor of the transistor and, thus, even the small transistor in terms of W/L ratio may be large enough. [0048] When Mc is designed to have a large size, there can cause coupling between the Mc terminals. That is, there is a parasitic capacitor between the source and drain of Mc. When the switch PUN_EN is closed, there is an instantaneous rise up or glitch in the voltage on output voltage VOU _T - TO alleviate this disturbance, VOU _T can be connected to a Glitch Filter circuit 410, which is configured to minimize disturbances. In general, the Glitch Filter circuit 410 minimizes disturbances from the output voltage VOU _T rising too fast or not as expected. This filter can also be useful for any other type of glitch that might happen during the process of VOU _T rising (instantaneous current demand of load, non-linear load etc.).

[0049] The Glitch Filter 410 can take the form of a closed loop RC circuit that helps control the output voltage ramp. Figure 5 is a schematic diagram of a Glitch Filter circuit 410 in accordance with one embodiment of the present invention. As shown, the Glitch Filter circuit 410 includes a first transistor Ns (NMOS enhancement mode) having a gate voltage of Vys, which is supplied from Voltage Sensor circuit 404, while the source is coupled to VOU _T - A second transistor Nbypass (NMOS, native or depletion mode) is coupled to the drain of the first transistor Ns. A capacitor C _B is coupled between the source of the first transistor Ns (VOU _T ) and the gate of the second transistor Nbypass- A resistor Recharge is coupled between the capacitor C _B (and gate of Nbypass) and ground.

[0050] In the illustrated example, the Glitch Filter circuit 410 is generally configured to turn on when the output voltage VOU _T begins to rise. Specifically, the Glitch Filter circuit 410 is controlled by a V _V s signal from Voltage Sensor 404. In one embodiment, V _V s is high until power transistor M _P leaves the cut-off region. At first when V _V s is high, transistor Ns conducts.

[0051] Capacitor C _B and Recharge form a high pass filter (HPF) with knee frequency of:

2nR(iischargeCB

[0053] All the frequencies higher than this knee frequency are shortened and form voltage at the gate of native transistor Nbypass- Consequently, this transistor Nbypass is also opened (it means, that GF "feels the glitch") and conducts other frequencies, which the CeRdischarge filter was unable to filter. When the glitch is filtered from VOUT, bypass closes, and VOUT continues to build up. The filter may also be useful during VOUT rise. [0054] When the output voltage VOUT goes up fast (e.g., faster than the RC time constant of the Glitch Filter circuit), the capacitor CB discharges and the gate voltage of transistor Nbypass increases so that transistor Nbypass turns on and conducts current. The result is a voltage drop on VOUT when VOUT increases too quickly. If the output voltage goes up slowly (e.g., slower than the RC time constant), in contrast, capacitor CB charges and the gate of Nbypass is not increased. As a result of no increase in gate voltage (e.g., relative to the source voltage), transistor Nbypass remains off and does not affect VOUT- In this embodiment, the Voltage Sensor 404 is also configured to cause the Glitch Filter circuit to turn off in response to the Voltage Sensor's output voltage (Vvs) becoming stable (e.g., decreasing towards turning M _P on). As the output Vvs of the sensor circuit 404 slowly decreases and is applied to the gate of transistor Ns, Ns is slowly turned off (in accordance to slow turning of M _P on, as M _P is the power transistor capable to drive the full current possibility of the switch. Therefore, the Glitch Filter 410 does not undergo high current stress when there is a "glitch"). At this stage the Ns transistor's gate voltage falls and its current capability decreases once VGS drops below the threshold of Ns and the Glitch Filter circuit no longer provides a filtering as the rise-up has finished.

[0055] As VOUT approaches V™, transistor M _c enters the linear region and its V _D s approaches 0. As a result, the Ramp-Up Control circuit 402 can provide only limited maximal current to load circuit 412. To provide more load current, Voltage Sensor 404 is operable to react to the output voltage VOUT as it approaches V™ (e.g., 75% and use such output voltage VOUT to provide more drive to the load circuit 412 by turning on a large power transistor M _P to conduct onto the VOUT node.

[0056] In a specific implementation, the voltage output VOUT from the Ramp-Up Control circuit 402 is supplied to the gate of a first transistor M _V si (PMOS, enhancement mode) in the Voltage Sensor circuit 404. The source of this first transistor is also coupled to supply voltage Vcc, and the drain is coupled to current source (or mirror) ISNSI - Transistors M _V si and Mvs2 are "on" when VQUT is low. As the output voltage VQUT from the Ramp-Up Control circuit 402 approaches a predefined threshold (e.g., 3 V) and results in an increase in VGS for Mysi, the transistor M _V si reaches cut-off. Consequently, the input voltage to the Schmitt Trigger (Schl) also decreases from V<x as M _V si reaches cutoff. That is, M _V si can no longer hold enough current to hold the input of Schl high. Once the bottom threshold of Schl is reached, Schl outputs an inversion of its input, which is output to the gate of M _V s2 to thereby cause M _V s2 (PMOS) to also be put into the cut-off region.

[0057] Appropriately tuned current mirrors Ivsi-Ivs _n are correlated to the same slew rate generated by the mirrored current sources I _REF and cause capacitor C _V s to slowly charge so as to result in a controlled Vys- As Vys slowly drops, power transistor M _P (PMOS enhancement mode) slowly opens according to the selected slew rate, finalizing the ramp up of the output voltage VOU _T to drive its full-specification) load current.

[0058] In an alternative embodiment, a large decoupling capacitor C _decoup i _e is attached to the drain of Mc and the Glitch Filter is not used. Figure 7 is a schematic diagram of a decoupling capacitor Cdecou _p ie attached to the drain of transistor Mc. The other components of the programmable switch of Figure 4 may also be present, except for the Glitch Filter circuit.

[0059] Certain embodiments of an analog programmable voltage supply circuit provide a smooth linear voltage ramping profile (unlike discrete ramp-up of by digital circuit) as shown in Figure 6. As shown, the output voltage VOU _T remains linear for different capacitive load values, 75 pF and 1 pF, as well as a load current that changes non-linearly from 1mA to 3.1mA. In this graph, the slew rate was adjusted to be 6.25mV/^s. The bottom graph of Figure 6 shows two converging linear profiles for the output voltage, even when there are two very different capacitance values. That is, a linear rise for the output voltage is achieved without being affected by non-linear varying loads and capacitance.

[0060] In order to avoid high short circuit current conductance, a Break-Before-Make circuit 406 may be employed. Once the enable flag (PUN_EN enable signal) for the power switch is removed, the power circuitry is caused to be turned off. After the power enable flag is removed, the Pull Down Network (PDN) 408 is activated (via PDN_EN enable signal) to discharge the output, VOU _T , and the CC/CD input, Vc. So in the case of the state "switch disabled" (Enable=0), the PDN_EN is the delayed inversion of PUN_EN. In the case of the state "switch enabled" (Enable=l), the PUN_EN is the delayed inversion of PDN EN. [0061] The programming of this new power switch circuit allows choosing a total I _REF current, yielding the demanded SR. This new technique described here allows highly effective control of the SR along with "clean" (low glitches) output and linear (analog) ramp- up. During ramp up, the ability of a power switch to provide current to the load is limited by maximal current ability of the Ramp-Up Control circuit 402. In cases in which more current needs to be provided to the load before reaching nominal output voltage, the inversion threshold of the Schl might be corrected to cause M _P to turn on sooner. Additionally, current mirror IS _N SI ^ma y be tuned so as to increase current sinking and allow M _P to turn on earlier.

[0062] The power transistor Mp can continue providing current to the load circuit 412 and such power transistor's slew rate can be the same as of the Ramp-Up Control circuit 402 because the final stage of the Voltage Sensor 404 can be designed by the same principle using an I-C network of mirrored currents I _V s and capacitor C _V s-

[0063] Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Therefore, the described embodiments should be taken as illustrative and not restrictive, and the invention should not be limited to the details given herein but should be defined by the following claims and their full scope of equivalents.