Title:
PROTECTIVE SHEET FOR SEMICONDUCTOR PROCESSING, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2023/281858
Kind Code:
A1
Abstract:
[Problem] To provide a protective sheet for semiconductor processing that sufficiently suppresses an electrostatic charge produced during processing of a wafer and suppresses cracking of chips during peel-off, even when the wafer is processed to be thin by DBG or similar, and to provide a semiconductor device manufacturing method in which said protective sheet for semiconductor processing is used. [Solution] A protective sheet for semiconductor processing, having: a substrate; an electrostatic charge prevention layer; an energy ray-curable adhesive layer; and a buffer layer, wherein the surface resistivity of the adhesive layer after energy ray curing is 5.1×1012 Ω/cm2 to 1.0×1015 Ω/cm2.
Inventors:
TAMURA KAZUYUKI (JP)
Application Number:
PCT/JP2022/014413
Publication Date:
January 12, 2023
Filing Date:
March 25, 2022
Export Citation:
Assignee:
LINTEC CORP (JP)
International Classes:
C09J201/00; C09J7/38; H01L21/301; H01L21/304
Domestic Patent References:
| WO2015156389A1 | 2015-10-15 |
Foreign References:
| JP2020038985A | 2020-03-12 | |||
| JP2011210944A | 2011-10-20 | |||
| JPH11269436A | 1999-10-05 | |||
| JP2021027091A | 2021-02-22 | |||
| JP2015183008A | 2015-10-22 | |||
| JP2012212732A | 2012-11-01 |
Attorney, Agent or Firm:
MAEDA & SUZUKI (JP)
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