PROVIDING A FEEDBACK LOOP IN A LOW LATENCY SERIAL INTERCONNECT ARCHITECTURE

Title:

PROVIDING A FEEDBACK LOOP IN A LOW LATENCY SERIAL INTERCONNECT ARCHITECTURE

Document Type and Number:

WIPO Patent Application WO/2012/082572

Kind Code:

A3

Abstract:

In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Inventors:

SHOOR EHUD (IL)
LAZAR DROR (IL)
BENHAMOU ASSAF (IL)

Application Number:

PCT/US2011/064306

Publication Date:

September 20, 2012

Filing Date:

December 12, 2011

Export Citation:

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Assignee:

INTEL CORP (US)
SHOOR EHUD (IL)
LAZAR DROR (IL)
BENHAMOU ASSAF (IL)

International Classes:

H04L29/06; H03M9/00

Foreign References:

US20100211859A1	2010-08-19
US20080263381A1	2008-10-23
US20090161738A1	2009-06-25

Attorney, Agent or Firm:

ROZMAN, Mark J. (Pruner & Hu P.C.,1616 S. Voss Rd., Ste. 75, Houston Texas, US)

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