| WO/2018/218313 | IMPROVED CHIPLESS RFID SYSTEM AND METHOD |
| JPH0680505 | PROBLEM TO BE SOLVED: To learn a method of a multi-layer neural network. |
| JPH04141762 | NETWORK LEARNING SYSTEM |
PELLERANO STEFANO (US)
CLARKE JAMES S (US)
ELSHERBINI ADEL A (US)
CAUDILLO ROMAN (US)
YOSCOVITS ZACHARY R (US)
MICHALAK DAVID J (US)
PILLARISETTY RAVI (US)
GEORGE HUBERT C (US)
THOMAS NICOLE K (US)
SINGH KANWALJIT (NL)
| WO2017015432A1 | 2017-01-26 |
| US20140264287A1 | 2014-09-18 | |||
| US20140246652A1 | 2014-09-04 | |||
| US20160148112A1 | 2016-05-26 | |||
| US9501748B2 | 2016-11-22 |
| Claims: 1. A quantum integrated circuit assembly, comprising: a substrate; a plurality of qubits over or in the substrate; and a resonator structure over or in the substrate, the resonator structure comprising: a signal line, and a plurality of periodic conductive elements substantially perpendicular to the signal line. 2. The quantum integrated circuit assembly according to claim 1, wherein the plurality of periodic conductive elements are below the signal line and are separated from the signal line by a dielectric material. 3. The quantum integrated circuit assembly according to claim 2, wherein each conductive element comprises a strip of an electrically conductive material. 4. The quantum integrated circuit assembly according to claim 2, wherein a period of the plurality of periodic conductive elements is between 20 and 2,000 nanometers. 5. The quantum integrated circuit assembly according to any one of clams 2-4, wherein the plurality of periodic conductive elements is provided at a distance between 10 and 1,000 nanometers below the conductor strip. 6. The quantum integrated circuit assembly according to any one of clams 2-4, wherein the dielectric material separating the plurality of periodic conductive elements from the signal line comprises epitaxial silicon. 7. The quantum integrated circuit assembly according to claim 1, wherein the plurality of periodic conductive elements comprise periodic pairs of conductive elements, each pair comprising a first conductive element and a second conductive element extending from the signal line in opposite directions. 8. The quantum integrated circuit assembly according to claim 7, wherein, for each of the first and the second conductive elements, an end section of the conductive element is rounded. 9. The quantum integrated circuit assembly according to claim 7, wherein the resonator structure is a coplanar waveguide further comprising a ground plane on each side of the signal line, and wherein a shape of a portion of the ground plane on each side of the signal line conforms to a shape of an end section of one of the first and the second conductive elements that is closest to said ground plane. 10. The quantum integrated circuit assembly according to claim 1, wherein the plurality of periodic conductive elements comprise periodic pairs of conductive elements, each pair comprising a first conductive element extending from a first ground plane of the resonator structure towards the signal line and a second conductive element extending from a second ground plane of the resonator structure towards the signal line opposite to the first conductive element. 11. The quantum integrated circuit assembly according to claim 10, wherein, for each of the first and the second conductive elements, an end section of the conductive element is rounded. 12. The quantum integrated circuit assembly according to claim 10, wherein a shape of a portion of the signal line on each side of the signal line conforms to a shape of an end section of one of the first and the second conductive elements that is closest to said portion. 13. The quantum integrated circuit assembly according to claim 1, wherein: the plurality of periodic conductive elements comprises periodic pairs of conductive elements, each pair comprises: a first conductive element between the signal line and a first ground plane structure of the resonator structure, the first conductive element comprising a first interdigitated capacitor, and an opposite second conductive element between the signal line and a second ground plane structure of the resonator structure, the second conductive element comprising a second interdigitated capacitor. 14. The quantum integrated circuit assembly according to claim 13, wherein: the first conductive element comprises a first portion extending from the signal line and a second portion extending from the first ground plane structure, the first and second portion of the first conductive element forming the first interdigitated capacitor, and the second conductive element comprises a first portion extending from the signal line and a second portion extending from the second ground plane structure, the first and second portion of the second conductive element forming the second interdigitated capacitor. 15. The quantum integrated circuit assembly according to any one of claims 7-14, wherein each of the first and second conductive elements has a length between 1,000 and 100,000 nanometers. 16. The quantum integrated circuit assembly according to any one of claims 7-14, wherein each of the first and second conductive elements has a width between 10 and 1,000 nanometers. 17. A method of manufacturing a quantum device, the method comprising: providing a signal line over or in a substrate; providing a plurality of periodic conductive elements substantially perpendicular to at least a portion of the signal line; and providing a plurality of qubits over or in the substrate, wherein the signal line and the plurality of periodic conductive elements form a resonator structure for one or more of the plurality of qubits. 18. The method according to claim 17, wherein the substrate is a silicon substrate and wherein providing the signal line and/or providing the plurality of periodic conductive elements comprises implanting dopants in a portion of a top layer of the substrate and activating the implanted dopants. 19. The method according to claim 18, wherein the top layer of the substrate comprises an uppermost layer of intrinsic or low-doped epitaxially grown silicon. 20. The method according to claim 19, wherein the uppermost layer of intrinsic or low-doped epitaxially grown silicon comprises isotopically enriched silicon. 21. The method according to claim 19, wherein the uppermost layer has a thickness between 0.5 and 5 micrometers (microns). 22. The method according to any one of claims 17-21, wherein the plurality of periodic conductive elements are provided before providing the signal line and the method further comprises epitaxially growing silicon on the top layer of the substrate after providing the plurality of periodic conductive elements and before providing the signal line. 23. The method according to any one of claims 17-21, further comprising providing one or more first interconnects for connecting the signal line to a signal source and one or more second interconnects for connecting at least one ground plane of the resonator structure to a ground potential. 24. A quantum computing device, comprising: a quantum processing device that includes a die comprising a substrate, a plurality of qubits over or in the substrate, and a resonator structure over or in the substrate, the resonator structure comprising a signal line and a plurality of periodic conductive elements substantially perpendicular to at least a portion of the signal line; a non-quantum processing device coupled to the quantum processing device; and a memory device to store data generated by the plurality of qubits during operation of the quantum processing device. 25. The quantum computing device according to claim 24, further comprising a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin. |
Technical Field
[0001] This disclosure relates generally to the field of quantum computing, and more specifically, to quantum circuit/qubit devices that use resonators.
Background
[0002] Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.
Brief Description of the Drawings
[0003] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
[0004] FIG. 1 provides a schematic illustration of an example quantum circuit, according to some embodiments of the present disclosure.
[0005] FIGS. 2A and 2B provide a schematic illustration of a conventional coplanar waveguide provided over a substrate.
[0006] FIGS. 3A-3C provide a schematic illustration of a slow wave coplanar waveguide provided over a substrate, with perpendicular conductive elements provided in the plane of and extending from a signal line, according to some embodiments of the present disclosure.
[0007] FIGS. 4A-4C provide a schematic illustration of a slow wave coplanar waveguide as in FIGS. 3A-3C but having rounded corners, according to some embodiments of the present disclosure.
[0008] FIGS. 5A-5C provide a schematic illustration of a slow wave coplanar waveguide provided over a substrate, with perpendicular conductive elements provided in the plane of a signal line, extending from each of the ground planes towards the signal line, according to some embodiments of the present disclosure.
[0009] FIGS. 6A-6C provide a schematic illustration of a slow wave coplanar waveguide as in FIGS. 5A-5C but having rounded corners, according to some embodiments of the present disclosure.
[0010] FIGS. 7A-7C provide a schematic illustration of a slow wave coplanar waveguide provided over a substrate, with perpendicular conductive elements provided in the plane of a signal line and implementing interdigitated capacitors, according to some embodiments of the present disclosure. [0011] FIG. 8 provides a flow chart of a method for fabricating slow wave resonator structures with perpendicular conductive elements provided in the plane of a signal line, according to some embodiments of the present disclosure.
[0012] FIGS. 9A-9C provide a schematic illustration of a slow wave coplanar waveguide with perpendicular conductive elements under the signal line, according to some embodiments of the present disclosure.
[0013] FIG. 10 provides a flow chart of a method for fabricating slow wave coplanar waveguide transmission line structures with perpendicular conductive elements under the signal line, according to some embodiments of the present disclosure.
[0014] FIGS. 11A and 11B are top views of a wafer and dies that may include one or more of slow wave resonator structures disclosed herein.
[0015] FIG. 12 is a cross-sectional side view of a device assembly that may include one or more of slow wave resonator structures disclosed herein.
[0016] FIG. 13 is a block diagram of an example quantum computing device that may include one or more of slow wave resonator structures disclosed herein, in accordance with various embodiments.
Detailed Description
Overview
[0017] As previously described herein, quantum computing, or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. One example of quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e. superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states. Quantum entanglement is another example of quantum-mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole. Yet another example of quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).
[0018] Put simply, superposition postulates that a given particle can be simultaneously in two states, entanglement postulates that two particles can be related in that they are able to instantly coordinate their states irrespective of the distance between them in space and time, and collapse postulates that when one observes a particle, one unavoidably changes the state of the particle and its' entanglement with other particles. These unique phenomena make manipulation of data in quantum computers significantly different from that of classical computers (i.e. computers that use phenomena of classical physics). Classical computers encode data into binary values, commonly referred to as bits. At any given time, a bit is always in only one of two states - it is either 0 or 1. Quantum computers use so-called quantum bits, referred to as qubits (both terms "bits" and "qubits" often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states. Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled.
[0019] Compared to well-established and thoroughly researched classical computers, quantum computing is still in its infancy, with the highest number of qubits in a solid-state quantum processor currently being about 10. One of the main challenges resides in protecting qubits from decoherence so that they can stay in their information-holding states long enough to perform the necessary calculations and read out the results. For this reason, materials, structures, and fabrication methods used for building quantum circuits continuously focus on reducing spurious (i.e. unintentional and undesirable) two-level systems (TLS's), thought to be the dominant source of qubit decoherence. In general, as used in quantum mechanics, a two-level (also referred to as "two-state") system is a system that can exist in any quantum superposition of two independent and physically
distinguishable quantum states. Another challenge that is unique to quantum computing is the ability to provide substantially lossless connectivity between qubits at very low powers, e.g. as low as a power of a single photon that may be present in a particular resonator interconnecting two qubits.
[0020] As the foregoing illustrates, ability to manipulate and read out quantum states, making quantum-mechanical phenomena visible and traceable, and ability to deal with and improve on the fragility of quantum states of a qubit present unique challenges not found in classical computers. These challenges explain why so many current efforts of the industry and the academics continue to focus on a search for new and improved physical systems whose functionality could approach that expected of theoretically designed qubits. Physical systems for implementing qubits that have been explored until now include e.g. superconducting qubits, quantum dot qubits (e.g. Silicon (Si) quantum dot qubits), single trapped ion qubits, photon polarization qubits, etc. [0021] Out of the various physical implementations of qubits listed above, superconducting qubits are promising candidates for building a quantum computer. Superconducting qubits operate based on the Josephson effect, which refers to a macroscopic quantum phenomenon of supercurrent, i.e. a current that, due to zero electrical resistance, flows indefinitely long without any voltage applied, across a device known as a Josephson Junction. Josephson Junctions are integral building blocks in quantum circuits employing superconducting qubit devices, forming the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits.
[0022] Another type of integral building blocks in superconducting qubit devices are resonators used to couple qubits together and to set qubit frequencies. In general, a resonator of a quantum circuit is a microwave transmission line that is deliberately designed to support resonant oscillations (i.e. resonance) within the line, under certain conditions (i.e. a resonant microwave transmission line). Conventionally, resonators of superconducting qubit devices have been implemented as coplanar waveguides (CPWs), which is a particular type of a microwave transmission line.
[0023] Inventors of the present disclosure realized that employing a conventional CPW architecture for forming resonators in superconducting qubit devices may have drawbacks. A length of a resonator needs to support the frequencies typically used for superconducting qubits. When typical qubit frequencies are in the range of 1-10 gigahertz (GHz) of the microwave spectrum, required lengths of the resonators used to control such qubits are on the order of millimeters. Due to the limited space on a typically microprocessor chip, implementing components having such large lengths makes scaling to many qubits to build a quantum computing device difficult.
[0024] Embodiments of the present disclosure propose new microwave resonator structures for providing microwave connectivity to, from, and/or between the qubits, or to set the frequencies that address individual qubits. An exemplary proposed resonator structure includes a resonant microwave transmission line having substantially periodic high-impedance and low-impedance sections along at least a portion of the length of the line, or along the entire length of the line. In some embodiments, such sections can be implemented by providing periodic conductive elements which are substantially perpendicular to the longitudinal dimension of a signal line of a microwave transmission line used to implement the resonator, in order to locally increase line-specific capacitance or inductance (a phenomenon referred to as "loading" of a transmission line structure). In some embodiments, periodic loading may be achieved by providing periodic conductive elements in the same plane and forming a part of (or attached to) either a signal line or each of the ground planes of a resonant microwave transmission line used to implement the resonator. In other embodiments, periodic loading may be achieved by providing periodic conductive elements in a plane below the signal line and separated from the signal line by a dielectric material. Fabrication techniques for forming such resonators are also disclosed.
[0025] In order to provide substantially lossless connectivity to, from, and between the qubits, electrically conductive portions of microwave resonators proposed herein, i.e. signal lines, ground planes, and periodic conductive elements provided perpendicular to the signal line, may be made from one or more superconducting materials. However, some or all of these electrically conductive portions could be made from electrically conductive materials which are not superconducting. In the following, unless specified otherwise, reference to an electrically conductive material implies that a superconducting material can be used. Furthermore, materials described herein as
"superconducting materials" may refer to materials, including alloys of materials, which exhibit superconducting behavior at typical qubit operating conditions (e.g. materials which exhibit superconducting behavior at very low temperatures at which qubits typically operate, but which may not exhibit such behavior at e.g. room temperatures).
[0026] As described above, in one aspect of the present disclosure, a proposed transmission line for superconducting qubits includes a signal line and a plurality of periodic conductive elements provided substantially perpendicular to at least a portion of the signal line. Since providing a conductive element perpendicular to a signal line of a microwave transmission line decreases the impedance of the transmission line at that section (by increasing the capacitance per unit length), periodically providing conductive elements perpendicular to a signal line results in creation of periodic high-impedance and low-impedance sections along the length of a transmission line.
Namely, sections of the proposed resonator structure having the conductive elements provided perpendicular to the signal line are the low-impedance sections while sections without such perpendicular conductive elements (i.e. portions which are in between the sections with the periodic perpendicular conductive elements) are the high-impedance sections. Having alternating high-impedance and low-impedance sections along the length of a resonant transmission line reduces the group velocity of the line, or, phrased differently, increases its group delay, compared to a transmission line structure without such variations in impedance. In turn, reducing the group velocity of a transmission line allows reducing the length of the line necessary to implement a specific phase shift of the propagating microwave signal of a given frequency, hence reducing the dimension of microwave resonators, e.g. resonators implemented as quarter-, half- or full- wavelength resonators. Reducing the length of microwave resonators used in superconducting qubit devices advantageously reduces the chip area required for implementing such resonators, reducing the cost of the quantum circuit device and enabling scaling to larger numbers of interconnected qubits. [0027] Since resonator structures proposed herein have a reduced group velocity (i.e. the speed at which electromagnetic energy, in this case - microwave energy, travels in the resonator), compared to conventional resonators typically used in quantum circuits employing superconducting qubits, the resonators proposed herein are referred to as "slow wave resonators," in order to highlight the difference in group velocities compared to conventional resonator.
[0028] As used herein, the terms such as "resonator structure," "transmission line structure," "signal line structure," and "ground plane structure" may be referred to without using the word "structure." Furthermore, the term "signal line" may be used interchangeably with the terms such as "conductor strip," "signal path," or "center line" as known in microwave engineering.
[0029] While some descriptions are provided with reference to superconducting qubits, in particular to transmons, a particular class of superconducting qubits, teachings of the present disclosure are applicable to implementations of any qubits, including superconducting qubits other than transmons and including qubits other than superconducting qubits, which may employ resonators, all of which implementations are within the scope of the present disclosure. For example, slow wave resonators described herein may be used in hybrid semiconducting- superconducting quantum circuits.
[0030] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.
[0031] Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
[0032] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C). [0033] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
[0034] In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the terms "oxide," "carbide," "nitride," etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20% of a target value based on the context of a particular value as described herein or as known in the art.
Furthermore, as used herein, terms indicating what may be considered an idealized behavior, such as e.g. "superconducting" or "lossless", are intended to cover functionality that may not be exactly ideal but is within acceptable margins for a given application. For example, a certain level of loss, either in terms of non-zero electrical resistance or non-zero amount of spurious two-level systems (TLS's) may be acceptable such that the resulting materials and structures may still be referred to by these "idealized" terms. Specific values associated with an acceptable level of loss are expected to change over time as fabrication precision will improve and as fault-tolerant schemes may become more tolerant of higher losses, all of which are within the scope of the present disclosure.
[0035] Still further, while the present disclosure may include references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature that qubits are operated at. In addition, techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of qubits are in 1-10 GHz, e.g. in 5-10 GHz, range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering. However, advantageously, because excitation energy of qubits is controlled by the circuit elements, qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure.
Quantum computing and slow wave resonators
[0036] FIG. 1 provides a schematic illustration of a quantum circuit 100 that may include any of the transmission lines described herein, according to some embodiments of the present disclosure. As shown in FIG. 1, an exemplary quantum circuit 100 includes a plurality of qubits 102. In some embodiments, the qubits 102 may be superconducting qubits (e.g. transmons), and the quantum circuit 100 may be referred to as a superconducting qubit device. In general, the qubits 100 may be any type of qubits which use microwave resonators.
[0037] As also shown in FIG. 1, an exemplary quantum circuit 100 typically includes a plurality of resonators 104, e.g. coupling and readout resonators, and non-resonant transmission lines 106. The non-resonant transmission lines 106 are typically used for providing microwave signals to different quantum circuit elements and components, such as e.g. various control lines for various qubits. For example, for superconducting qubits, examples of the non-resonant transmission lines 106 include flux bias lines, microwave lines, and drive lines.
[0038] In general, a resonator of a quantum circuit differs from a non-resonant microwave transmission line in that a resonator is a transmission line that is deliberately designed to support resonant oscillations (i.e. resonance) within the line, under certain conditions. In contrast, non- resonant transmission lines may be similar to conventional microwave transmission lines in that they are designed to avoid resonances, especially resonances at frequencies/wavelengths close to the resonant frequencies/wavelengths of any resonators in the proximity of such non-resonant lines. Once non-resonant transmission lines are manufactured, some of them may inadvertently support some resonances, but, during its design, efforts are taken to minimize resonances, standing waves, and reflected signals as much as possible, so that all of the signals can be transmitted through these lines without, or with as little resonance as possible. For example, the ends of non-resonant transmission lines are typically engineered to have a specific impedance (e.g. substantially 50 Ohm) to minimize impedance mismatches to other circuit elements to which the lines are connected, in order to minimize the amount of reflected signal at transitions (e.g., transitions from the chip to the package, the package to the connector, etc.).
[0039] A resonator is made with fixed boundary conditions, and these boundary conditions control the frequencies/wavelengths which will resonate within a given transmission line structure used to implement a resonator. In order to satisfy boundary conditions for resonance, each end of a transmission line that implements a resonator can be either a node, if it is shorted to ground (e.g. by being electrically connected to a ground plane of a transmission line structure that implements the resonator, or to any other ground potential), or an antinode, if it is capacitively or inductively coupled to another quantum circuit element. Thus, resonators 104 differ from non-resonant microwave transmission lines 106 in how these lines are terminated. A line used to route a signal on a substrate, i.e. one of the non-resonant transmission lines 106, typically extends from a specific source, e.g. a bonding pad or another type of electrical connection to a source, to a specific load (e.g. a short circuit proximate to a quantum dot device or another bonding pad or another electrical connection to a load). In other words, non-resonant transmission lines 106 terminate with direct electrical connections to sources and loads. On the other hand, a transmission line resonator is typically composed of a piece of transmission line terminated with an open or short circuit. In this case, for a desired resonant frequency, transmission line length may e.g. be a multiple of a microwave wavelength divided by 4. However, other terminations are possible, for example capacitive or inductive, and in this case the required line length to support resonance will be different from that identified above. For example, capacitive terminations may be used for resonators which are coupled to a line or another resonator by capacitors.
[0040] Besides line termination by capacitive or inductive coupling or a short circuit, in order to support resonant oscillations, transmission lines of the resonators 104 need to be of a specific length that can support such oscillations. That is why, often times, resonators 104 may be laid out on a substrate longer than the actual distance would require (i.e. a non-resonant transmission line would typically be laid out to cover the distance in the most compact manner possible, e.g. without any curves, wiggles, or excess length, while a resonator may need to have curves, wiggles, and be longer than the shortest distance between the two elements the resonator is supposed to couple in order to be sufficiently long to support resonance).
[0041] One type of the resonators 104 used with superconducting qubits are so-called coupling resonators, which allow coupling different qubits together in order to realize quantum logic gates. A coupling resonator may be implemented as a microwave transmission line that includes capacitive or inductive connections to ground on both sides (e.g. a half wavelength resonator), which results in oscillations (resonance) within the transmission line. While the ends of a coupling resonator have open circuits to the ground, each side of a coupling resonator is coupled, either capacitively or inductively, to a respective (i.e. different) qubit by being in sufficient proximity to the qubit. Because each side of a coupling resonator has coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator. In this manner, state of one qubit depends on the state of the other qubit, and the other way around. Thus, coupling resonators may be employed in order to use a state of one qubit to control a state of another qubit, a necessary functionality for implementing logic gates. [0042] Another type of the resonators 104 used with superconducting qubits are so-called readout resonators, which may be used to read the state(s) of qubits. In some embodiments, a
corresponding readout resonator may be provided for each qubit. A readout resonator is similar to a coupling resonator in that it may be implemented as a transmission line that includes a capacitive or an inductive connection to ground on one side. On the other side, a readout resonator may either have a capacitive connection to ground (for a half wavelength resonator) or may have a short circuit to the ground (for a quarter wavelength resonator), which also results in oscillations within the transmission line, with the resonant frequency of the oscillations being close to the frequency of the qubit. A readout resonator is coupled to a qubit by being in sufficient proximity to the qubit, again, either through capacitive or inductive coupling. Due to a coupling between a readout resonator and a qubit, changes in the state of the qubit result in changes of the resonant frequency of the readout resonator. In turn, changes in the resonant frequency of the readout resonator can be read externally via connections which lead to external electronics e.g. wire or solder bonding pads.
[0043] At least some of the resonators 104 shown in FIG. 1 may be implemented as resonant transmission lines in the form of slow wave resonator structures as described herein.
[0044] Coupling resonators and readout resonators 104 may be considered as interconnects for supporting propagation of microwave signals in a quantum circuit. The non-resonant transmission lines 106 may also be considered as being included within a broad category of interconnects.
Further, any other connections for providing microwave or other electrical signals to different quantum circuit elements and components, such as e.g. connections between electrodes of various circuit components, or connections between two ground lines of a particular transmission line for equalizing electrostatic potential on the two ground lines, are also referred to herein as
interconnects. Still further, the term "interconnect" may also be used to refer to elements providing electrical interconnections to/from/between quantum circuit elements and components and non- quantum circuit elements, which may also be provided in a quantum circuit, as well as to electrical interconnections between various non-quantum circuit elements provided in a quantum circuit. Examples of non-quantum circuit elements which may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog to digital converters, mixers, multiplexers, amplifiers, etc.
[0045] In various embodiments, the interconnects included in a quantum circuit could have different shapes and layouts. In general, the term "line" as used herein in context of signal lines or transmission lines does not imply straight lines, unless specifically stated so. For example, some transmission lines or parts thereof (e.g. conductor strips of transmission lines) may comprise more curves, wiggles, and turns while other transmission lines or parts thereof may comprise less curves, wiggles, and turns, and some transmission lines or parts thereof may comprise substantially straight lines. In some embodiments, various interconnects may intersect one another, in such a manner that they don't make an electrical connection, which can be done by using e.g. a bridge, bridging one interconnect over the other.
[0046] In some embodiments, materials forming the interconnects, and in particular the resonator structures described herein, include aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TIN), and/or niobium titanium nitride (NbTiN), all of which are particular types of superconductors, as well as their alloys. However, in various embodiments, other suitable superconductors as well as non-superconducting conductors may be used as well, all of which may be referred to "conductive" or "electrically conductive" materials.
[0047] The qubits 102, the resonators 104, and the non-resonant transmission lines 106 of the quantum circuit 100 may be provided on, over, or at least partially embedded in a substrate (not shown in FIG. 1).
[0048] In various embodiments, quantum circuits such as the one shown in FIG. 1 may be used to implement components associated with a quantum integrated circuit (IC). Such components may include those that are mounted on or embedded in a quantum IC, or those connected to a quantum IC. The quantum IC may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., depending on the components associated with the integrated circuit. The integrated circuit may be employed as part of a chipset for executing one or more related functions in a quantum system.
[0049] In order to highlight the advantages offered by novel quantum circuit transmission line structures proposed herein, it would be helpful to first explain how conventional quantum circuit microwave lines are implemented.
[0050] As mentioned above, conventionally, microwave resonators used in quantum circuits have been implemented as CPWs. An example of a CPW resonator is shown as a CPW 200 in FIGS. 2A and 2B providing, respectively, a perspective and a cross-section illustrations. In FIGS. 2A and 2B, the CPW 200 includes two ground planes 204 and 208 and a signal line 206 provided in the middle, between the two ground planes. The signal line 206 and the ground planes 204 and 208 all lie in the same plane over a dielectric substrate 202 and are all made from electrically conductive materials (e.g. from superconductors). FIG. 2A indicates a height hi, which refers to the thickness of the substrate 202, a strip width Wl of the signal line 206, and slot spaces SI between the signal line 206 and each of the ground planes 204 and 208. The height hi, strip width Wl, and slot spaces SI are parameters that define characteristics of a CPW resonator, such as e.g. impedance of the transmission line and electromagnetic field distribution.
[0051] As described above, using a conventional CPW architecture as shown in FIGS. 2A and 2B may be not be the most suitable architecture for implementing microwave resonators in superconducting qubit devices because the length of such resonators may become prohibitively large if these resonators are to support typical qubit frequencies. However, new microwave resonators proposed herein improve on this problem by reducing the group velocity of the electromagnetic energy travelling therein, thereby allowing to use microwave transmission line structures of shorter lengths for implementing the resonators. In particular, the group velocity can be reduced by ensuring that a resonant transmission line has periodic high-impedance and low-impedance sections along its length (i.e. the high-impedance and low-impedance sections repeat along the length of a transmission line). Various approaches may be taken in order to provide such high-impedance and low-impedance sections along the length of a resonator, all of which being within the scope of the present invention.
[0052] One of such approaches described herein resides in providing periodic electrically conductive elements (i.e. elements made of electrically conductive materials, e.g. of
superconductive materials) disposed substantially perpendicular to a signal line of a microwave transmission line forming the resonator. Such perpendicular periodic conductive elements may be provided either in-plane with the transmission line (i.e. in the same plane where the signal line is provided), an embodiment illustrated in FIGS. 3A-3C, FIGS. 4A-4C, FIGS. 5A-5C, FIGS. 6A-6C, and FIGS. 7A-7C, or below the plane of the transmission line (i.e. below the plane where the signal line is provided), an embodiment illustrated in FIGS. 9A-9C. It should also be noted that, while FIGS, provided herein refer to a CPW as an exemplary transmission line architecture which could be modified to be a slow wave resonator structure as described herein, embodiments of the present disclosure are equally applicable to other transmission line architectures, such as e.g. microstrip, strip line, grounded CPW, etc., by modifying their signal lines and/or regions around their signal lines to include alternative high-impedance and low-impedance structures/elements as proposed herein.
[0053] FIGS. 3A-3C provide a schematic illustration of a slow wave CPW resonator 300 provided over a dielectric substrate 302, with perpendicular conductive elements 310 provided in the plane of a signal line 306 and extending from the signal line 306 towards each of the ground planes 304 and 308, according to some embodiments of the present disclosure. FIG. 3A illustrates a top down view of the slow wave CPW 300 (i.e. the view of the x-y plane of a coordinate system as shown in FIG. 2A), while each of FIGS. 3B and 3C provide cross-section views (i.e. the views of the z-y plane of a coordinate system as shown in FIG. 2A), with the cross-sections taken, respectively, along the planes illustrated in FIG. 3A as planes BB and CC. [0054] As shown in FIGS. 3A-3C, the slow wave CPW 300 includes two upper ground planes 304 and 308 and a signal line 306 provided in the middle, between the two upper ground planes, similar to the ground planes 204 and 208 and the signal line 206 shown in FIGS. 2A and 2B. The signal line 306 and the ground planes 304 and 308 all lie in the same plane over the dielectric substrate 302. In addition, as can be seen in FIG. 3A, the slow wave CPW 300 further includes a plurality of conductive elements 310 provided perpendicular to the signal line 306. Only two of such conductive elements are labeled in FIG. 3A in order to not clutter the drawing, one on each side of the signal line 306, but eight of them are shown in FIG. 3A on each side of the signal line 306, provided periodically along the length of the signal line 306 (i.e., along the x-axis of a coordinate system as shown in FIG. 2A). Of course, in other embodiments, any other number of conductive elements 310 may be provided.
[0055] Together with the number of conductive elements 310 and the qubit frequencies that the slow wave CPW 300 is supposed to support, one or more of the dimensions illustrated in FIGS. 3A-3C (e.g. height Λ2, widths W2, W3, etc.) are parameters to be carefully selected to achieve desired characteristics of the slow wave CPW resonator 300, such as e.g. group velocity and the length used when the CPW 300 implements one of the resonators in a quantum circuit. These parameters will now be described.
[0056] FIGS. 3B and 3C indicate a height Λ2, which refers to the thickness of a dielectric material 302 below the CPW 300. In various embodiments, the height h2 may be greater than about 20 nanometers, e.g. between 100 and 3000 nanometers, including all values and ranges therein.
[0057] FIG. 3B indicates a width W2, which refers to the width of the signal line 306 in regions where there are no perpendicular conductive elements 310 making that width greater (i.e. as shown with the top view of the cross sectional plane BB shown in FIG. 3A). In various embodiments, the width W2 may be between 100 and 100,000 nanometers, including all values and ranges therein, e.g. between 10,000 and 20,000 nanometers or between 1,000 and 10,000 nanometers.
[0058] FIG. 3B further indicates a slot width 52, which refers to the distance from the signal line 306 to each of the first and the second ground plane structures 304 and 308 in regions where there are no perpendicular conductive elements 310 making that width greater (i.e. as shown with the top view of the cross sectional plane BB shown in FIG. 3A). In various embodiments, the slot width 52 may be between 1,000 and 100,000 nanometers, including all values and ranges therein, e.g.
between 10,000 and 20,000 nanometers or between 1,000 and 10,000 nanometers.
[0059] FIG. 3C indicates a width W3, which refers to the width of the signal line 306 in regions where a perpendicular conductive element 310 extends that width (i.e. as shown with the top view of the cross sectional plane CC shown in FIG. 3A). Thus, the width W3 may be viewed as the length (i.e. the largest dimension) of the conductive element 310. In various embodiments, the width W3 may be between 1,000 and 100,000 nanometers, including all values and ranges therein, e.g.
between 20,000 and 50,000 nanometers or between 50,000 and 100,000 nanometers.
[0060] FIG. 3C further indicates a slot width S3, which refers to the distance from the end of the conductive element 310 to each of the first and the second ground plane structures 304 and 308. In various embodiments, the slot width S3 may be between 1,000 and 100,000 nanometers, including all values and ranges therein, e.g. between 10,000 and 20,000 nanometers or between 1,000 and 10,000 nanometers. Since the first and second ground plane structure 304 and 308 are provided parallel to one another, 2*S2+W2=2*S3+W3.
[0061] FIG. 3A indicates a width W4, which refers to the width of each of the conductive elements 310 and a spacing 54, which refers to the distance between two conductive elements 310 immediately adjacent to one another. FIG. 3A further illustrates a period P, where P=S4+W4, which indicates the periodicity of the conductive elements 310 and, thus the periodicity of the high- impedance and low-impedance regions in the CPW 300. In various embodiments, the width W4 may be between 10 and 1,000 nanometers, including all values and ranges therein, e.g. between 10 and 50 nanometers or between 50 and 100 nanometers. In various embodiments, the spacing 54 may be between 10 and 1,000 nanometers, including all values and ranges therein, e.g. between 10 and 50 nanometers or between 50 and 100 nanometers.
[0062] In various embodiments, a thickness of each of the signal line 306, the first and second ground planes 304 and 308, and the conductive elements 310 (i.e. a dimension measured along the z-axis of a coordinate system as shown in FIG. 2A) may be between 20 and 500 nanometers, including all values and ranges therein. In some embodiments, the thickness of the conductive elements 310 may be the same as that of the signal line 306. In other embodiments, the thickness of the conductive elements 310 may be different from, e.g. smaller than, the thickness of the signal line 306. In various embodiments, the signal line 306 and the conductive elements 310 may be made from the same or different materials.
[0063] As can be seen in the view of FIG. 3A, in the embodiment of the CPW 300, the conductive elements 310 are implemented as a continuation of, or an integral part of, the signal line 306, perpendicularly extending from the signal line 306 in opposite directions. Namely, for each conductive element 310 that extends to the left of the signal line 306, towards the first ground plane 304 (i.e. the conductive element 310 to the left of the signal line 306), there is a corresponding conductive element 310 on the opposite side of the signal line 306 that extends to the right of the signal line 306, towards the second ground plane 308 (i.e. the conductive element 310 to the right of the signal line 306), and vice versa. Because such pairs of conductive elements 310 extend away from the signal line but are typically much shorter than the length of the signal line, they may be referred to as "stubs." For example, the length of such stubs 310 on each side of the signal line 306, shown in FIG. 3A as length Ls, could be between 1,000 and 100,000 nanometers, including all values and ranges therein, which can be calculated as [W3-W2)/2. In such an embodiment, along the length L of the CPW 300, portions of the transmission line which include the stubs (e.g. portions such as the one shown in FIG. 3A between lines indicated as lines LI and L2) are the low-impedance portions, while portions of the transmission line which do not have the stubs (e.g. portions such as the one shown in FIG. 3A between lines indicated as lines 12 and 13) are the high-impedance portions. Thus, providing such periodic stubs allows implementing periodic high-impedance and low-impedance sections along the length of the resonator structure and, therefore, advantageously reducing the group velocity of the resonator.
[0064] A coupling resonator may be implemented as a microwave element that includes capacitive or inductive connections to ground on both ends of a signal line of such an element (e.g. a full wavelength resonator, a half wavelength resonator, or a quarter wavelength resonator), which results in oscillations (resonance) when the transmission line supplies photons at the resonant energy.
[0065] When the CPW 300 has capacitive/inductive or direct connections to ground on both ends of the signal line 306 (in FIG. 3A - the upper-most end and the lowest end of the signal line 306 shown), the CPW 300 can support resonance when photons of the resonant energy/frequency are provided within the CPW 300, thus forming a resonator, e.g. one of the resonators 104 shown in FIG. 1. The length L, labeled in FIG. 3A, of such a resonator would depend on at least some of the design parameters including e.g. the number of conductive elements 310, the qubit frequencies that the slow wave CPW 300 is supposed to support, one or more of the dimensions illustrated in FIGS. 3A-3C and described above, as well as the materials used to form each one of the parts of the CPW 300. Namely, if Za is the characteristic impedance of the low-impedance portions (i.e. portions of line with the stubs) and Zb is the characteristic impedance of the high-impedance portions (i.e. portions of line without the stubs) stubs, then assuming that Za«Zb and that S4=W4, then, a slowing factor SF can be expressed in terms of a ratio K between the characteristic impedances of low- and high- impedance portions (i.e., K=Za/Zb) as [sqrt(K)+l/sqrt(K)]/2. The characteristic impedances of low- and high-impedance portions Za ad Zb can be estimated using well-known approaches relating CPW line impedance with signal line width [W2 or W3), ground spacing (52 or 53), substrate thickness and dielectric constant of the substrate 302. The reduction in length L for any type of resonator built with such periodic conductive elements is substantially the same as the slowing factor. The slow wave line composite impedance can be estimated as sqrt(Za*Zb) and can still be designed as required to ensure proper resonant behavior of the CPW 300. [0066] The length of a resonator, and, hence, the length of the signal lines described herein, is primarily set by the desired resonant frequency and propagation velocity. In some embodiments, target frequencies may be between 1 and 10 GHz, e.g. between 3 and 7 GHz. The resonant frequency of a microwave resonator inversely depends on the length of the resonator and directly to the propagation velocity, where, with everything else equal, a longer resonator will resonate at longer wavelengths and, therefore, lower frequencies or a lower propagation velocity will reduce the resonance frequency for the same length resonator, or, conversely, reduce the length of the resonator for the same resonance frequency. Resonators with open/short terminations can have a length equal of multiples of quarter of the wavelength at the resonance frequency. The resonant frequency, and therefore the length of the center conductor (i.e. the signal line), is also affected by the capacitance and inductance of the resonator, including the kinetic inductance of the
superconducting wire, since these determine the group velocity hence the resonator length for a specific resonance frequency. If required, longer resonators for lower resonance frequencies can have lengths that exceed chip length by implementing curves/wiggles in the transmission line. In some embodiments, the length L of the signal line 306 (i.e. the length of the CPW resonator 300) may be between 60 microns and 33 millimeters (mm), including all values and ranges therein, e.g. between 5 mm and 20 mm, or between 6 mm and 15 mm. This length is smaller than the length of the signal line 206 of the conventional CPW resonator 200 shown in FIG. 2A by the slowing factor SF, described above, provided that both resonators are configured to have the same resonant frequency. Consider e.g. that Za = 4 Ohm, Zb = 100 Ohm, in which case the ratio K = 0.04 and the slowing factor SF= 2.6, illustrating that the length of a resonator can be reduced dramatically by employing periodic high- and low-impedance portions.
[0067] While the CPW resonator 300 already provides substantial advantages over conventional CPW resonators such as e.g. the CPW resonator 200, further improvements could be made. One such improvement is based on a realization of the inventors of the present disclosure that having relatively sharp corners of the conductive elements 310, shown in FIG. 3A as corners 312 for one exemplary stub, may not always be desirable because this can creates high values of electrical field concentrated around sharp corners/angles. Higher concentration of electrical field at
metal/dielectric or metal/air interfaces (i.e. at the interfaces of an electrically conductive material, typically conductive/superconductive metal, of the stubs 310 and either the dielectric material or air in contact with it) can increase loss due to interface impurity, hence possibly reducing the resonator quality factor and qubit decoherence times.
[0068] FIGS. 4A-4C provide a schematic illustration of a slow wave coplanar waveguide 400 disposed over a dielectric substrate 302 similar to the CPW 300 shown in FIGS. 3A-3C, but with the conductive elements 310 having rounded corners (shown in FIGS. 4A-4C as conductive stubs 410), according to some embodiments of the present disclosure. Therefore, unless specified otherwise, descriptions provided above for the CPW 300 are applicable to FIGS. 4A-4C and only the differences are described. In particular, in order to not clutter the drawing, FIG. 4A illustrates only a portion of the CPW 400, focusing on the rounded corners of the conductive elements 410, while descriptions provided above regarding e.g. the dimensions L, P, S4, W4, and Ls, as well as descriptions provided regarding the portions between lines LI, L2, and 13 as shown in FIG. 3A are applicable to the CPW 400.
[0069] FIG. 4A illustrates a top down view of the slow wave CPW 400 (i.e. the view of the x-y plane of a coordinate system as shown in FIG. 2A). Each of FIGS. 4B and 4C provide cross-section views (i.e. the views of the z-y plane of a coordinate system as shown in FIG. 2A), with the cross-sections taken, respectively, along the planes illustrated in FIG. 4A as planes BB and CC, similar to the views of FIGS. 3B and 3C.
[0070] In CPW 400, at least some, but preferably all of the relatively sharp corners of the stubs, shown as corners 312 in FIG. 3A, are eliminated by rounding the ends of the conductive elements 410, as is labeled in FIG. 4A for one such rounded end portion 414 of one of the conductive elements 410. In order to maintain the same distance between each point of the end portions 414 of the conductive elements 410 and the corresponding ground plane 404 or 408, the edge of the ground planes facing the conductive elements could also be curved, to follow the shape of the rounded end portions of the conductive elements 410. Thus, as can be seen from analyzing FIGS. 4A-4C, unlike for the CPW 300, for the CPW 400, 2*S2+W2 is not equal to, but is actually less than, 2*S3+W3. In various embodiments, at least a portion of the curved portion 414 may be implemented by having a plurality of straight portions at an angle to one another (i.e. the curved portion 414 does not have a circular/oval shape, but rather a shape of plurality of straight lines approximating a circular/oval shape). The corresponding edge of each of the first and second ground planes may have a concave shape with dimensions and curvature being complementary to those of the convex curved portion 414 to ensure that the shortest distance between each point of the rounded portion 414 to a corresponding point of the ground plane structure is the same for all points of the rounded portion 414, so that a most uniform electrical field distribution could be achieved between the ground planes 404/408 and the curved stubs 410 of the signal line 406.
[0071] While FIGS. 3A-3C and 4A-4C illustrate perpendicular stubs 310/410 extending away from the signal line to each of the ground planes in order to implement periodic high-impedance and low- impedance sections along the length of the transmission line structure, similar effect may be achieved by providing perpendicular stubs extending away from each of the ground planes towards the signal line, as shown in FIGS. 5A-5C and 6A-6C.
[0072] In particular, FIGS. 5A-5C provide a schematic illustration of a slow wave CPW resonator 500 provided over the dielectric substrate 302, with perpendicular conductive elements 510 provided in the plane of a signal line 506, perpendicularly extending from each of the ground planes 504 and 508 towards the signal line 506, according to some embodiments of the present disclosure. The views of each of FIGS. 5A-5C are analogous to those shown in FIGS. 3A-3C and the dimensions shown in FIGS. 3A-3C, such as e.g. h2, 52, W2, S3, 54, W4, P, and L are also applicable to the embodiment shown in FIGS. 5A-5C (although not all of these dimensions are specifically shown in FIGS. 5A-5C in order to not clutter the drawings) and, therefore, in the interests of brevity, are not repeated here.
Furthermore, descriptions with respect to the length Ls of the stubs 310 are applicable to the length of the stubs 510, except that now measured from the respective ground plane 504 or 508, as shown with Ls labeled in FIG. 5A.
[0073] Similar to FIG. 3A, in FIG. 5A, only two of the perpendicular conductive elements 510 are specifically labeled, in order to not clutter the drawing, one on each side of the signal line 506, but eight of them are shown in FIG. 5A on each side of the signal line 506, provided periodically along the length of the signal line 506 (i.e., along the x-axis of a coordinate system as shown in FIG. 2A) but now extending away from the respective ground plane 504/508 towards the signal line 506. Of course, in other embodiments, any other number of conductive elements 510 may be provided.
[0074] As can be seen in the view of FIG. 5A, in the embodiment of the CPW 500, the conductive stubs 510 are implemented as a continuation of, or an integral part of, the respective ground plane 504/508, perpendicularly extending from the respective ground plane 504/508 towards the signal line 306, opposite one another. Namely, for each conductive element 510 that extends from the first ground plane 504 towards the signal line 506 (i.e. the conductive element 510 to the left of the signal line 506), there is a corresponding conductive element 510 on the opposite side of the signal line 506 that extends from the second ground plane 508 towards the signal line 506 (i.e. the conductive element 510 to the right of the signal line 506), and vice versa. Again, because such pairs of conductive elements 510 extend towards the signal line but are typically much shorter than the length of the signal line, they may also be referred to as "stubs," similar to the stubs 310 shown in FIG. 3A.
[0075] Similar to the embodiment of FIGS. 3A-3C, in the embodiment of FIGS. 5A-5C, along the length L of the CPW 500, portions of the transmission line which include the stubs 510 are the low- impedance portions, while portions of the transmission line which do not have the stubs 510 are the high-impedance portions, where providing such periodic pairs of stubs 510 on each side of the signal line 506 allows implementing periodic high-impedance and low-impedance sections along the length of the resonator and, therefore, advantageously reducing the group velocity of the resonator.
Discussions and examples provided with reference to the CPW 300 for the characteristic impedances Za and Zb, the slowing factor SF, and the reduction in length L of the resonator are applicable to the CPW 500 and, therefore, are not repeated here.
[0076] Furthermore, similar to the illustration of FIGS. 4A-4C corresponding to the embodiment shown in FIGS. 3A-3C, the CPW resonator 500 shown in FIGS. 5A-5C may be implemented with having the corners 512 rounded, as is shown in FIGS. 6A-6C.
[0077] FIGS. 6A-6C provide a schematic illustration of a slow wave coplanar waveguide resonator 600 disposed over the dielectric substrate 302 similar to the CPW resonator 500 shown in FIGS. 5A- 5C, but with the conductive elements 510 having rounded corners (shown in FIGS. 6A-6C as conductive stubs 610), according to some embodiments of the present disclosure. Therefore, unless specified otherwise, descriptions provided above for the CPW 500 are applicable to FIGS. 6A-6C and only the differences are described. In particular, in order to not clutter the drawing, FIG. 6A illustrates only a portion of the CPW 600, focusing on the rounded corners of the conductive elements 610, while descriptions provided above regarding e.g. the dimensions L, P, 54, W4, and Is, as well as descriptions provided regarding the portions between lines LI, L2, and L3 as shown in FIG. 3A are applicable to the CPW 600.
[0078] FIG. 6A illustrates a top down view of the slow wave CPW 600 (i.e. the view of the x-y plane of a coordinate system as shown in FIG. 2A). Each of FIGS. 6B and 6C provide cross-section views (i.e. the views of the z-y plane of a coordinate system as shown in FIG. 2A), with the cross-sections taken, respectively, along the planes illustrated in FIG. 6A as planes BB and CC, similar to the views of FIGS. 4B and 4C.
[0079] In CPW 600, at least some, but preferably all of the relatively sharp corners of the stubs, shown as corners 512 in FIG. 5A, are eliminated by rounding the ends of the conductive elements 610, as is labeled in FIG. 6A for one such rounded end portion 614 of one of the conductive elements 610. In order to maintain the same distance between each point of the end portions 614 of the conductive elements 610 and the signal line 606, the edge of the signal line 606 facing the conductive elements 610 could also be curved, to follow the shape of the rounded end portions of the conductive elements 610. Thus, as can be seen from analyzing FIGS. 6A-6C, sides of the signal line 606 facing the ground planes 604 and 608 may be periodically curved in a wave-like manner, with the period being the same as the period P of the periodic stubs 610. In other words, the top view of FIG. 6A illustrates that the sides of the signal line 606 facing the ground planes 604 and 608 have a plurality of hills (the top view of FIG. 6A where the cross-sectional line BB is) and valleys (the top view of FIG. 6A where the cross-sectional line CC is). Thus, the width W2 of the signal line 606 in portions where there are no stubs 610 (i.e. the view of FIG. 6B) may be greater than a width W6 of the signal line 606 in portions where stubs 610 are present (i.e. the view of FIG. 6C), to account for the fact that the sides of the signal line 606 are curved to follow the shape of the curved portions 614 of the stubs 610 in order to keep the distance between the signal line 606 and the opposing points of the curved portions 614 of the stubs 610 constant (i.e. equal to S3). The difference between W2 and W6 may be e.g. between 0.25 and 1 times the width of the stubs (from 0.25*W4 to 1*W4, with W4 as in FIG. 3A).
[0080] In various embodiments, at least a portion of the curved portions 614 may be implemented by having a plurality of straight portions at an angle to one another (i.e. the curved portion 614 does not have a circular/oval shape, but rather a shape of plurality of straight lines approximating a circular/oval shape). The corresponding side of the signal line 606 may have a concave shape with dimensions and curvature being complementary to those of the convex curved portion 614 to ensure that the shortest distance between each point of the rounded portion 614 to a
corresponding point of the signal line 606 is the same for all points of the rounded portion 614, so that a uniform electrical field distribution could be achieved between the curved stubs of the ground planes 604/608 and the signal line 606.
[0081] As the foregoing illustrates, the embodiment shown in FIGS. 3A-3C provides periodic loading to achieve the slow wave effect by keeping the width of each of the ground planes constant while changing the width of the signal line along the length of the signal line (i.e. the stubs 310 extending away from the signal line change the width of the signal line, compared to the width of the signal line without the stubs, by the length of the two stubs, one on each side of the signal line), whereas the embodiment shown in FIGS. 5A-5C provides periodic loading to achieve the slow wave effect by keeping the width of the signal line constant while changing the width of the ground planes along the length of the signal line (i.e. the stubs 510 extending away from ground planes change the width of each of the ground planes compared to the width of each ground plane without the stubs by the length of the stub). Yet another embodiment of a slow wave CPW resonator with in-plane periodic elements provided substantially perpendicular to a signal line is illustrated in FIGS. 7A-7C. This embodiment is based on a recognition that adding interdigitated capacitive fingers to such periodic elements perpendicular to the signal line may allow achieving higher capacitance per unit length for the same minimum metal to metal spacing achievable using the fabrication technique, thus increasing the periodic loading. In turn, increasing the periodic loading increases the slow wave effect. [0082] In particular, FIGS. 7A-7C provide a schematic illustration of a slow wave CPW resonator 700 provided over the dielectric substrate 302, with perpendicular conductive elements 710 provided in the plane of a signal line 706, extending in a substantially perpendicular direction, between the signal line 706 and a respective one of the ground planes 704 and 708, according to some embodiments of the present disclosure. The views of each of FIGS. 7A-7B are analogous to those shown in FIGS. 3A-3B and the dimensions shown in FIGS. 3A-3B, such as e.g. Λ2, 52, W2, 54, W4, P, and L are also applicable to the embodiment shown in FIGS. 7A-7B (although not all of these dimensions are specifically shown in FIGS. 7A-7B in order to not clutter the drawings) and, therefore, in the interests of brevity, are not repeated here. FIG. 7C is different from FIG. 3C in that FIG. 7C is an enlarged view of a portion of the CPW resonator 700 within the dashed box indicated in FIG. 7A (i.e. FIG. 7C provides a top down view analogous to the view of FIG. 7A).
[0083] Similar to FIG. 3A, in FIG. 7A, only two of the perpendicular conductive elements 710 are specifically labeled, in order to not clutter the drawing, one on each side of the signal line 706, but more of them are shown in FIG. 7A on each side of the signal line 706, provided periodically along the length of the signal line 706 (i.e., along the x-axis of a coordinate system as shown in FIG. 2A) but now extending both from the signal line 706 and from the respective ground plane 704/708, as described below. Of course, in other embodiments, any other number of conductive elements 710 may be provided.
[0084] As can be seen in the view of FIG. 7C, in the embodiment of the CPW 700, each of the conductive stubs 710 has a first portion 712 extending from the signal line 706 towards a respective ground plane 704 or 708 (the plane 708 for the exemplary stub 710 shown in FIG. 7C), and a second portion 714 extending from the respective ground plane 704 or 708 (again, (the plane 708 for the exemplary stub 710 shown in FIG. 7C) towards the signal line 706. In this embodiment, the first and second portions 712 and 714 of a given conductive element 710 are opposite one another and their opposing ends have "fingers" in an area 716 which interleave to form an interdigitated capacitor, as shown in FIG. 7C. Similar to the previous in-plane embodiments, for each conductive element 710 that extends between the first ground plane 704 and the signal line 706 (i.e. the conductive element 710 to the left of the signal line 706), there is a corresponding conductive element 710 on the opposite side of the signal line 706 that extends between the second ground plane 708 and the signal line 706 (i.e. the conductive element 710 to the right of the signal line 706), and vice versa. Again, because such conductive elements 710 are typically much shorter than the length of the signal line, they may also be referred to as "stubs," similar to the stubs 310 shown in FIG. 3A and stubs 510 shown in FIG. 5A. Together, the first and second portions 712 and 714 of each stub 710 cover the distance 52 between the signal line 706 and the respective ground plane. [0085] Similar to the embodiment of FIGS. 3A-3C, in the embodiment of FIGS. 7A-7C, along the length L of the CPW 700, portions of the transmission line which include the stubs 710 are the low- impedance portions, while portions of the transmission line which do not have the stubs 710 are the high-impedance portions, where providing such periodic pairs of stubs 710 on each side of the signal line 706 allows implementing periodic high-impedance and low-impedance sections along the length of the resonator and, therefore, advantageously reducing the group velocity of the resonator.
Discussions and examples provided with reference to the CPW 700 for the characteristic impedances Za and Zb, the slowing factor SF, and the reduction in length L of the resonator are applicable to the CPW 700 and, therefore, are not repeated here.
[0086] The first and the second portions 712 and 714 are illustrated in FIG. 7C with patterns different from one another and different from the solid color used to show the signal line 706 and the ground plane 708, which is done merely to clearly illustrate the shape of the first and second portions 712 and 714, in particular how they face one another to form an interdigitated capacitor in an area 716. However, the different patterns used for these elements does not imply that the elements have to be made of different materials. In fact, the first portion 712 may form an integral part of the signal line 706 and may be made of the same electrically conductive material as the signal line 706, and the second portion 714 may form an integral part of the ground plane 708 and may be made of the same electrically conductive material as the ground plane 708 (which could, but does not have to, be the same as the electrically conductive material of the signal line 706).
[0087] In various embodiments, quantum circuits with slow wave resonator structures with in- plane perpendicular conductive elements as described above may be fabricated using any suitable fabrication techniques.
[0088] FIG. 8 provides a flow chart of a method 800 for fabricating slow wave resonator structures with perpendicular conductive elements provided in the plane of a signal line, according to some embodiments of the present disclosure. Although the operations of the method 800 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the method 800 may be illustrated with reference to one or more of the embodiments discussed above, but the method 800 may be used to manufacture any suitable quantum circuit component comprising one or more slow wave resonator structures with perpendicular conductive elements provided in the plane of a signal line according to any embodiments disclosed herein.
[0089] The method 800 may begin with providing a signal line, ground plane(s) and perpendicular conductive elements in the plane of the signal line over a substrate (process 802 shown in FIG. 8). [0090] The substrate used in the process 802, e.g. the substrate 302 as described above, may comprise any substrate suitable for realizing quantum circuit components described herein. In one implementation, the substrate may be a crystalline substrate such as, but not limited to a silicon or a sapphire substrate, and may be provided as a wafer or a portion thereof. In other implementations, the substrate may be non-crystalline. In general, any material that provides sufficient advantages (e.g. sufficiently good electrical isolation and/or ability to apply known fabrication and processing techniques) to outweigh the possible disadvantages (e.g. negative effects of spurious TLS's), and that may serve as a foundation upon which a quantum circuit may be built, falls within the spirit and scope of the present disclosure. Additional examples of substrates include silicon-on-insulator (SOI) substrates, lll-V substrates, and quartz substrates.
[0091] In some embodiments, the substrate may be cleaned prior to or/and after any of the processes for forming slow wave resonator structures described herein, e.g. to remove surface- bound organic and metallic contaminants, as well as subsurface contamination. In some embodiments, cleaning may be carried out using e.g. a chemical solutions (such as peroxide), and/or with UV radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g. using HF).
[0092] In some embodiments, any suitable deposition and patterning techniques may be used for forming the signal line, ground plane(s) and perpendicular conductive elements in the process 502. In such embodiments, the signal line, ground plane(s) and perpendicular conductive elements may comprise any conducting or superconducting material suitable for serving as an interconnect in a quantum circuit, such as e.g. aluminum (Al), niobium (Nb), niobum nitride (NbN), niobium titanium nitride (NbTiN), titanium nitride (TiN), molybdenum rhenium (MoRe), etc., or any alloy of two or more superconducting/conducting materials. These materials may be deposited over the substrate using any known techniques for depositing conducting/superconducting materials, such as e.g. atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g. evaporative deposition, magnetron sputtering, or e-beam deposition), chemical vapor deposition (CVD), or electroplating, and patterned using any known patterning techniques, e.g. photolithographic patterning. In some embodiments, the conducting or superconducting materials for forming the signal line, ground plane(s) and perpendicular conductive elements in the process 802 could, first, be deposited and then substractively patterned. In other embodiments, first, openings in the substrate may be formed in accordance with the desired locations and geometry of the signal line, ground plane(s) and perpendicular conductive elements, and then the openings may be filled with the conducting or superconducting materials as described above, thus forming the signal line, ground plane(s) and perpendicular conductive elements in the process 802. [0093] In other embodiments, the signal line, ground plane(s) and perpendicular conductive elements may be formed in the process 802 using dopant implantation and subsequent activation of dopants. In such embodiments, the process 802 may begin with depositing a mask for the subsequent dopant implantation to form the signal line, ground plane(s) and perpendicular conductive elements. In some such embodiments, it may be particularly advantageous to use a silicon (Si) or a silicon germanium (SiGe) substrate in the process 802, because of the established techniques for dopant implantation and epitaxial growth on such substrates and because such substrates may be suitably low-loss in terms of spurious TLS's.
[0094] Prior to providing a dopant implantation mask on the substrate in the process 802, any standard processing cleaning techniques as known in the art may be applied to obtain single crystal silicon surface that is either as received from a supplier or has an intrinsic (i.e. non-doped or low- doped, where doping is either unintentional or deliberate) epitaxially grown silicon region in the upper 0.5 to 8 micrometers (microns). In various implementations, this thin epitaxially grown region may comprise silicon that is sufficiently pure so that it can behave as a low-loss insulator at qubits operating temperatures (i.e. either no dopants or sufficiently low-level of dopants) or might be isotopically enriched 28Si (i.e. sufficiently few atoms with nuclear moments to ensure a low loss).
[0095] In this context, non-doped or low-doped silicon implies a non-conductive silicon at temperatures at which qubits operate (i.e. cryogenic temperatures). A person of ordinary skill in the art would recognize that intrinsic layers may sometimes be accidentally doped with defects due to e.g. the addition of unintentional impurities (e.g., oxygen, residual dopants in the chamber, etc.) or unintentional doping from the highly conductive region by diffusion during subsequent thermal processing. Furthermore, sometimes dopants may be deliberately added to materials for reasons such as e.g. thermal or mechanical stability. As long as dopants, whether unintentional or deliberately added, are in amounts that are low enough so that the substrate used in the process 802 may still be considered low-loss and insulating at low temperatures at which qubits operate, such silicon may be referred to as intrinsic or non-doped silicon.
[0096] After that, the mask may be provided over the substrate in any manner known in the art for providing suitable ion implantation masks, e.g. using photoresist and patterning of the photoresist in a manner similar to that described above. Dimensions and shape/geometry of the openings in the mask may be the same or comparable to the dimensions and shape/geometry of the signal line, ground plane(s) and perpendicular conductive elements to be formed, and could be as described above with reference to the dimensions and shape/geometry of the CPW resonators 300, 400, 500, 600, and 700 described above. [0097] Next, dopants are implanted into the substrate through the openings in the mask, which results in dopants implanting in portions of the substrate exposed by the openings. Dopants may also be implanted into the mask, but dopants implanted into mask do not reach the substrate below it.
[0098] Dopant implantation may be performed by any known dopant implantation techniques. For example, a Si or SiGe substrate may be doped with phosphorus (P) or arsenic (As) to doping concentrations ranging lel8 to le21, including all values and ranges therein, e.g. to about le20. After dopant implantation, the mask may be removed and the substrate may be annealed to activate the dopants. Annealing to activate dopants may, for example, be performed at
temperatures in the range of 900" C to 1100" C, including all values and ranges therein, for a time period in the range of 1 nanoseconds to 1 minute, including all values and ranges therein. As a result, doped regions of the substrate are made conductive or superconductive, as suitable for forming the signal line, ground plane(s) and perpendicular conductive elements of a slow wave resonator structure employed in a quantum circuit. The substrate comprising implanted and activated dopants may then, optionally, be cleaned again, using any suitable cleaning techniques as known in the art.
[0099] In some embodiments, the signal line, ground plane(s) and perpendicular conductive elements could be formed in the process 802 using a combination of metal deposition and patterning and dopant implantation.
[0100] In various embodiments, some or all of the electrically conductive/superconductive materials used to implement the signal line, ground plane(s) and perpendicular conductive elements in the process 802 could be the same or different materials.
[0101] The method 800 may further include providing the qubits (process 804 shown in FIG. 8). Any of the known methods could be used for providing the qubits in the process 804, all of which being within the scope of the present disclosure. In some embodiments, at least some of the processes of forming the signal line and the ground planes could also be used to fabricate at least parts of the qubits (i.e. qubits and parts of the slow wave resonator structures could be fabricated in some shared process steps). In other embodiments, qubits may be fabricated after all of most of the fabrication processes used for forming the slow wave resonator structure are finished, in order to eliminate or reduce potential negative impacts due to the fabrication processes used for forming the slow wave resonator structure on the integrity and performance of the qubits.
[0102] Turning back to other scenarios for implementing slow wave architecture in microwave elements employed in quantum circuits, in some embodiments, alternating high-impedance and low-impedance sections along the length of the microwave signal line may be implemented by providing conductive elements perpendicular to the signal line, as described above for the conductive elements 310, 410, 510, 610, and 710, but this time provided below the signal line. In such an embodiment, along the length of the transmission line, portions of the transmission line having conductive elements below the signal line are the low-impedance portions, while portions of the transmission line which do not have the conductive elements below the signal line are the high- impedance portions. Providing such periodic conductive elements below the signal line allows implementing periodic high-impedance and low-impedance sections along the length of the transmission line structure and, therefore, advantageously reducing the group velocity of the transmission line. Such an embodiment is illustrated in FIGS. 9A-9C for the example of a CPW architecture.
[0103] FIGS. 9A-9C provide a schematic illustration of a slow wave coplanar waveguide 900 disposed over a dielectric substrate 302 similar to the CPW 300 shown in FIGS. 3A-3C, but with the conductive elements 910 being provided under the surface of the substrate 302, below the signal line 906, and centered with respect to the signal line 906, according to some embodiments of the present disclosure. Therefore, unless specified otherwise, descriptions provided above for the CPW 300 are applicable to FIGS. 9A-6C and only the differences are described. In particular, descriptions provided above regarding e.g. the dimensions L, P, S2-S4, and W2-W4, as well as descriptions provided regarding the portions between lines LI, L2, and L3 as shown in FIG. 3A are applicable to the CPW 900.
[0104] The conductive elements 910 being shown in FIG. 9A with dashed lines illustrates the fact that they are provided below the surface of the signal line 906 and the ground planes 904/908. In some embodiments, such conductive elements may be provided at a distance d from the signal line, as is illustrated in FIG. 9C. In various embodiments, the depth d may be between 10 and 10,000 nanometers, including all values and ranges therein, e.g. between 100 and 500 nanometers or between 500 and 2,000 nanometers.
[0105] In various embodiments, quantum circuits with slow wave resonator structures with below- plane perpendicular conductive elements as described above with reference to FIGS. 9A-6C may be fabricated using any suitable fabrication techniques.
[0106] FIG. 10 provides a flow chart of a method 1000 for fabricating slow wave resonator structures with perpendicular conductive elements provided below the plane of a signal line, according to some embodiments of the present disclosure. Although the operations of the method 1000 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the method 1000 may be illustrated with reference to one or more of the embodiments discussed above, but the method 1000 may be used to manufacture any suitable quantum circuit component comprising one or more slow wave resonator structures with perpendicular conductive elements provided below the plane of a signal line according to any embodiments disclosed herein.
[0107] The method 1000 may begin with providing the perpendicular conductive elements, e.g. as described with reference to the conductive elements 910 above, over or in the surface of a substrate (process 1002 shown in FIG. 10). Discussions provided for the method 800 of FIG. 8 with respect to providing a signal line, ground plane(s) and perpendicular conductive elements in the plane of the signal line over a substrate in the process 802 of the method 800 are applicable to providing, now, only the conductive elements 910, and, therefore, are not repeated here. Discussions provided for the method 800 of FIG. 8 with respect to the substrate being used are also applicable to the method 1000 of FIG. 10 and are also not repeated.
[0108] Once the conductive elements are provided in the process 1002, the method may proceed with disposing a dielectric material over the conductive elements provided in the process 1002 (process 1004 shown in FIG. 10). That dielectric material will provide the distance d, illustrated in FIG. 9C, between the conductive elements 910 and the signal line 906. The dielectric material used in the process 1004 could be selected as any dielectric material suitable for undergoing further fabrication processing described herein. For example, etching properties of potential candidate materials may be to be considered when selecting a suitable material to be used for the dielectric material of the process 1004. Besides appropriate etching characteristics, some other
considerations in selecting a suitable material may include e.g. possibilities of smooth film formation, low shrinkage and outgassing, and good dielectric properties (such as e.g. low electrical leakage, suitable value of a dielectric constant, and thermal stability). Examples of dielectric materials that may be used as the dielectric material of the process 1004 include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.
[0109] In some embodiments, the dielectric material of the process 1004 may include an oxide deposited over the conductive elements formed in the process 1002 using e.g. chemical vapor deposition or/and plasma-enhanced chemical vapor deposition, as typically done in conventional processing. In still other embodiments, the dielectric material of the process 1004 may include a dielectric material formed over the conductive elements formed in the process 1002 using coating techniques involving cross-linking of liquid precursors into solid dielectric materials. In some embodiments, the surface of the conductive elements formed in the process 1002 may be cleaned or treated prior to applying the dielectric to reduce surface contamination and minimize interface traps and/or promote adhesion, for example using chemical or plasma clean, or applying heat in a controlled environment. In some embodiments, an "interface layer" may be applied between the conductive elements formed in the process 1002 and the dielectric material of the process 1004 to prevent, decrease, or minimize spontaneous and uncontrolled formation of other interfacial layers. In some embodiments, an adhesion promoter or adhesion layer may be applied prior to application of the dielectric.
[0110] In some embodiments, especially when the substrate is a Si or a SiGe substrate and the conductive elements were formed in the process 1002 using dopant implantation, the dielectric material provided in the process 1004 may be Si or SiGe grown over the substrate with the doped portion(s) forming the conductive elements of the future slow wave resonator structure using any of the atomic level growth techniques as known in the art, e.g. using epitaxial growth. Growth of Si or SiGe over the substrate with the doped portions forming the conductive elements results in the conductive elements being embedded (enclosed on all sides) within the substrate, i.e. being below the surface of the substrate but above the very bottom of the substrate.
[0111] The method 1000 may then proceed with providing a signal line and ground plane(s) over the dielectric formed in the process 1004 (process 1006 shown in FIG. 10), resulting in creation of a transmission line structure as described above, e.g. the signal line 906 and the ground planes 904/908. Discussions provided for the method 800 of FIG. 8 with respect to providing a signal line and ground plane(s) in the process 802 of the method 800 are applicable to providing the signal line and the ground planes in the process 1006 and, therefore, are not repeated here.
[0112] In some embodiments, the surface of the dielectric provided in the process 1004, in particular where the dielectric is an epitaxially grown semiconductor, may be processed prior to deposition of the signal line 906 and the ground planes 904/908 in order to improve quality of Si/superconductor or Si/conductor interface in terms of removal of any lossy native oxide layers followed by any deposition or treatment to change the chemical nature of the resulting Si surface. Such processing may include removal of the native oxide by using one or a combination of wet chemical fluorine etching solutions including but not limited to aqueous HF or aqueous NH*F or combinations thereof. Such processing may also include dry etching, for example using a plasma dry etch tool along with SF 6 , CF 4 , or NF 3 , or any combination thereof to remove native oxide followed by further in-situ or ex-situ processing which may include, but is not limited to, high temperature thermal treatments for times up to a few hours at temperatures up to 1400 C, exposure of the surface to hot gaseous vapor or plasmas containing chemicals such as N ¾ NH 3/ organic molecules, organosilicon molecules, metal precursors, etc., designed to create a chemically distinct transition region between the Si substrate and the superconducting film. Such processing may also be applied when the dielectric provided in the process 1004 is not Si.
[0113] The qubits are provided in the process 1008 shown in FIG. 8. Discussions provided for the method 800 of FIG. 8 with respect to providing the qubits in the process 804 are applicable to the process 1008 of the method 1000 and, therefore, are also not repeated.
[0114] Although not specifically shown in FIGS. 3A-3C, FIGS. 4A-4C, FIGS. 5A-5C, FIGS. 6A-6C, FIGS. 7A-7C, and FIGS. 9A-9C, the slow wave CPWs illustrated in these FIGS, may, optionally, be covered with a dielectric material which is a low-loss material in terms of spurious TLS's, with controlled interfaces between the conductive materials of the CPW (e.g. the signal line, the ground planes, and, for the embodiments of FIGS. 3A-3C, FIGS. 4A-4C, FIGS. 5A-5C, FIGS. 6A-6C, and FIGS. 7A-7C, also the conductive elements 310/410/510/610/710) and the cover dielectric material. Such encapsulation of the slow wave resonator structures in quantum circuits may help with reducing qubit
decoherence problems because it could eliminate superconductor-air interfaces above the conductive materials of the slow wave resonator structures. In some embodiments, the
encapsulation may be carried out as follows (not shown in FIGS.).
[0115] First, a layer of dielectric material, e.g. a suitable inter layer dielectric (ILD), is provided over structure with the slow wave resonator structure formed thereon. Considerations described above with reference to the dielectric material used in the process 1004 are applicable to the dielectric material used for the encapsulation and deposition thereof and, therefore, in the interest of brevity, are not repeated here. In some embodiments, the dielectric material used for the encapsulation may be the same as the dielectric material used in the process 1004. In other embodiments, these materials may be different. Optionally, planarization may be performed in order to achieve a relatively smooth, plane surface of the dielectric layer used for the encapsulation. A thickness of the dielectric layer used for the encapsulation could depend on e.g. the desired distance to the surface of the device from the signal line and ground planes of the slow wave resonator structure. For example, the dielectric layer used for the encapsulation may have a thickness between e.g. 20 and 3000 nm, including all values and ranges therein, typically for qubit applications between 50 and 100 nm.
[0116] Next, one or more first via openings are formed in the dielectric material used for the encapsulation to connect to the signal line and one or more second via openings are formed to connect to the ground planes of the slow wave resonator structure. Number, dimensions and a shape of the via openings could depend on e.g. the conductive/superconductive material used to fill the via openings, dimensions and shape of the ground planes and the signal line, and the etching process used to form these via openings. For example, in some embodiments, one via opening could be used as a first via opening and one via opening could be used as a second via opening. However, in other embodiments, any other number of first and second via openings, arranged in any location and in any shape/geometry as suitable for providing electrical interconnection to the signal line and the ground planes of the slow wave resonator structure may be used, all of which being within the scope of the present disclosure. The first and second via openings extend from the surface of the dielectric layer used for the encapsulation to the respective conductors of the slow wave resonator structure. The dielectric layer used for the encapsulation at least partially surrounds each of the via openings, isolating them from one another and from other openings that may be formed in that layer, both physically and electrically. In various embodiments, largest dimensions of the first and second via openings could be between 5 and 40 nm for both the x-axis and y-axis, including all values and ranges therein. In various embodiments, any kind of etching techniques, possibly techniques that involve etching in combination with patterning, e.g. patterning as described above, may be used to form the first and second via openings. In some embodiments, both the first and second via openings are formed in a single etching step. For example, once patterning has been done to expose portions of the underlying dielectric layer used for the encapsulation in a patterned mask that defines location and arrangement of future first and second vias, exposed portions of the underlying dielectric layer are then chemically etched.
[0117] The method may then proceed with filling the one or more first via openings and one or more second via openings in the dielectric layer used for the encapsulation with a conducting or superconducting material suitable to provide electrical connectivity to, respectively, the signal line and the ground planes of the slow wave resonator structure.
[0118] Each of the top views of FIGs. 3A, 4A, 5A, 6A, 7A, and 9A illustrates an example of a signal line of a resonator implemented as a substantially straight line. However, in other embodiments, the signal line could have any other shapes/geometries suitable for serving as a signal line conductor of a slow wave resonator structure, all of which shapes/geometries being within the scope of the present disclosure. For example, the signal line may have various shapes such as e.g. substantially straight line, a lines with bends (e.g. a wiggly line or a line comprising one or more loop portions), or any other configuration suitable for a particular quantum circuit design. In some embodiments, the ground plane structures would conform to the shape of the signal line in that the shortest distance between the signal line and the ground plane structures would be the same along the length of the signal line.
[0119] It should be noted that while FIGS. 3A-3C, FIGS. 4A-4C, FIGS. 5A-5C, FIGS. 6A-6C, FIGS. 7A-7C and FIGS. 9A-9C illustrate an example with only one signal line 306/406/506/606/706/906 formed within a transmission line structure of a slow wave resonator, explanations provided herein could easily be extended to embodiments where multiple such signal lines are formed, all of which are within the scope of the present disclosure. Furthermore, in various embodiments, the ground planes may either be connected to a single ground potential or these ground planes could be connected to individual reference potentials.
[0120] Still further, while FIGS. 3A, 4A, 5A, 6A, 7A and 9A illustrate periodic loading provided along the entire length of the CPW resonators shown (i.e. the substantially perpendicular conductive elements are provided, periodically, along the entire length L), in other embodiments, such periodic loading may be implemented only on a portion of a resonator (e.g. on a portion at one end of the resonator), leaving the other portion (i.e. the remaining portion, the portion at the other end of the resonator) without any periodic conductive elements. Using the periodic loading only in a part of a transmission line resonator, as opposite to using it along the entire length of a transmission line resonator may be advantageous in terms of losses at temperatures above absolute zero. For example, a quarter-wavelength resonator will have high current densities near its' shorted end and lower current densities at its' open end (i.e. the end that is capacitively or inductively coupled to another circuit element). By periodically loading the areas of the transmission line where the current densities are low, the impact of the periodic loading on the quality factor of the resonator (and consequently the coherence time) can be reduced. In various embodiments, a portion of the resonator implementing the periodic loading as described herein could be between 20% and 50% of the entire length L of the resonator, at one end of the resonator, with the remaining portion of the resonator being implemented without periodic loading.
[0121] Slow wave resonator structures as described herein could be particularly useful as a quantum circuit resonator 104 coupled to the one or more of the plurality of qubits 102, shown in FIG. 1. In various embodiments, such a resonator could be coupled to the one or more qubits 102 via capacitive or inductive coupling. The resonator could be a coupling resonator or a readout resonator. If the resonator is a coupling resonator, then it could be coupled to two or more qubits, thereby coupling two or more qubits so that a change of state of one qubit may cause a change of state of the other qubits. If the resonator is a readout resonator, then typically each qubit could have its own readout resonator (i.e. a given readout resonator would be coupled to only one qubit) so that a state of each qubit could be determined independently from other qubits.
[0122] At least portions of qubits could be advantageously provided within the same plane as the signal line 306/406/506/606/706/906. Providing the qubits in the plane of the signal line
306/406/506/606/706/906 may be particularly advantageous for the encapsulated slow wave resonator structures described above in that the qubits could then be encapsulated (i.e. hermetically sealed) by the upper dielectric used for the encapsulation on top and by the dielectric substrate on the bottom, eliminating or at least reducing interfaces of conductive/superconductive materials and air, which could be present if the qubits were not encapsulated.
[0123] The different views of the slow wave resonator structures with perpendicular conductive elements as described herein are shown in the FIGS, with precise right angles and straight lines, which does not reflect example real world process limitations which may cause the features to not look so ideal when any of the structures described above are examined using e.g. scanning electron microscopy (SEM) images or transmission electron miscroscope (TEM) images. In such images of real structures, possible processing defects could also be visible, such as e.g. tapered vias, occasional screw, edge, or combination dislocations within the crystalline region, occasional dislocation defects of single atoms or clusters of atoms.
[0124] FIGS. 11A-11B are top views of a wafer 1100 and dies 1102 that may be formed from the wafer 1100, according to some embodiments of the present disclosure. The dies 1102 may include any of the quantum circuits/devices disclosed herein, e.g., the quantum circuit 100, and may include any of the slow wave resonator structures described herein, such as e.g. the slow wave resonator structures shown in FIGS. 3A-3C, FIGS. 4A-4C, FIGS. 5A-5C, FIGS. 6A-6C, FIGS. 7A-7C and FIGS. 9A-9C, or any combinations of these slow wave resonator structures, or any further embodiments of these structures as described herein (e.g. with the periodic loading being implemented only on a portion of the length of the resonator and not on the entire resonator). The wafer 1100 may include semiconductor material and may include one or more dies 1102 having conventional and quantum circuit device elements formed on a surface of the wafer 1100. Each of the dies 1102 may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum circuit qubit device. After the fabrication of the semiconductor product is complete, the wafer 1100 may undergo a singulation process in which each of the dies 1102 is separated from one another to provide discrete "chips" of the semiconductor product A die 1102 may include one or more quantum circuits 100 and/or supporting circuitry to route electrical signals to the quantum circuits 100 (e.g., interconnects connected to the conductive contacts of the slow wave resonator structures described herein, and other conductive vias and lines), as well as any other IC components. In some embodiments, the wafer 1100 or the die 1102 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1102. For example, a memory array formed by multiple memory devices may be formed on a same die 1102 as a processing device (e.g., the processing device 2002 of FIG. 13) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array. [0125] FIG. 12 is a cross-sectional side view of a device assembly 1200 that may include any of the embodiments of the quantum circuits employing slow wave resonator structures disclosed herein. The device assembly 1200 includes a number of components disposed on a circuit board 1202. The device assembly 1200 may include components disposed on a first face 1240 of the circuit board 1202 and an opposing second face 1242 of the circuit board 1202; generally, components may be disposed on one or both faces 1240 and 1242.
[0126] In some embodiments, the circuit board 1202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1202. In other embodiments, the circuit board 1202 may be a package substrate or flexible board.
[0127] The IC device assembly 1200 illustrated in FIG. 12 includes a package-on-interposer structure 1236 coupled to the first face 1240 of the circuit board 1202 by coupling components 1216. The coupling components 1216 may electrically and mechanically couple the package-on-interposer structure 1236 to the circuit board 1202, and may include solder balls (as shown in FIG. 12), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
[0128] The package-on-interposer structure 1236 may include a package 1220 coupled to an interposer 1204 by coupling components 1218. The coupling components 1218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1216. Although a single package 1220 is shown in FIG. 12, multiple packages may be coupled to the interposer 1204; indeed, additional interposers may be coupled to the interposer 1204. The interposer 1204 may provide an intervening substrate used to bridge the circuit board 1202 and the package 1220. The package 1220 may be a quantum circuit device package as described herein, e.g. a package including the quantum circuit 100 with any of the slow wave resonator structures described herein, or a combination thereof, or may be a conventional IC package, for example. Generally, the interposer 1204 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 1204 may couple the package 1220 (e.g., a die) to a ball grid array (BGA) of the coupling components 1216 for coupling to the circuit board 1202. In the embodiment illustrated in FIG. 12, the package 1220 and the circuit board 1202 are attached to opposing sides of the interposer 1204; in other embodiments, the package 1220 and the circuit board 1202 may be attached to a same side of the interposer 1204. In some embodiments, three or more components may be interconnected by way of the interposer 1204.
[0129] The interposer 1204 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 1204 may include metal interconnects 1208 and vias 1210, including but not limited to through-silicon vias (TSVs) 1206. The interposer 1204 may further include embedded devices 1214, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1204. The package-on-interposer structure 1236 may take the form of any of the package-on-interposer structures known in the art.
[0130] The device assembly 1200 may include a package 1224 coupled to the first face 1240 of the circuit board 1202 by coupling components 1222. The coupling components 1222 may take the form of any of the embodiments discussed above with reference to the coupling components 1216, and the package 1224 may take the form of any of the embodiments discussed above with reference to the package 1220. The package 1224 may be a package including one or more quantum circuits with qubits as described herein or may be a conventional IC package, for example. In some embodiments, the package 1224 may take the form of any of the embodiments of the quantum circuit 100 with any of the slow wave resonator structures described herein.
[0131] The device assembly 1200 illustrated in FIG. 12 includes a package-on-package structure 1234 coupled to the second face 1242 of the circuit board 1202 by coupling components 1228. The package-on-package structure 1234 may include a package 1226 and a package 1232 coupled together by coupling components 1230 such that the package 1226 is disposed between the circuit board 1202 and the package 1232. The coupling components 1228 and 1230 may take the form of any of the embodiments of the coupling components 1216 discussed above, and the packages 1226 and 1232 may take the form of any of the embodiments of the package 1220 discussed above. Each of the packages 1226 and 1232 may be a qubit device package as described herein or may be a conventional IC package, for example. In some embodiments, one or both of the packages 1226 and 1232 may take the form of any of the embodiments of the quantum circuit 100 with any of the slow wave resonator structures described herein, or a combination thereof. [0132] FIG. 13 is a block diagram of an example quantum computing device 2000 that may include any of the quantum circuits with slow wave resonator structures disclosed herein. A number of components are illustrated in FIG. 13 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the quantum computing device 2000 may be attached to one or more printed circuit boards (e.g., a motherboard), and may be included in, or include, any of the quantum circuits with slow wave resonator structures described herein. In some embodiments, various ones of these components may be fabricated onto a single system-on- a-chip (SoC) die. Additionally, in various embodiments, the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 13, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components. For example, the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled. In another set of examples, the quantum computing device 2000 may not include an audio input device 2024 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2024 or audio output device 2008 may be coupled.
[0133] The quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices). The quantum processing device 2026 may include one or more of the quantum circuits 100 with slow wave resonator structures disclosed herein, and may perform data processing by performing operations on the qubits that may be generated in the quantum circuits 100, and monitoring the result of those operations. For example, as discussed above, different qubits may be allowed to interact, the quantum states of different qubits may be set or transformed, and the quantum states of different qubits may be read. The quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters.
[0134] As noted above, the processing device 2002 may include a non-quantum processing device 2028. In some embodiments, the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026. For example, the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc. The non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026. For example, the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components. The non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
[0135] The quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004. In some embodiments, the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).
[0136] The quantum computing device 2000 may include a cooling apparatus 2030. The cooling apparatus 2030 may maintain the quantum processing device 2026, in particular the quantum circuits 100 as described herein, at a predetermined low temperature during operation to avoid qubit decoherence and to reduce the effects of scattering in the quantum processing device 2026. This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less. In some embodiments, the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2030, and may instead operate at room temperature. The cooling apparatus 2030 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.
[0137] In some embodiments, the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
[0138] The communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for
Microwave Access, which is a certification mark for products that pass conformity and
interoperability tests for the IEEE 802.16 standards. The communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2012 may operate in accordance with other wireless protocols in other embodiments. The quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless
communications (such as AM or FM radio transmissions).
[0139] In some embodiments, the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2012 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.
[0140] The quantum computing device 2000 may include battery/power circuitry 2014. The battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).
[0141] The quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above). The display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
[0142] The quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). The audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
[0143] The quantum computing device 2000 may include an audio input device 2024 (or corresponding interface circuitry, as discussed above). The audio input device 2024 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
[0144] The quantum computing device 2000 may include a global positioning system (GPS) device 2018 (or corresponding interface circuitry, as discussed above). The GPS device 2018 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.
[0145] The quantum computing device 2000 may include an other output device 2010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
[0146] The quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader. [0147] The quantum computing device 2000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
[0148] The following paragraphs provide examples of various ones of the embodiments disclosed herein.
[0149] Example 1 provides a quantum integrated circuit assembly/device that includes a substrate, a plurality of qubits disposed over or in the substrate, and a resonator structure disposed over or in the substrate and associated with one or more of the plurality of qubits. The resonator structure includes a signal line, and a plurality of periodic conductive elements substantially perpendicular to the signal line provided, in various embodiments, along at least a portion of an entire length of the signal line, or along the entire length of the signal line.
[0150] Example 2 provides the quantum integrated circuit assembly according to Example 1, where the plurality of periodic conductive elements are below the signal line and are separated from the signal line by a dielectric material.
[0151] Example 3 provides the quantum integrated circuit assembly according to Example 2, where each conductive element of the plurality of periodic conductive elements includes a strip of an electrically conductive material.
[0152] Example 4 provides the quantum integrated circuit assembly according to Example 3, where the strip has a length between 1,000 and 100,000 nanometers.
[0153] Example 5 provides the quantum integrated circuit assembly according to Examples 3 or 4, where the strip has a width between 10 and 1,000 nanometers.
[0154] Example 6 provides the quantum integrated circuit assembly according to any one of Examples 3-5, where the strip has a thickness between 20 and 10,000 nanometers.
[0155] Example 7 provides the quantum integrated circuit assembly according to any one of Examples 2-6, where a period of the plurality of periodic conductive elements is between 20 and 2,000 nanometers.
[0156] Example 8 provides the quantum integrated circuit assembly according to any one of clams 2-7, where the plurality of periodic conductive elements is provided at a distance between 10 and 1,000 nanometers below the conductor strip. [0157] Example 9 provides the quantum integrated circuit assembly according to any one of clams 2-8, where the dielectric material separating the plurality of periodic conductive elements from the signal line includes epitaxial silicon.
[0158] Example 10 provides the quantum integrated circuit assembly according to Example 1, where the plurality of periodic conductive elements include periodic pairs of conductive elements, each pair including a first conductive element (a first stub) and a second conductive element (a second stub) extending from the signal line (i.e. the first and second elements are continuation of, or parts of, the signal line) in opposite directions.
[0159] Example 11 provides the quantum integrated circuit assembly according to Example 10, where, for each of the first and the second conductive elements, an end section of the conductive element (i.e. a part of the conductive element that is the farthest away from the signal line) is rounded.
[0160] Example 12 provides the quantum integrated circuit assembly according to Example 10, where the resonator structure is a coplanar waveguide further including a ground plane on each side of the signal line, and where a shape of a portion of the ground plane on each side of the signal line conforms to a shape of an end section of one of the first and the second conductive elements that is closest to said ground plane. In this manner, for a given stub that is closest to a given ground plane, the distance to the ground plane is the same for all points at an end of the stub, advantageously resulting in uniform distribution of electrical field and avoidance of "hot spots" of high value of electrical field near sharp edges or corners that would potentially increase loss.
[0161] Example 13 provides the quantum integrated circuit assembly according to Example 1, where the plurality of periodic conductive elements include periodic pairs of conductive elements, each pair including a first conductive element (a first stub) extending from a first ground plane of the resonator structure towards the signal line and a second conductive element (a second stub) extending from a second ground plane of the resonator structure towards the signal line opposite to the first conductive element (i.e. the first and second elements are continuation of, or parts of, the first and second ground planes, respectively, extending towards opposite sides of the signal line).
[0162] Example 14 provides the quantum integrated circuit assembly according to Example 13, where, for each of the first and the second conductive elements, an end section of the conductive element (i.e. a part of the conductive element that is the farthest away from the respective ground plane and closest to the signal line) is rounded.
[0163] Example 15 provides the quantum integrated circuit assembly according to Example 13, where a shape of a portion of the signal line on each side of the signal line conforms to a shape of an end section of one of the first and the second conductive elements that is closest to said portion. In this manner, for a given stub that extends from a given ground plane, the distance to the signal line is the same for all points at an end of the stub, advantageously resulting in uniform distribution of electrical field and avoidance of "hot spots" of high value of electrical field near sharp edges or corners that would potentially increase loss.
[0164] Example 16 provides the quantum integrated circuit assembly according to Example 1, where the plurality of periodic conductive elements includes periodic pairs of conductive elements. Each pair may include a first conductive element (a first stub) between the signal line and a first ground plane structure of the resonator structure, the first conductive element including a first interdigitated capacitor, and an opposite second conductive element (a second stub; provided opposite to the first stub) between the signal line and a second ground plane structure of the resonator structure (i.e. the first and second conductive elements/stubs are on the opposite sides of the signal line), the second conductive element including a second interdigitated capacitor.
[0165] Example 17 provides the quantum integrated circuit assembly according to Example 16, where the first conductive element includes a first portion extending from the signal line and a second portion extending from the first ground plane structure, the first and second portion of the first conductive element forming the first interdigitated capacitor, and the second conductive element includes a first portion extending from the signal line and a second portion extending from the second ground plane structure, the first and second portion of the second conductive element forming the second interdigitated capacitor.
[0166] Example 18 provides the quantum integrated circuit assembly according to any one of Examples 10-17, where each of the first and second conductive elements has a length between 1,000 and 100,000 nanometers.
[0167] Example 19 provides the quantum integrated circuit assembly according to any one of Examples 10-18, where each of the first and second conductive elements has a width between 10 and 1,000 nanometers.
[0168] Example 20 provides the quantum integrated circuit assembly according to any one of Examples 10-19, where each of the first and second conductive elements has a thickness between 20 and 10,000 nanometers. In some embodiments, the thickness of the first and second conductive elements may be the same as the thickness of the signal line/ground planes from which they extend. In other embodiments, the thickness of the first and second portions may be different from (e.g. smaller than) the thickness of the signal line/ground planes from which they extend.
[0169] Example 21 provides the quantum integrated circuit assembly according to any one of Examples 10-20, where a period of the periodic pairs of conductive elements is between 20 and 2,000 nanometers. [0170] Example 22 provides the quantum integrated circuit assembly according to any one of
Examples 1-21, where the resonator structure is a stripline transmission line.
[0171] Example 23 provides the quantum integrated circuit assembly according to any one of
Examples 1-21, where the resonator structure is a microstrip transmission line.
[0172] Example 24 provides the quantum integrated circuit assembly according to any one of
Examples 1-21, where the resonator structure is a coplanar waveguide transmission line.
[0173] Example 25 provides the quantum integrated circuit assembly according to any one of the preceding Examples, where the resonator structure is a quantum circuit resonator coupled to one or more of the plurality of qubits.
[0174] Example 26 provides the quantum integrated circuit assembly according to any one of the preceding Examples, further including one or more first interconnects for connecting the signal line to a signal source and one or more second interconnects for connecting at least one ground plane of the resonator structure to a ground potential.
[0175] Example 27 provides the quantum integrated circuit assembly according to any one of the preceding Examples, where each of the conductive elements includes one or more superconductive materials.
[0176] Example 28 provides the quantum integrated circuit assembly according to any one of the preceding Examples, where the signal line includes one or more superconductive materials.
[0177] Example 29 provides the quantum integrated circuit assembly according to Examples 27 or 28, where the one or more superconductive materials include one or more of aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (UN), or niobium titanium nitride (NbTiN).
[0178] Example 30 provides the quantum integrated circuit assembly according to any one of the preceding Examples, where the plurality of qubits includes a plurality of superconducting qubits.
[0179] Example 31 provides a method of manufacturing a quantum device. The method includes providing a signal line over or in a substrate; providing a plurality of periodic conductive elements substantially perpendicular to at least a portion of the signal line; and providing a plurality of qubits over or in the substrate, where the signal line and the plurality of periodic conductive elements form a resonator structure for one or more of the plurality of qubits.
[0180] Example 32 provides the method according to Example 31, where the substrate is a silicon substrate and where providing the signal line and/or providing the plurality of periodic conductive elements includes implanting dopants in a portion of a top layer of the substrate and activating the implanted dopants.
[0181] Example 33 provides the method according to Example 32, where the top layer of the substrate includes an uppermost layer of intrinsic or low-doped epitaxially grown silicon. [0182] Example 34 provides the method according to Example 33, where the uppermost layer includes silicon that is sufficiently pure to behave as a low-loss insulator at qubit operating temperatures.
[0183] Example 35 provides the method according to Examples 33 or 34, where the uppermost layer of intrinsic or low-doped epitaxially grown silicon includes isotopically enriched silicon.
[0184] Example 36 provides the method according to any one of Examples 33-35, where the uppermost layer has a thickness between 0.5 and 5 micrometers (microns).
[0185] Example 37 provides the method according to any one of Examples 31-36, where the plurality of periodic conductive elements are provided before providing the signal line and the method further includes epitaxially growing silicon on the top layer of the substrate after providing the plurality of periodic conductive elements and before providing the signal line.
[0186] Example 38 provides the method according to any one of Examples 31-37, further including providing one or more first interconnects for connecting the signal line to a signal source and one or more second interconnects for connecting at least one ground plane of the resonator structure to a ground potential.
[0187] Example 39 provides the method according to Example 38, where providing the one or more first interconnects or/and the one or more second interconnects includes providing interconnect openings in the substrate and depositing one or more electrically conductive materials within the interconnect openings.
[0188] Example 40 provides the method according to Example 38, where providing the one or more first interconnects or/and the one or more second interconnects includes implanting dopants in the substrate and activating the implanted dopants.
[0189] Example 41 provides the method according to any one of Examples 31-40, where the plurality of qubits include superconducting qubits and are provided over the substrate after the resonator structure is formed.
[0190] Example 42 provides a quantum computing device, including a quantum processing device and a non-quantum processing device coupled to the quantum processing device. The quantum processing device includes a substrate, a plurality of qubits disposed over or in the substrate, and a resonator structure disposed over or in the substrate and associated with one or more of the plurality of qubits, the resonator structure including a signal line and a plurality of periodic conductive elements substantially perpendicular to at least a portion of the signal line, provided, in various embodiments, along at least a portion of an entire length of the signal line, or along the entire length of the signal line. The quantum computing device further includes a memory device to store data generated by the plurality of qubits during operation of the quantum processing device. [0191] Example 43 provides the quantum computing device according to Example 42, further including a cooling apparatus configured to maintain a temperature of the quantum processing device below 5 degrees Kelvin.
[0192] Example 44 provides the quantum computing device according to Examples 42 or 43, where the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.
[0193] In further Examples, the quantum processing device of the quantum computing according to any one of Examples 42-44 may include a quantum integrated circuit assembly according to any one of the preceding Examples.
[0194] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.
[0195] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.