Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
RADIO FREQUENCE DIGITAL TO ANALOG CONVERTER (RF-DAC) UNIT CELL
Document Type and Number:
WIPO Patent Application WO/2021/206597
Kind Code:
A1
Abstract:
An RF-DAC unit cell. In one aspect, the unit cell has a configuration that reduces output capacitance and thus serves to extend the possible bandwidth. In another aspect, the unit cell has an organization that provides LO leakage compensation at the cell level which enables a low overall leakage at the converter level. Additionally, in another aspect, the unit cell employs a data storage circuit (e.g., a flip-flop) to ensure that only one timing-critical signal needs to be routed to all cells.

Inventors:
ÅBERG VICTOR (SE)
SVENSSON LARS (SE)
Application Number:
PCT/SE2020/050372
Publication Date:
October 14, 2021
Filing Date:
April 08, 2020
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
ERICSSON TELEFON AB L M (SE)
International Classes:
H03D7/14; H03M1/74; H04L27/36
Attorney, Agent or Firm:
ERICSSON AB (SE)
Download PDF:
Claims:
CLAIMS

1. A radio frequency digital to analog converter, RF-DAC, unit cell (500), the RF-DAC unit cell (500) comprising: a first data storage circuit (506); a second data storage circuit (508); a first bit multiplier (502) having: a first input terminal (561) for receiving a first RF signal (LO-); a second input terminal (562) for receiving a second RF signal (LO+); a third input terminal (582) connected to an output (581) of the first data storage circuit; a first output terminal (541) connected to a first RF output node (RF+); and a second output terminal (542) connected to a second RF output node (RF-); and a second bit multiplier (504) having: a first input terminal (571) for receiving the first RF signal (LO-); a second input terminal (572) for receiving the second RF signal (LO+); a third input terminal (592) connected to an output (591) of the second data storage circuit; a first output terminal (543) connected to the first RF output node (RF+); and a second output terminal (544) connected to the second RF output node (RF-).

2. The RF-DAC unit of claim 1, wherein the first bit multiplier further comprises a first switch (511), a second switch (512), and a third switch (521), each switch comprising a first terminal, a second terminal, and a third terminal, the first input terminal (561) of the first bit multiplier (502) is connected to the first terminal (e.g., gate) of the first switch (511), the second input terminal (562) of the first bit multiplier (502) is connected to the first terminal (e.g., gate) of the second switch (512), the third input terminal (582) of the first bit multiplier is connected to the first terminal (e.g., gate) of the third switch (521), and the third terminal of the first switch (511) is connected to the second terminal of the third switch (521).

3. The RF-DAC unit of claim 2, wherein the third terminal of the second switch (512) is connected to the second terminal of the third switch (521), and the third terminal of the third switch (521) is connected to ground.

4. The RF-DAC unit of claim 2, wherein the first bit multiplier further comprises a fourth switch (522), and the third input terminal (582) of the first bit multiplier is connected to the first terminal (e.g., gate) of the fourth switch (522).

5. The RF-DAC unit of claim 4, wherein the third terminal of the second switch (512) is connected to the second terminal of the fourth switch (522), the third terminal of the third switch (521) is connected to ground, and the third terminal of the fourth switch (522) is connected to ground.

6. The RF-DAC unit of any one of claims claim 1-5, wherein the first output terminal (541) of the first bit multiplier (502) is connected to the second terminal (e.g., drain) of the second switch (512), and the second output terminal (542) of the first bit multiplier (502) is connected to the second terminal (e.g., drain) of the first switch (511).

7. The RF-DAC unit of any one of claims 2-6, wherein the second bit multiplier further comprises a fifth switch (513), a sixth switch (514), and a seventh switch (524), each switch comprising a first terminal, a second terminal, and a third terminal, the first input terminal (571) of the second bit multiplier (504) is connected to the first terminal (e.g., gate) of the sixth switch (514), the second input terminal (572) of the second bit multiplier (504) is connected to the first terminal (e.g., gate) of the fifth switch (513), the third input terminal (592) of the second bit multiplier (504) is connected to the first terminal (e.g., gate) of the seventh switch (524), and the third terminal of the fifth switch (513) is connected to the second terminal of the seventh switch (524).

8. The RF-DAC unit of claim 7, wherein the first output terminal (543) of the second bit multiplier (504) is connected to the second terminal (e.g., drain) of the sixth switch (514), the second output terminal (544) of the second bit multiplier (504) is connected to the second terminal (e.g., drain) of the fifth switch (513), and the second bit multiplier further comprises an eighth switch (523), where the third input terminal (592) of the second bit multiplier (504) is connected to the first terminal (e.g., gate) of the eighth switch (523).

9. The RF-DAC unit cell of any one of claims 1-8, wherein the first data storage circuit (506) has a first input for receiving a clock signal (Cks) and a second input for receiving an output of a first logic circuit (551), and the second data storage circuit (508) has a first input for receiving the clock signal and a second input for receiving an output of a second logic circuit (552).

10. The RF-DAC unit cell of claim 9, wherein the first logic circuit has a first input for receiving a data signal and a second input for receiving a sign signal representing a sign of the data signal, and the second logic circuit has a first input for receiving the data signal and a second input for receiving an inverted sign signal.

11. The RF-DAC unit cell of any one of claims 1-10, wherein each said switch is a transistor.

12. A radio frequency digital to analog converter, RF-DAC, unit cell (500), the RF- DAC unit cell comprising: a first bit multiplier (502) having: a first input terminal (561) for receiving a first RF signal (LO-); a second input terminal (562) for receiving a second RF signal (LO+); a third input terminal (582) for receiving a data signal; a first output terminal (541) connected to a first RF output node (RF+); and a second output terminal (542) connected to a second RF output node (RF-); and a second bit multiplier (504) having: a first input terminal (571) for receiving the first RF signal (LO-); a second input terminal (572) for receiving the second RF signal (LO+); a third input terminal (592) for receiving the data signal; a first output terminal (543) connected to the first RF output node (RF+); and a second output terminal (544) connected to the second RF output node (RF-), wherein the first bit multiplier (502) further comprises a first switch (511), a second switch (512), and a third switch (521), each switch comprising a first terminal, a second terminal, and a third terminal, the first input terminal (561) of the first bit multiplier (502) is connected to the first terminal (e.g., gate) of the first switch (511), the second input terminal (562) of the first bit multiplier (502) is connected to the first terminal (e.g., gate) of the second switch (512), the third input terminal (582) of the first bit multiplier is connected to the first terminal (e.g., gate) of the third switch (521), the first output terminal (541) of the first bit multiplier (502) is connected to the second terminal (e.g., drain) of the second switch (512), the second output terminal (542) of the first bit multiplier (502) is connected to the second terminal (e.g., drain) of the first switch (511), the second bit multiplier (504) further comprises a fifth switch (513), a sixth switch (514), and a seventh switch (523), each switch comprising a first terminal, a second terminal, and a third terminal, the first input terminal (571) of the second bit multiplier (504) is connected to the first terminal (e.g., gate) of the sixth switch (514), the second input terminal (572) of the second bit multiplier (504) is connected to the first terminal (e.g., gate) of the fifth switch (513), the third input terminal (592) of the second bit multiplier (504) is connected to the first terminal (e.g., gate) of the seventh switch (523), the first output terminal (543) of the second bit multiplier (504) is connected to the second terminal (e.g., drain) of the sixth switch (514), and the second output terminal (544) of the second bit multiplier (504) is connected to the second terminal (e.g., drain) of the fifth switch (513).

13. The RF-DAC unit of claim 12, wherein the third terminal of the second switch (512) is connected to the second terminal of the third switch (521), and the third terminal of the third switch (521) is connected to ground.

14. The RF-DAC unit of claim 12, wherein the first bit multiplier further comprises a fourth switch (522), and the third input terminal (582) of the first bit multiplier is connected to the first terminal (e.g., gate) of the fourth switch (522).

15. The RF-DAC unit of claim 14, wherein the third terminal of the second switch (512) is connected to the second terminal of the fourth switch (522), the third terminal of the third switch (521) is connected to ground, and the third terminal of the fourth switch (522) is connected to ground.

16. The RF-DAC unit cell of any one of claims 12-15, wherein the RF-DAC unit further comprises: a first data storage circuit (506); and a second data storage circuit (508), wherein the third input terminal of the first bit multiplier is connected to an output of the first data storage circuit, and the third input terminal of the second bit multiplier is connected to an output of the second data storage circuit.

17. The RF-DAC unit cell of claim 16, wherein the first data storage circuit has a first input for receiving a clock signal and a second input for receiving an output of a first logic circuit (e.g., AND gate), and the second data storage circuit has a first input for receiving the clock signal and a second input for receiving an output of a second logic circuit (e.g., AND gate).

18. The RFDAC unit cell of claim 17, wherein the first logic circuit has a first input for receiving a data signal and a second input for receiving a sign signal representing a sign of the data signal, and the second logic circuit has a first input for receiving the data signal and a second input for receiving an inverted sign signal.

19. The RFDAC unit cell of any one of claims 12-18, wherein each said switch is a transistor.

20. The RF-DAC unit cell of any one of claims 1-11 or 16-19, wherein the first data storage circuit is a flip-flop; and the second data storage circuit is a flip-flop.

Description:
RADIO FREQUENCE DIGITAL TO ANALOG CONVERTER (RF-DAC) UNIT CELL

TECHNICAL FIELD

[001] Disclosed are embodiments related to RF-DACs.

BACKGROUND

[002] RF-DACs are used to modulate high-frequency RF signals, most commonly in communication systems (see, e.g., reference [11]). An RF-DAC multiplies an RF signal by a digital data value. Bandwidth-efficient modulation formats require the multiplication to allow signed data; a negative multiplier would then result in an output value with the opposite phase from that of positive values.

[003] In a typical use of the RF-DAC, the signal to be modulated would be provided by a local oscillator (LO). For simplicity, this usage will be assumed in the following, but is not strictly necessary. The LO signal may be phase modulated as for a polar transmitter or it may be an unmodulated signal used in a quadrature arrangement; without restriction, the latter case is assumed in this disclosure. The typical RF-DAC is built from a collection of unit cells.

SUMMARY

[001] The unit cells of an RF-DAC contain one or more bit multipliers. In one configuration, all the bit multiplier outputs are wired together and connected to a load impedance such as a transformer or a balun. The fraction of bit multipliers activated then determines the RF level at the output of the DAC.

[002] It is desirable for an RF-DAC to have a high modulation bandwidth. A high modulation bandwidth, however, necessitates a large analog bandwidth at the output summing port, and this is difficult to achieve at high resolutions as many unit cells are connected to the same output port, each contributing to the capacitance at that port. It is also desirable that a data bit value of 0 should result in no current being delivered into the summing port. In practice, some “LO leakage” is inevitable — the two phases of the LO signal are not perfectly balanced, and the devices are not perfectly matched — but system requirements demand that leakage be minimized. Furthermore, it is also desirable to reduce timing inaccuracies because timing inaccuracies in (de)activation of unit currents may cause output glitches which distort the output signal and limit the possible switching speed.

[003] This disclosure describes an RF-DAC unit cell that has one or more of the desirable properties mentioned above. In one aspect, the unit cell has a configuration that reduces output capacitance and thus serves to extend the possible bandwidth. In another aspect, the unit cell has an organization that provides LO leakage compensation at the cell level which enables a low overall leakage at the converter level. Additionally, in another aspect, the unit cell employs flip-flops (e.g., D-type flip-flops) to ensure that only one timing-critical signal needs to be routed to all cells.

[004] In one embodiment, the RF-DAC unit comprises a first data storage circuit (e.g., a first flip-flop); a second data storage circuit (e.g., a second flip-flop); a first bit multiplier; and a second bit multiplier. The first bit multiplier has: a first input terminal for receiving a first RF signal (LO-); a second input terminal for receiving a second RF signal (LO+); a third input terminal connected to an output of the first data storage circuit; a first output terminal connected to a first RF output node (RF+); and a second output terminal connected to a second RF output node (RF-). The second bit multiplier has a first input terminal for receiving the first RF signal (LO-); a second input terminal for receiving the second RF signal (LO+); a third input terminal connected to an output of the second data storage circuit; a first output terminal connected to the first RF output node (RF+); and a second output terminal connected to the second RF output node (RF-).

[005] In some embodiments, the first bit multiplier further comprises a first switch, a second switch, and a third switch, each switch comprising a first terminal, a second terminal, and a third terminal, the first input terminal of the first bit multiplier is connected to the first terminal (e.g., gate) of the first switch, the second input terminal of the first bit multiplier is connected to the first terminal (e.g., gate) of the second switch, the third input terminal of the first bit multiplier is connected to the first terminal (e.g., gate) of the third switch, and the third terminal of the first switch is connected to the second terminal of the third switch. In some embodiments, the third terminal of the second switch is connected to the second terminal of the third switch, and the third terminal of the third switch is connected to ground. In other embodiments, the first bit multiplier further comprises a fourth switch, and the third input terminal of the first bit multiplier is connected to the first terminal (e.g., gate) of the fourth switch. In some embodiments, the third terminal of the second switch is connected to the second terminal of the fourth switch, the third terminal of the third switch is connected to ground, and the third terminal of the fourth switch is connected to ground. In some embodiments, the second bit multiplier also comprises four switches, giving a total of eight switches for the unit cell.

[006] In some embodiments, the first output terminal of the first bit multiplier is connected to the second terminal (e.g., drain) of the second switch, and the second output terminal of the first bit multiplier is connected to the second terminal (e.g., drain) of the first switch.

[007] In some embodiments, the second bit multiplier further comprises a fifth switch, a sixth switch, and a seventh switch, each switch comprising a first terminal, a second terminal, and a third terminal, the first input terminal of the second bit multiplier is connected to the first terminal (e.g., gate) of the sixth switch, the second input terminal of the second bit multiplier is connected to the first terminal (e.g., gate) of the fifth switch, the third input terminal of the second bit multiplier is connected to the first terminal (e.g., gate) of the seventh switch, and the third terminal of the fifth switch is connected to the second terminal of the seventh switch. In some embodiments, the first output terminal of the second bit multiplier is connected to the second terminal (e.g., drain) of the sixth switch, and the second output terminal of the second bit multiplier is connected to the second terminal (e.g., drain) of the fifth switch. In some embodiments, the second bit multiplier further comprises an eighth switch. In some embodiments, the third terminal of the sixth switch is connected to the second terminal of the eighth switch, the third terminal of the seventh switch is connected to ground, and the third terminal of the eighth switch is connected to ground.

[008] In some embodiments, the first data storage circuit has a first input for receiving a clock signal (Cks) and a second input for receiving an output of a first logic circuit (e.g.,

AND gate), and the second data storage circuit has a first input for receiving the clock signal and a second input for receiving an output of a second logic circuit. In some embodiments, the first logic circuit has a first input for receiving a data signal and a second input for receiving a sign signal representing a sign of the data signal, and the second logic circuit has a first input for receiving the data signal and a second input for receiving an inverted sign signal.

[009] In some embodiments, each said switch is a transistor (e.g., CMOS transistor).

[0010] In another aspect an RF-DAC unit cell is provided that comprises a first bit multiplier having: a first input terminal for receiving a first RF signal (LO-); a second input terminal for receiving a second RF signal (LO+); a third input terminal for receiving a data signal; a first output terminal connected to a first RF output node (RF+); and a second output terminal connected to a second RF output node (RF-); and a second bit multiplier having: a first input terminal for receiving the first RF signal (LO-); a second input terminal for receiving the second RF signal (LO+); a third input terminal for receiving the data signal; a first output terminal connected to the first RF output node (RF+); and a second output terminal connected to the second RF output node (RF-). The first bit multiplier further comprises a first switch, a second switch, and a third switch, each switch comprising a first terminal, a second terminal, and a third terminal. The first input terminal of the first bit multiplier is connected to the first terminal (e.g., gate) of the first switch. The second input terminal of the first bit multiplier is connected to the first terminal (e.g., gate) of the second switch. The third input terminal of the first bit multiplier is connected to the first terminal (e.g., gate) of the third switch. The first output terminal of the first bit multiplier is connected to the second terminal (e.g., drain) of the second switch. The second output terminal of the first bit multiplier is connected to the second terminal (e.g., drain) of the first switch, the second bit multiplier further comprises a fifth switch, a sixth switch, and a seventh switch, each switch comprising a first terminal, a second terminal, and a third terminal. The first input terminal of the second bit multiplier is connected to the first terminal (e.g., gate) of the sixth switch. The second input terminal of the second bit multiplier is connected to the first terminal (e.g., gate) of the fifth switch. The third input terminal of the second bit multiplier is connected to the first terminal (e.g., gate) of the seventh switch. The first output terminal of the second bit multiplier is connected to the second terminal (e.g., drain) of the sixth switch. And the second output terminal of the second bit multiplier is connected to the second terminal (e.g., drain) of the fifth switch. [0011] In some embodiments the third terminal of the second switch is connected to the second terminal of the third switch, and the third terminal of the third switch is connected to ground.

[0012] In some embodiments the first bit multiplier further comprises a fourth switch, and the third input terminal of the first bit multiplier is connected to the first terminal (e.g., gate) of the fourth switch. In some embodiments the third terminal of the second switch is connected to the second terminal of the fourth switch, the third terminal of the third switch is connected to ground, and the third terminal of the fourth switch is connected to ground.

[0013] In some embodiments the RF-DAC unit further comprises: a first data storage circuit; and a second data storage circuit, wherein the third input terminal of the first bit multiplier is connected to an output of the first data storage circuit, and the third input terminal of the second bit multiplier is connected to an output of the second data storage circuit. In some embodiments the first data storage circuit has a first input for receiving a clock signal and a second input for receiving an output of a first logic circuit (e.g., AND gate), and the second data storage circuit has a first input for receiving the clock signal and a second input for receiving an output of a second logic circuit (e.g., AND gate). In some embodiments the first logic circuit has a first input for receiving a data signal and a second input for receiving a sign signal representing a sign of the data signal, and the second logic circuit has a first input for receiving the data signal and a second input for receiving an inverted sign signal.

[0014] In some embodiments the first data storage circuit is a first Flip-Flop (e.g., D-

Type); and the second data storage circuit is a second Flip-Flop (e.g., D-Type).

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various embodiments.

[0016] FIG. 1 illustrates an RF-DAC according to one embodiment.

[0017] FIG. 2 illustrates an RF-DAC according to another embodiment.

[0018] FIG. 3 illustrates an RF-DAC according to another embodiment.

[0019] FIG. 4 illustrates an RF-DAC according to another embodiment. [0020] FIG. 5 illustrates an RF-DAC unit cell according to one embodiment.

[0021] FIG. 6 illustrates an RF-DAC unit cell according to one embodiment.

[0022] FIG. 7 is a block diagram of a Cartesian RF IQ-modulator.

[0023] FIG. 8 illustrates an example floor plan.

[0024] FIG. 9 is a schematic of an LO generation chain.

[0025] FIG. 10A is a graph illustrating some results.

[0026] FIG. 10B is a graph illustrating some results.

[0027] FIG. 11 shows EVM for different signals at various data rates.

[0028] FIG. 12 illustrates power spectral density for a 32-QAM signal.

[0029] FIGs. 13 A- 13F are constellation diagrams.

DETAILED DESCRIPTION

[0030] Four different examples of modulator (RF-DAC) topologies are shown in FIGs. 1-

4.

[0031] FIG. 1 show's a binary sealed modulator (RF-DAC) 100 where a set of unit cells

199 are grouped into binary weighted groups. XI, X2, and X4 indicates the number of unit cells connected in parallel in each group. Each group is connected to its own data signal (Di) corresponding to one bit in the binary control word. In the embodiment shown, a common control signal (S) is used to control the sign of each unit cell 199.

[0032] A thermometer based modulator 200 is shown in FIG. 2. This structure is based on having individual control signals to each unit cell 299, activating the number of unit cells needed for a specific output code. In this case no grouping exists. Flowever, to convert the binary data to the thermometer control signals, a binary to thermometer encoder (not shown) will be needed. In the embodiment shown, a common control signal (S) is used to control the sign of each unit cell 299.

[0033] [0034] FIG. 3 shows a binary scaled modulator 300 according to another embodiment.

This embodiment has the same arrangement of unit cells 199 as shown in FIG. 1, but the embodiment of FIG. 3 employs individual sign control signals (S0, S1, S2, ...) for each unit cell group 199, thereby enabling more configuration freedom.

[0035] FIG. 4 shows a thermometer based modulator 400 according to another embodiment. This embodiment has the same arrangement of unit cells 299 as shown in FIG. 2, but the embodiment of FIG. 4 employs individual sign control signals (S0, S1, S2, ...) for each unit cell 299, thereby enabling more configuration freedom.

[0036] FIG. 5 illustrates an RF-DAC unit cell 500 according to one embodiment. The cell 500 contains a first balanced hit multiplier 502 and a second balanced hit multiplier 504. Multiplier 502 inciudes two LO switches 511 and 512 and two data switches 521 and 522. Likewise, multiplier 504 includes two LO swatches 513 and 514 and two data swatches 523 and 524. As shown in FIG. 5, each LO switch 511-514 and each data switch 521-524 is a transistor (e.g., a CMOS transistor in the embodiment shown). As further shown, switches 511 and 521 are connected in series - - i.e., in this embodiment, the source of transistor 51 1 is connected to the drain of switch 521. Likewise, switches 512 and 522 are connected in series, switches 513 and 523 are connected in series, and switches 514 and 524 are connected in series.

[0037] The first multiplier 502 is controlled by a first data storage circuit 506 (which in this example is a first flip-flop (FF) (e.g., D-type)), and second multiplier 504 is controlled by a second data storage circuit 508 (wTsich in this example is a second flip-flop (FF) (e.g., D- type)). Output 581 of FF 506 is connected to input terminal 582 of multiplier 502, and output 591 of FF 508 is connected to input terminal 592 of multiplier 504. Input terminal 582 is connected to the gate of data switch 521 and the gate of data switch 522, Input terminal 592 is connected to the gate of data switch 523 and the gate of data switch 524. The sources of data switches 521-124 are each connected to ground.

[0038] A balanced input RF signal (LO- and LO+) is connected with opposite phases to the hit multipliers, such that any signal level difference between LO+ and LO- is cancelled at the RF+ and RF- outputs. More specifically, in the embodiment shown in FIG. 5, input terminal 561 of multiplier 502 receives a first RF signal (LO-) and input terminal 562 of multiplier 502 receives a second RF signal (LO+). As further shown, input terminal 561 is connected to the gate of switch 511 (hence, switch 511 is referred to as an LO switch) and input terminal 562 is connected to the gate of switch 512. Likewise, input terminal 571 of multiplier 504 receives the first RF signal (LO-) and input terminal 572 of multiplier receives the second RF signal (LO+). As further shown, input terminal 571 is connected to the gate of switch 514 and input terminal 572 is connected to the gate of switch 513.

[0039] Only one of the two multipliers 502 and 504 would be active at any one time, depending on a signal S. It is assumed that the input data Di for the two bit multipliers are identical, as would be the case when S is the sign bit in a sign-magnitude representation of the data; this is a beneficial but not a necessary arrangement. Unless the data bit D; is set, neither of the two bit multipliers is active. More specifically, in the embodiment shown in FIG. 5, a firstlogic circuit 551 (e.g,. a first AND gate) receives Di and S as input and the output of logic circuit 551 is fed into the data input of FF 506. Similarly, a second logic circuit 552 (e.g., a second AND gate) receives Di and the inverse of S as input and the output of logic circuit 552 is fed into the data input of FF 508.

[0040] Unit Cell Stack Configuration

[0041] In one embodiment, the LO switches 511-114 are connected to the DAC output

(i.e., RF+ and RF- terminals). More specifically, the drain of switch 512 is connected to output terminal 541 which is connected to the RF+ terminal, the drain of switch 514 is connected to output terminal 543 which is connected to the RF÷ terminal, the drain of switch 511 is connected to output terminal 542 which is connected to the RF- terminal, and the drain of switch 513 is connected to output terminal 544 which is connected to the RF- terminal. . In some embodiments, the width of the LO switches 511-514 are chosen to achieve desired RF signal properties such as gain, current swing, and output and input impedances at the LO frequency. In one embodiment the LO switches 511.-51.4 have a width of 5 micrometers (tim), In one embodiment, the data switches 521.-524 are wider than the LO switches, so as to closer approximate ideal switches that would not influence the RF properties. For example, in on embodiment, the width of the data switches 521-524 is 8 um. The narrower LO switches present a smaller capacitance when connected directly to the DAC output, and thus enable a higher bandwidth when other parameters are unchanged,

[0042] Unit Cell Organization

[0043] Unit cell 500 provides cancellation of the LQ leakage at the cell level, thus counteracting the leakage increase caused by the stack configuration. As described above, unit cell 500 contains two balanced bit multipliers, at most one of which is active at any time. The bit multipliers are wired together at the unit cell output in such a way that their current contributions have opposite signs. Thus, any leakage caused by imbalance of the two LO phases contributes equally to both RF+ and RF- and is therefore cancelled out. It is not necessary for RF+ and RF- to be true inverses for the benefits to occur; therefore unit call 500 is usable also with n on- sinusoidal signals, as may facilitate combining of I- and Q-channels (see, e.g., reference [12]).

[0044] Data Switch Timing

[0045] The data switches 521-124 of unit cell 500 are controlled by logic signals, which need to be routed individually to each unit cell, resulting in different and data-dependent arrival times across a collection of cells. In unit cell 500, the control signals for the data switches are provided from individual flip-flops 506 and 508 located with each bit multiplier. The timing of the data-s witch control voltages is therefore derived only from the clock signal (Ck s ), a single signal common for the entire RF-DAC which may therefore more easily be distributed for simultaneous arrival at each cell. This improved timing precision serves to increase the possible sample rate of the RF-DAC, which is needed to be able to maximize the usable bandwidth.

[0046] FIG. 6 illustrates an RF-DAC unit cell 600 according to another embodiment.

Unit cell 600 contains a first balanced bit multiplier 602 and a second balanced bit multiplier 604. Unit cell 600 is identical to unit cell 500 with the exception that multiplier 602 does not include switch 522 (i.e., multiplier 602 comprises the two LO switches 511 and 512 but just the one data switch 521, instead of the two data switches 521 and 522). Likewise, multiplier 604 does not include the data switch 524. As shown in FIG. 6, the source of switches 511 and 512 are connected to the drain of switch 521, and the source of switch 521 is connected to ground. Likewise, the source of switches 513 and 514 are connected to the drain of switch 524, and the source of switch 524 is connected to ground. In some embodiments, the size of data switches 521 and 524 of unit cell 600 may have a different size than the size of data switches 521 and 524 of unit cell 500.

[0047] Cartesian RF IQ-modulator

[0048] Described below is a Cartesian RF IQ-modulator that is based on the unit cell topology disclosed herein.

[0049] I. INTRODUCTION

[0050] The continuously increasing demand for higher data rates pushes the need for increased spectral resources. The limited spectral resources available in the sub-6GHz bands, therefore, drive the exploration of higher carrier frequencies. The newly-introduced fifth generation (5G) mobile communication standard introduces millimeter-wave (mm-wave) bands in frequency range 2 (FR2) [1], allowing multi-Gb/s communication. Active antennas are an important part in realizing 5G. The combination of high data rates and small antenna separation at mm-wave frequencies make highly integrated CMOS the most suitable implementation option. [0051] CMOS integration of RF-DACs are a promising alternative for mm-wave 5G transmitter realizations. These operate to a large extent in switching mode, thereby making them suitable for CMOS integration [2], For complex modulation formats such as M-QAM, RF-DACs can be used in either a polar or a Cartesian configuration. In the polar configuration, the carrier is first modulated with the phase information before the amplitude modulation is applied through an RF-DAC. Then, the phase and amplitude signals needs to be synced to sub-sample precision in order to achieve good performance [3], which is very challenging for wideband signals. The Cartesian IQ-modulator on the other hand uses two RF-DACs, operating in parallel with 90° phase offset to generate the I- and Q-components. However, combining these two components without power loss and artefacts is complex.

[0052] Although the 3 dB vector summing penalty, caused by direct RF summation of the two components, in many cases seems to be acceptable in Cartesian IQ-modulators, several methods can provide isolated summing of these two components. A fully isolated combiner can be used to combine the two components without interference, at the cost of additional loss and area. An alternative to combiners is to use non-overlapping sub-50% duty-cycle LO signals to drive the RF-DACs, which has been demonstrated with good results in the low-GHz range [4], [0053] RF-DACs have been demonstrated to operate in a large set of frequency bands, ranging from a few GHz to 60 GHz and beyond [2]-[7], In [5], a 2x6 bit RF IQ-modulator operating at 20-32GHz with a sample rate of 5GS/s is described. A 2x lObit, 20-32GHz RF IQ- modulator, clocked at 2GHz is described in [2], A 4 bit polar modulator operating at 60 GHz is demonstrated in [3], The amplitude modulator is clocked at 10GHz, while the analog phase modulation is fed to the chip. A 2x9 bit RF-IQ modulator operating at 85-95 GHz and clocked at 15 GHz is demonstrated in [6], This IQ-modulator is however only verified by toggling the MSB. A 2x2bit RF-IQ modulator operating at 94 GHz, and clocked at 20 GHz is demonstrated in [7], [0054] In this disclosure, we present a 2x6bit Cartesian based RF IQ-modulator operating from 17-24GHz, clocked at 8GHz. The modulator uses a novel LO neutralization technique at unit cell level to mitigate LO leakage. Sub-50 % duty-cycle LO signals are used to reduce the effects of interference between the I- and Q-branch. The core focus has been to maximize the sample rate, and thereby the reachable bandwidth and/or the achievable oversampling ratio.

[0055] II. RF IQ-MODULATOR DESIGN

[0056] A block diagram of the RF IQ-modulator designed to evaluate our proposed unit cell topology is shown in Fig. 7. A LO at double the RF frequency, is used to generate the orthogonal LOs needed to drive the RF IQ-modulator. Inverter-based buffers are placed between the divider and the RF IQ-modulator to provide the desired drive strength. The digital control signals are fed from an on-chip 16 kS memory.

[0057] The RF IQ-modulator design will be described in detail, starting at the bottom with the unit cell design, followed by the RF IQ-modulator core, the design of the LO generation, and the memory block.

[0058] A. Unit cell

[0059] An important factor when designing RF-DACs is how transistors are placed at cell level. Many RF-DACs presented in literature generate the amplitude modulation through bitwise cancellation, constantly keeping all cells active [5], [8], LO leakage cancellation can be achieved through individual biasing of the differential switches [8], Gating the top-placed data switch, has been demonstrated not only to reduce leakage but also to reduce the bias current [2], [9], Also gating the LO signal with the data signal, thereby deactivating both stages of the cascode [2], has been observed to further reduce leakage, however potentially at the cost of peak performance. The LO switches would be sized for the desired output power while the data switches are slightly larger to increase efficiency. Placing the data switches on top would thereby increase the capacitive load at the output, limiting the output bandwidth.

[0060] We here present unit cell topology, shown in Fig. 5 and Fig. 6, that combines the sign generation and LO leakage neutralization. The topology also brings a bias current reduction as the mixer bias current is cut when the cell is not in use. Two balanced mixers with the LO switches placed on top are used to generate signed outputs from the cell, making it capable of producing three levels [-1, 0, 1], The LO switches are 5 μm wide and the data switches are 8 μm wide, both using minimum transistor length. The sign generating, opposite polarity LO switch pairs, also helps cancel the LO leakage, bringing inherent LO leakage neutralization at cell-level. The unit cell features internal flip-flops that reduced data switching skew, thereby allowing for higher data switching rates.

[0061] B. RF IQ-modulator core

[0062] The floor plan of the RF IQ-modulator is shown in Fig. 8. The unit cells are distributed over a large area, making delay matching of LO and RF paths important for optimum combining of the unit-cell outputs. Distributing the LO and collecting the RF signal is done through two mirrored ‘F’ shaped nets, giving equal delay for all cells from LO input to RF output. A common-centroid placement scheme has been chosen, with MSBs placed around the edges and the LSBs in the middle, as can also be seen in Fig. 8.

[0063] The sample clock is fed into the middle of the DAC core before being distributed to all unit cells using a H-tree. The balance in the clock-tree is further improved by using dummy loads at the locations where no unit cells are connected, thereby reducing the clock skew.

[0064] C. Quadrature LO generation

[0065] For the LO generation we have chosen to use two cross-coupled CML latches, dividing a LO at double the RF frequency into the 0° and 90° LOs needed to drive the RF IQ- modulator. This topology gives us the possibility to generate non-overlapping 25% LO signals, allowing us to directly sum the RF currents. Fig. 9 shows a schematic of the two CML latches and four 17 inverter buffers. The buffers use 1 μm wide transistors in the first stage and 8x25 μm wide transistors in the two last stages, using NMOS and PMOS transistors of equal size. The large number of inverters used in the buffers are needed to increase the drive strength while maintaining the narrow pulses. Equally sized inverters in the last two stages further sharpen the transition rates, giving more well-defined pulses.

[0066] DC-block capacitors are placed both at the input and output of the inverter buffer.

These allow free tuning of the bias not only in the RF IQ-modulator but also at the input of the buffer chain. Adjusting the bias at the buffer input changes the duty-cycle of the LO signals, making it possible to achieve 25-50 % duty-cycle.

[0067] D. Memory

[0068] To test the design, modulated data needs to be sent to the RF IQ-modulator at high rate. For a 2><6bit resolution, operating at 8GS/s, a total of 96Gb/s needs to be sent to the IQ-modulator. An on-chip memory has been used to keep the high bandwidth within the chip. The SRAM-based memory stores 1024words, each containing 16S, which are then serialized in order to achieve the desired data rate. A low-speed serial interface is used to program the memory.

[0069] III. EXPERIMENTAL RESULTS

[0070] The design has been implemented and fabricated using GlobalFoundries 22nm fully depleted SOI CMOS process. The entire design measures 1.18 mm by 1.0 mm, out of which the core including baluns occupy 225 μm by 650 μm. The LO generation and RF IQ- modulator alone only occupy 225μm by 190 μm. The fabricated chip has been evaluated both using static and modulated measurements, performed with on-chip power calibration.

[0071] The divider and LO generation consumes 330mA from a IV supply, independent of output signal. The clock and data distribution in the IQ-modulator consume a maximum of 20mA from a 0.925V supply. However, this power consumption is highly dependent on the clock rate and the transmitted signal. The RF IQ-modulator has been evaluated upto 8 GS/s, being limited by the speed of the memory.

[0072] The tuning range for the divider and buffer chains has been smaller than expected, limiting the possibility to explore the non-overlapping duty-cycle. The true performance of the LO leakage cancellation at unit cell level has not been possible to verify due to LO leakage caused by the DAC-level routing. The source of the leakage has been verified with simulations and is in the order of one LSB, making is possible to digitally compensate for. [0073] A. Static Measurements

[0074] The static properties of the RF IQ-modulator has been evaluated using two methods. In both cases, a Keysight PNA-X network analyzer was used for the measurements. [0075] The analog bandwidth has been measured with all IQ-modulator cells being active; the result is shown in Fig. 10A. The RF IQ-modulator is functional in the range 17-25GHz and has a 3dB bandwidth of 17-24GHz. Proper function is defined as when the IQ-modulator is capable of producing a narrow-band 16-QAM signal; a larger range is possible in CW mode. The peak saturated output power is 10.4dBm, while consuming 78mA from a 0.9V supply, giving a drain efficiency of 15.6 %. During the measurement, the bias at the buffer inputs was adjusted for a constant IQ-phase imbalance.

[0076] The output power and phase has also been measured for all combinations of I and

Q; the results are presented in Fig. 10B. In Fig. 10B it’s possible to notice a small difference between the I and Q output levels, as well as a small phase drift.

[0077] B. Modulated Measurements

[0078] The modulated measurements have been performed using a Keysight UXR oscilloscope for time-domain capturing and the PNA-X for frequency-domain capturing. All measurements have been performed at 21 GHz. Fig.l 1 shows the EVM for 16-, 32-, and 64- QAM signals at various data rates, using 7 samples per symbol. A DPD has been trained at every point to account for static IQ-gain and IQ-phase imbalance and LO leakage. The IQ-modulator can reach a data rate of 4.6 Gb/s for both 16- and 32-QAM with an EVM of less than 12.6 % and 8.9 % respectively. For 64-QAM, the IQ-modulator has an average output power of 2.5dBm, consuming 28mA from a 0.9V supply giving a drain efficiency of 7.1%. The power spectral density for a 32-QAM signal sampled at 6.4GHz is shown in Fig. 12. There are no spurs between the signal and the images occurring around ±6.4 GHz from the carrier. Constellation diagrams for some of the points presented in Fig. 11 are shown in Figs. 13A-13F.

[0079] The performance of the RF IQ-modulator is compared with other presented implementations in Table I.

TABLE I

* Working range for modulated signals, CW range is larger. * * PAE.

[0080] IV. CONCLUSION

[0081] In this disclosure we present a 2x6 bit RF IQ-modulator using a novel unit cell featuring inherent LO leakage neutralization, implemented in a commercial 22nm fully depleted SOI CMOS process. The IQ-modulator achieves a saturated output power of 10.4dBm, with a drain efficiency of 15.6%. A peak data rate of 4.6 Gb/s with an EVM of 8.9 % has been demonstrated using 32-QAM. The RF IQ-modulator has been measured at sample rates upto 8GS/s. This is the highest clock rate reported for >3bit fully integrated modulators, making it possible to achieve larger bandwidth and/or higher oversampling.

[0082] While various embodiments are described herein, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of this disclosure should not be limited by any of the above-described exemplary embodiments. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by the disclosure unless otherwise indicated herein or otherwise clearly contradicted by context.

[0083] Additionally, while the processes described above and illustrated in the drawings are shown as a sequence of steps, this was done solely for the sake of illustration. Accordingly, it is contemplated that some steps may be added, some steps may be omitted, the order of the steps may be re-arranged, and some steps may be performed in parallel.

[0084] References

[0085] [1] 5G; NR; Base Station (BS) radio transmission and reception, ETSI3GPP Std.

138.104 (V 15.8.0), Jan. 2020.

[0086] [2] H. J. Qian et al. , “A 20-32-GHz quadrature digital transmitter using synthesized impedance variation compensation,” IEEE Journal of Solid-State Circuits , pp. 1-13, 2020

[0087] [3] K. Khalaf et al. , “Digitally modulated cmos polar transmitters for highly- efficient mm-wave wireless communication,” IEEE Journal of Solid-State Circuits , vol. 51, no.

7, pp. 1579-1592, July 2016.

[0088] [4] S. M. Alavi et al. , “A wideband 2 x 13-bit all-digital I/Q RF-DAC,” IEEE

Transactions on Microwave Theory and Techniques , vol. 62, no. 4, pp. 732-752, April 2014.

[0089] [5] S. Shopov et al. , “Ultra-broadband I/Q RF-DAC transmitters,” IEEE

Transactions on Microwave Theory and Techniques , vol. 65, no. 12, pp. 5411-5421, Dec 2017.

[0090] [6] S. Shopov et al. , “A 19 dBm, 15 Gbaud, 9 bit SOI CMOS power-DAC cell for high-order QAM W-band transmitters,” IEEE Journal of Solid-State Circuits , vol. 49, no. 7, pp. 1653-1664, July 2014.

[0091] [7] H. Al-Rubaye and G. M. Rebeiz, “W-band direct-modulation / , 20-Gb/s transmit and receive building blocks in 32-nm SOI CMOS,” IEEE Journal of Solid-State Circuits , vol. 52, no. 9, pp. 2277-2291, Sep. 2017.

[0092] [8] D. Zhao and P. Reynaert, “A 40 nm CMOS E-band transmitter with compact and symmetrical layout floor-plans,” IEEE Journal of Solid-State Circuits , vol. 50, no. 11, pp. 2560-2571, Nov 2015. [0093] [9] K. Dasgupta et al. , “A 25 Gb/s 60 GHz digital power amplifier in 28nm

CMOS,” in 43rd IEEE European Solid State Circuits Conference, ESSCIRC, Sept 2017, pp. 207-210.

[0094] [10] A. Agah et al. , “A 42 to 47-GHz, 8-bit I/Q digital -to-RF converter with 21- dBm Psat and 16% PAE in 45-nm SOI CMOS,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), June 2013, pp. 249-252.

[0095] [11] P. Eloranta et al. Direct-Digital RF Modulator IC in 0.13μm CMOS for

Wide-Band Multi-Radio Applications. IEEE ISSCC 2005.

[0096] [12] Alavi et al. A 2x13 -bit all-digital EQ RF-DAC in 65-nm CMOS. IEEE RFIC

2013.