Title:
RECEPTION CIRCUIT, INTEGRATED CIRCUIT AND RECEPTION METHOD
Document Type and Number:
WIPO Patent Application WO/2016/046883
Kind Code:
A1
Abstract:
A reception circuit provided with: a de-serializer that converts serial data to parallel data in accordance with a processing clock; a phase difference detection unit that detects, on the basis of the parallel data, a phase difference between the processing clock and the serial data; a control unit that determines, in accordance with an integration result of the phase difference, a phase adjustment amount required for shifting the phase of the processing clock by one bit of the serial data if the delimiters of the parallel data outputted from the de-serializer are not logically correct; and a phase interpolator that shifts the phase of the processing clock by one bit of the serial data using the phase adjustment amount determined in accordance with the integration result.
Inventors:
HASHIMOTO TOMOHIRO (JP)
Application Number:
PCT/JP2014/075074
Publication Date:
March 31, 2016
Filing Date:
September 22, 2014
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H03L7/08; H04L7/033; H03M9/00
Foreign References:
| JP2008005044A | 2008-01-10 | |||
| JP2013255231A | 2013-12-19 |
Attorney, Agent or Firm:
ITOH, Tadashige et al. (JP)
Tadashige Ito (JP)
Tadashige Ito (JP)
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