CROSS-REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims the priority of U.S. Non-Provisional Application Serial No. 13/954,746 entitled "REFERENCE CURRENT GENERATOR" and filed on July 30, 2013, which is expressly incorporated by reference herein in its entirety.

BACKGROUND

Field

[0002] The present invention relates generally to reference current generation. More specifically, the present invention relates to embodiments for a reference current generator including enhanced stability.

Background

[0003] Various electrical applications, such as frequency-to-digital converters (FDC) or charge pump based clock multipliers, may require a reference current, which when integrated onto a capacitor over a reference time interval produces a voltage that may match a reference voltage. The generated voltage is often some fraction of a supply voltage VDD. Current prior-art implementations may require a very large compensation capacitor, which is undesirable.

[0004] A need exists for an enhanced reference current generator. More specifically, a need exists for embodiments related to a reference current generator having enhanced stability and a reduced sized compensation capacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIG. 1 depicts a circuit for generating a reference current.

[0006] FIG. 2 is a timing diagram for the circuit illustrated in FIG. 1.

[0007] FIG. 3 is a circuit diagram of a current generator, according to an exemplary embodiment of the present invention.

[0008] FIG. 4 is a timing diagram for the current generator of FIG. 3, in accordance with an exemplary embodiment of the present invention.

[0009] FIG. 5 is an example clock generator for generating the clocks illustrated in the timing diagram of FIG. 4. [0010] FIG. 6 is a flowchart depicting a method, in accordance with an exemplary embodiment of the present invention.

[0011] FIG. 7 is a flowchart depicting another method, in accordance with an exemplary embodiment of the present invention.

[0012] FIG. 8 illustrates a device including a reference current generator, in accordance with an exemplary embodiment of the present invention.

DETAILED DESCRIPTION

[0013] The detailed description set forth below in connection with the appended

drawings is intended as a description of exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention can be practiced. The term "exemplary" used throughout this description means "serving as an example, instance, or illustration," and should not necessarily be construed as preferred or advantageous over other exemplary embodiments. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary embodiments of the invention. It will be apparent to those skilled in the art that the exemplary embodiments of the invention may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary embodiments presented herein.

[0014] As noted above, in some applications, such as in frequency to digital converters

(FDC) or charge pump based clock multipliers, there may be a need to generate a reference current that, when integrated onto a capacitor over a reference time interval (e.g., a multiple of a clock period), produces a voltage matching a reference voltage. The generated reference voltage is often some fraction of VDD or an inverter threshold.

[0015] FIG. 1 is a circuit diagram of a reference current generator 100. Reference current generator 100 includes an amplifier 102, resistors Rl and R2, capacitors Cc, C _H O _LD , and C _I N _T , transistors Ml and M2, and switches Scpo, Scps, and Sdiv2. During an operation of reference current generator 100, switch Sdiv2 may be closed for a time period (e.g., having a duration of one clock cycle) and a current is conveyed to charge capacitor C _INT - After the time period, switch Sdiv2 may be opened for another time period (e.g., having a duration of one clock cycle). During the time period wherein switch Sdiv2 is opened, switch Scps niay be closed for a relatively short time period (i.e., a duration sufficient to enable a voltage across capacitor C _H O _LD to stabilize) to charge capacitor C _H O _LD - Further, after switch Scps is opened, switch Scpo may be closed for a relatively short time period (i.e., a duration sufficient to enable capacitor Ci _NT to be discharged). As will be appreciated by a person having ordinary skill in the art, a voltage at node NO is used by amplifier 102 to adjust the amount of current conveyed to capacitor Q _NT until an adequate voltage at node NO is obtained.

[0016] FIG. 2 is a timing diagram 120 for operating current generator 100. Timing diagram 120 includes timing signals for a clock reference ckref, switch Sdiv2, switch Scps, and switch Scpo- As illustrated in timing diagram 120, switch Sdiv2 is closed (i.e., asserted to couple a source of transistor Ml to supply voltage V _DD ) for a full clock cycle starting at time ti and ending and time t ₂ . Further, switch Sdiv2 is opened (i.e., negated to isolate the source of transistor Ml from supply voltage V _DD ) for a full clock cycle starting at time t ₂ and ending and time t ₇ . In addition, after switch Sdiv2 is closed at time t2, switch Scps is closed at time t ₃ and opened at time t ₄ .

[0017] As noted above, switch Scps is closed for a time duration sufficient to enable a voltage across capacitor C _H O _LD (see FIG. 1) to stabilize. Moreover, after switch Scps is opened at time t ₄ , switch Scp _D is closed at time t ₅ and opened at time t ₆ . As previously noted, switch Scpo is closed for a time duration sufficient to enable capacitor Q _NT (see FIG. 1) to be discharged. This cycle may be repeated starting at time t ₇ . It is noted that each of switch Scps, and switch Scpo are closed (i.e., asserted) while switch Sdiv2 is negated.

[0018] As will be appreciated by a person having ordinary skill in the art, when settled, reference current generator 100 may generate a reference current I _REF that when integrated over a clock period onto capacitor Q _NT , generates a reference voltage, which may be a fraction of supply voltage VDD. For reference current generator 100 to be stable, a bandwidth of amplifier 102 must be substantially less than a frequency of a sampling clock. If the sampling clock is fairly low, for example 19.2 MHz, a very large compensation capacitor Cc (e.g., between 10 and 100 picofarads (pF)) is required to stabilize a feedback loop.

[0019] It may appear that selecting a value of capacitor C _H O _LD that is much larger than a value of capacitor Q _NT may stabilize the feedback loop. However, if a large difference exists between a voltage on capacitor C _H O _LD and a voltage at the negative input terminal of amplifier 102 (e.g., when reference current generator 100 is first powered-up), an output of amplifier 102 may rail high or low. Therefore, changing the relative sizing of capacitor C _H O _LD and capacitor C _INT may not be a viable option to stabilize current generator 100. One alternative is to brute-force compensate current generator 100 by using a very large compensation capacitor Cc, which is undesirable.

[0020] Exemplary embodiments, as described herein, are directed to a reference current generator. According to one exemplary embodiment, a device may include a hold capacitor coupled to an input of an amplifier. Further, the device may include a first integration capacitor configured for selectively charging the hold capacitor and a second integration capacitor configured for selectively charging the hold capacitor. According to another exemplary embodiment, a device may include a first integration path for charging a first integration capacitor during a first phase. The device may further include a second integration path for charging a second integration capacitor during a second phase. Moreover, the first integration capacitor may be configured for charging a capacitor coupled to an amplifier during the second phase and the second integration capacitor may be configured for charging the capacitor during the first phase.

[0021] According to another exemplary embodiment, the present invention includes methods for generating a reference current. Various embodiments of such a method may include generating a voltage at an input of an amplifier. The method may also include charging a hold capacitor coupled to the input of the amplifier via a first integration capacitor during a portion of a first phase and charging the hold capacitor via a second integration capacitor during a portion of a second, different phase. In accordance with another exemplary embodiment, a method may include coupling a first capacitor to a supply voltage during a phase and coupling a second capacitor to the supply voltage during another, different phase. The method may further include coupling the second capacitor to a hold capacitor during at least a portion of the phase and coupling the first capacitor to the hold capacitor during at least a portion of the another, different phase.

[0022] Other aspects, as well as features and advantages of various aspects, of the

present invention will become apparent to those of skill in the art though consideration of the ensuing description, the accompanying drawings and the appended claims.

[0023] FIG. 3 is a circuit representation of a current generator 300, according to an

exemplary embodiment of the present invention. Current generator 300 is configured to generate a reference current I _REF . As depicted, current generator 300 includes amplifier 302, resistors Rl and R2, and capacitors Cci, CINTI, CHOLD, and CINT2- Current generator 300 further includes transistors M3, M4, and M5, switches Scpoi, Scpm, Scpc, Scpsi, S(ps2, Sdiv2, and Sdiv2b, and tail current source ICURRENT- A first input (e.g., an inverting input) of amplifier 302 is coupled to a node A, which is positioned between resistors Rl and R2. Resistor Rl is further coupled to a supply voltage VDD and resistor R2 is further coupled to a ground voltage GRND. In addition, amplifier 302 is configured to receive supply voltage via a node B, which is further coupled to each of switch Sdiv2b, compensation capacitor Cci, switch Sdiv2, and a source of transistor M5.

[0024] An output of amplifier 302 is coupled to a gate of each of transistors M3, M4, and

M5. A source of transistor M3 is coupled to a node C via switch Sdiv2b and a drain of transistor M3 is coupled to a node G. Moreover, a source of transistor M4 is coupled to a node E via switch Sdiv2 and a drain of transistor M4 is coupled to a node I.

Compensation capacitor Cci is coupled between nodes D and F. By way of example only, compensation capacitor Cci may have a size of substantially 500 femtofarads (fF). A node H, which is switchably coupled to nodes G and I via respective switches Scpsi and Scps2, is further coupled to a second input (e.g., a non-inverting input) of amplifier 302 and capacitor CHOLD- Capacitor CINTI is coupled between nodes G and K, capacitor CHOLD is coupled between nodes H and L, and capacitor NT2 is coupled between nodes I and M. Additionally, switch Scpc is configured for coupling current source IsouRCE to ground voltage GRND, which is further coupled to nodes K, L, and M.

[0025] During an operation of reference current generator 300, switch Sdiv2 may be closed for a time period (e.g., having a duration of one clock cycle) and a current may be conveyed to charge capacitor NT2- Further, during another, different (i.e., a time period in which switch Sdiv2 is opened), switch Sdiv2b may be closed and a current may be conveyed to charge capacitor CINTI- Moreover, during the time period in which switch Sdiv2 is closed and Sdiv2b is open, switch Scpsi may be closed for a relatively short time period (i.e., a duration sufficient to enable a voltage across capacitor CHOLD to stabilize) to charge capacitor CHOLD- Stated another way, switch psi may be closed for a duration sufficient to charge share between capacitor CINTI and capacitor CHOLD- Further, after switch Scpsi is opened, switch Scpoi may be closed for a relatively short time period (i.e., a duration sufficient to enable capacitor CINTI to be discharged).

[0026] In addition, during the time period in which switch Sdiv2b is closed and Sdiv2 is open, switch Scps ₂ may be closed for a relatively short time period (i.e., a duration sufficient to enable a voltage across capacitor C _H O _LD to stabilize) to charge capacitor C _H O _LD - Stated another way, switch Scps ₂ may be closed for a duration sufficient to charge share between capacitor _NT2 and capacitor C _H O _LD - Further, after switch Scps ₂ is opened, switch Scp _D2 may be closed for a relatively short time period (i.e., a duration sufficient to enable capacitor _NT2 to be discharged). As will be appreciated by a person having ordinary skill in the art, a voltage at node G is used by amplifier 302 to adjust the amount of current conveyed to capacitors _NTI and C _INTI until an adequate voltage at node H is obtained.

[0027] FIG. 4 is an example timing diagram 350 for operating current generator 300 of

FIG. 3. Time diagram 350 includes timing signals for a clock reference ckref, switch Sdiv2, switch Scpsi, switch Scpoi, switch Scps ₂ , switch ScpD2, and switch Scpc. As illustrated in timing diagram 350, switch Sdiv2 is closed (i.e., asserted to couple a source of transistor M4 to supply voltage V _DD ) and switch Sdiv2b is closed for a full clock cycle starting at time tl and ending and time t6. Further, switch Sdiv2 is opened (i.e., negated to isolate the source of transistor M4 from supply voltage V _DD ) and switch Sdiv2b is closed (i.e., asserted to couple a source of transistor M3 to supply voltage V _DD ) for a full clock cycle starting at time t6 and ending and time tl 1. Additionally, after switch Sdiv2 is closed at time tl, switch Scpsi is closed at time t2 and opened at time t3. Switch Scpsi may be closed for a time duration sufficient to enable a voltage across capacitor C _H O _LD (see FIG. 3) to stabilize. Moreover, after switch Scpsi is opened at time t3, switch Scpoi is closed at time t4 and opened at time t5. Switch Scpoi may be closed for a time duration sufficient to enable capacitor C _INTI (see FIG. 3) to be discharged. Moreover, switch Scpc is also closed at time t4 and opened at time t5.

[0028] After switch Sdiv2 is opened and switch Sdiv2b is closed at time t6, switch Scps ₂ is closed at time tl and opened at time t8. Switch Scps ₂ may be closed for a time duration sufficient to enable a voltage across capacitor C _H O _LD (see FIG. 3) to stabilize. Moreover, after switch Scps ₂ is opened at time t8, switch Scpo ₂ is closed at time t9 and opened at time tlO. Switch Scpo ₂ may be closed for a time duration sufficient to enable capacitor Q _NT2 (see FIG. 3) to be discharged. Moreover, switch Scpc is also closed at time t9 and opened at time tlO. As will be appreciated by a person having ordinary skill in the art, this cycle (i.e., the cycle from time tl to time tlO) may be repeated starting at time tl 1. [0029] In comparison to prior art devices, reference current generator 300 may use a reduced-sized compensation capacitor by using a combination of amplifier bias current duty cycle throttling and double sampling. An update rate of the voltage on hold capacitor C _R O _LD is effectively doubled by adding a second integration capacitor Q _NT2 and operating its integration, sampling, and discharge switches on the opposite phase of the div2 clock. As will be appreciated by a person having ordinary skill in the art, increasing the update rate of hold capacitor C _H O _LD allows the bandwidth of amplifier 302 to be correspondingly higher, requiring less compensation capacitance. To further reduce a bandwidth of amplifier 302, the tail current of amplifier 302 may be duty-cycle throttled using a very low duty cycle clock cpc.

[0030] It is noted that amplifier 302 may comprise a single-stage, five transistor design with an NMOS tail current source, NMOS differential pair, and PMOS current mirror load. Current source ISOU _R C _E may comprise the NMOS tail current source. Shutting off the tail current (i.e., via current source ISOU _R C _E ) to amplifier 302 freezes the voltage at its output until the next time the tail current is turned on. Since an output voltage of amplifier 302 can only change during a small period of time once per reference clock cycle, a bandwidth of amplifier 302 is greatly reduced, allowing a much smaller compensation capacitor Cc to be used. Furthermore, the bandwidth reduction tracks the reference clock, maintaining good phase margin over a wide range of frequencies.

[0031] FIG. 5 depicts a clock generator 400 for generating the clocks shown in timing diagram 350. It is noted that clock generator 400 is only an example of a clock generator that may be used for generating clocks signal and other suitable clock generators may be used for generating the clock signals. Clock generator 400 includes D-fiip-fiops 402, 404, 406, 408, and 410, buffers 412, 414, 416, 418, 420, 422, 424, and 426, and NAND gate 428. As will be appreciated by a person having ordinary skill in the art, D-flip-flop 402 may receive clock reference ckref and a feedback signal (e.g., signal div2b) and convey signals div2 and div2b. Further, signal div2 may be conveyed via buffer 412 to D-flip-flop 408, which also receives supply voltage V _DD - In response to receipt of signal div2 and supply voltage V _DD , D-flip-flop 408 may generate switch signal cpsi, which may be used for controlling switch Scpsi (see FIG. 3). Switch signal cpsi may also be conveyed to a reset port rst of D-flip-flop 408 via buffer 416. Further, D-flip-flop 408 may generate a signal FF1, which may be conveyed via buffer 418 to D- flip-flop 410, which also receives supply voltage V _DD - In response to receipt of signal FFl and supply voltage V _DD , D-flip-flop 410 may generate switch signal cp _D1 , which may be used for controlling switch Scpoi (see FIG. 3). Switch signal cp _D1 may also be conveyed to a reset port rst of D-flip-flop 410 via buffer 420. Further, D-flip-flop 410 may generate a signal FF2, which may be conveyed to an input terminal of NAND gate 428.

[0032] Signal div2b, which is output from D-flip-flop 402, may be conveyed via buffer

414 to D-flip-flop 404, which also receives supply voltage V _DD - In response to receipt of signal div2b and supply voltage V _DD , D-flip-flop 404 may generate switch signal cp _S2 , which may be used for controlling switch Scps ₂ (see FIG. 3). Switch signal cps ₂ may also be conveyed to a reset port rst of D-flip-flop 404 via buffer 422. Further, D-flip-flop 404 may generate a signal FF3, which may be conveyed via buffer 424 to D-flip-flop 406, which also receives supply voltage V _DD - In response to receipt of signal FF3 and supply voltage V _DD , D-flip-flop 406 may generate switch signal cp _D2 , which may be used for controlling switch Scpo ₂ (see FIG. 3). Signal cp _D2 may also be conveyed to a reset port rst of D-flip-flop 406 via buffer 423. Further, D-flip-flop 406 may generate a signal FF4, which may be conveyed to another input terminal of NAND gate 428.

Upon receipt of signal FF2 from D-flip-flop 410 and signal FF4 from D-flip-flop 406, NAND gate 428 may output a signal cpc, which may be used for controlling switch Scpc (see FIG. 3).

[0033] FIG. 6 is a flowchart illustrating a method 650, in accordance with one or more exemplary embodiments. Method 650 may include coupling a first capacitor to a supply voltage during a phase (depicted by numeral 652). Method 650 may also include coupling a second capacitor to the supply voltage during another, different phase (depicted by numeral 654). In addition, method 650 may include coupling the second capacitor to a hold capacitor during at least a portion of the phase (depicted by numeral 656). Moreover, method 650 may include coupling the first capacitor to the hold capacitor during at least a portion of the another, different phase (depicted by numeral 658).

[0034] FIG. 7 is a flowchart illustrating another method 700, in accordance with one or more exemplary embodiments. Method 700 may include generating a voltage at an input of an amplifier (depicted by numeral 702). In addition, method 700 may also include charging a hold capacitor coupled to the input of the amplifier via a first integration capacitor during a portion of a first phase (depicted by numeral 704). Method 700 may also include charging the hold capacitor via a second integration capacitor during a portion of a second, different phase (depicted by numeral 706).

[0035] FIG. 8 is a block diagram of an electronic device 800, according to an exemplary embodiment of the present invention. According to one example, device 800 may comprise a portable electronic device, such as a mobile telephone. By way of example, device 800 may comprise at least one current generator 300 described above with respect to FIGS. 3-7. In this example, device 800 includes one or more modules, such as a digital module 802 and an RF module 804. Digital module 802 may comprise memory and one or more processors. RF module 804, which may comprise a radio-frequency integrated circuit (RFIC), may include a transceiver 806 including a transmitter 808 and a receiver 810 and may be configured for bi-directional wireless communication via an antenna 812.

[0036] In general, device 800 may include any number of transmitters and any number of receivers for any number of communication systems, any number of frequency bands, and any number of antennas. Further, RF module 804 may include one or more current generators, such as current generator 300 illustrated in FIG. 3. As a more specific, non- limiting example, RF module 804 may include one or more frequency to digital converters (FDC) and/or charge pump based clock multipliers including at least one current generator 300, as illustrated in FIG. 3.

[0037] Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0038] Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the exemplary embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the exemplary embodiments of the invention.

[0039] The various illustrative logical blocks, modules, and circuits described in

connection with the exemplary embodiments disclosed herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of

microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0040] In one or more exemplary embodiments, the functions described may be

implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The previous description of the disclosed exemplary embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these exemplary embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the exemplary embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.