Title:
REGULATOR CIRCUIT PROVIDED WITH PROTECTION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/051744
Kind Code:
A1
Abstract:
According to the present invention, a buffer stage (4, 804) comprises: a first transistor (15) that has a control terminal that is connected to an output terminal of an op-amp (3); and a second transistor (16) that is connected in series to a main conduction path of the first transistor. When the current flowing in a main conduction path of an output transistor (6) as detected using an overcurrent detection transistor (19) is below a prescribed value, an overcurrent control circuit (5, 205, 305, 405, 505, 605, 705, 805) passes the output voltage of the op-amp through the control terminal of the first transistor so as to make the first transistor operate normally. When the current flowing in the main conduction path of the output transistor is at or above the prescribed value, the overcurrent control circuit controls the output voltage of the op-amp to a prescribed voltage that corresponds to the current flowing in a main conduction path of the overcurrent detection transistor. A regulator circuit is thereby protected from overcurrent.
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Inventors:
FUJIMOTO YUU (JP)
KAI YOSHIHIDE (JP)
KAI YOSHIHIDE (JP)
Application Number:
PCT/JP2016/076875
Publication Date:
March 30, 2017
Filing Date:
September 13, 2016
Export Citation:
Assignee:
DENSO CORP (JP)
International Classes:
G05F1/56
Foreign References:
| JP2013003700A | 2013-01-07 | |||
| US20100090665A1 | 2010-04-15 | |||
| JP2014002458A | 2014-01-09 | |||
| JP2002023868A | 2002-01-25 | |||
| JP2012088987A | 2012-05-10 | |||
| JPH08263152A | 1996-10-11 |
Attorney, Agent or Firm:
JIN Shunji (JP)
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