Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SCRAMBLING DATA-PORT AUDIO IN SOUNDWIRE SYSTEMS
Document Type and Number:
WIPO Patent Application WO/2020/081387
Kind Code:
A1
Abstract:
Systems and methods for scrambling data-port audio in SOUNDWIRE™ systems include a scramble enable feature that allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS) such as, but not limited to, the PRBS defined in the SOUNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk.

Inventors:
AMARILIO LIOR (US)
BENJAMINI YIFTACH (US)
GRAIF SHARON (US)
Application Number:
US2019/055841
Publication Date:
April 23, 2020
Filing Date:
October 11, 2019
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
QUALCOMM INC (US)
International Classes:
G06F13/42; H04L25/03
Foreign References:
US20140269954A12014-09-18
US20130195218A12013-08-01
GB2265069A1993-09-15
US8949493B12015-02-03
US20170117979A12017-04-27
US201862745534P2018-10-15
US201916597902A2019-10-10
Other References:
MIPI ALLIANCE: "Mipi Specification for SoundWire - Version 1.0", MIPI SOUNDWIRE,, no. Version 1.0, 1 January 2015 (2015-01-01), pages 289pp, XP009191915
Attorney, Agent or Firm:
DAVENPORT, Taylor, M. (US)
Download PDF:
Claims:
What is claimed is:

1 A method for reducing crosstalk in an audio system, comprising;

at an audio source associated with an audio bus, enabling an output signal from a linear feedback shift register (LFSR) based on an enable signal, wherein the output signal comprises an offset output of a pseudo-random binary sequence (PRBS),

scrambling a data stream with the output signal of the LFSR to produce a scrambled stream of data; and

providing the scrambled stream of data to the audio bus.

2 The method of claim 1, wherein the audio system comprises a SOUND WIRE or SOUND WIRE NEXT audio system.

3. The method of claim 1, wherein scrambling the data stream with the output signal of the LFSR comprises using an exclusive OR (XOR) circuit.

4. The method of claim 1, further comprising multiplexing the output signal of the LFSR with a zero signal.

5 The method of claim l, further comprising using a first offset for a first data port and a second offset, different than the first offset, for a second data port in the audio source.

6. A method for reducing crosstalk in an audio system, comprising:

at an audio sink associated with an audio bus, enabling an output signal from a linear feedback shift register (LFSR) based on an enable signal, wherein the output signal comprises an offset output of a pseudo-random binary sequence (PRBS);

descrambling an incoming data stream from the audio bus with the output signal of the LFSR to produce a descramhled stream of data; and outputting the descramhled stream of data.

7. The method of claim 6, wherein the audio system comprises a SOUND WIRE or SGUNDWlRE NEXT audio system.

8. The method of claim 6, wherein descrambling the incoming data stream with the output signal of the LFSR comprises using an exclusive OR (XOR) circuit.

9. The method of claim 6, further comprising multiplexing the output signal of the LFSR with a zero signal.

10. The method of claim 6, wherein the audio sink comprises an application processor.

11. An audio source comprising:

an audio bus interface comprising a first data port coupled to an audio bus; and a control system coupled to the audio bus interface;

wherein the first data port comprises:

a first linear feedback shift register (LFSR),

a first offset circuit coupled to the first LFSR configured to provide a first offset signal to the first LFSR; and

a first exclusive Oll (XOR) circuit coupled to the first LFSR to scramble a stream of data to be provided to the audio bus.

12. The audio source of claim 11 integrated into an integrated circuit (IC).

13. The audio source of claim 1 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit, a navigation device; a communications device, a fixed location data unit, a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor, a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

14. The audio source of claim 11, further comprising a multiplexer coupled to the first LFSR and the first XOR circuit.

15. The audio source of claim 11, further comprising a second data port, the second data port comprising:

a second LFSR

a second offset circuit coupled to the second LFSR configured to provide a second offset signal to the second LFSR; and

a second XOR circuit coupled to the second LFSR to scramble a second stream of data to be provided to the audio bus.

16. The audio source of claim 15, wherein the second offset circuit provides the second offset signal that is different than the first offset signal provided by the first offset circuit.

17. The audio source of claim 11, further comprising a microphone.

18. The audio source of claim 11, wherein the audio bus comprises a SOUNDWIRE or SOUNDWIRE NEXT audio bus.

19. An audio system comprising:

an audio bus,

an audio sink coupled to the audio bus; and

an audio source comprising:

an audio bus interface comprising a first data port coupled to the audio bus; and

a control system coupled to the audio bus interface,

wherein the first data port comprises: a first linear feedback shift register (LFSR);

a first offset circuit coupled to the first LFSR configured to provide a first offset signal to the first LFSR; and a first exclusive OR (XOR) circuit coupled to the first LFSR to scramble a stream of data to be provided to the audio bus.

20. The audio system of claim 19, wherein the audio source comprises a microphone.

21. The audio system of claim 19, wherein the audio bus comprises a SOUNDWIRE or SOUNDWIRE NEXT audio bus.

22. The audio system of claim 19, wherein the audio source further comprises a second data port, the second data port comprising:

a second LFSR

a second offset circuit coupled to the second LFSR configured to provide a second offset signal to the second LFSR; and

a second XOR circuit coupled to the second LFSR to scramble a second stream of data to be provided to the audio bus.

23. The audio system of claim 22, further comprising an application processor, wherein the application processor is configured to program the first and second offset circuits during a configuration process.

24. The audio system of claim 19 integrated into a device selected from the group consisting of: a set top box; an entertainment unit, a navigation device; a communications device, a fixed location data unit, a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor, a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

25. An audio sink comprising:

an audio bus interface comprising a physical layer (PHY) coupled to an audio bus; and

a control system coupled to the audio bus interface;

wherein the PHY comprises a linear feedback shift register (LFSR) coupled to an exclusive OR (XOR) circuit to descramble an incoming stream of data received from the audio bus.

26. The audio sink of claim 25 integrated into an integrated circuit (IC).

27. The audio sink of claim 25 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device, a fixed location data unit, a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television, a tuner, a radio, a satellite radio, a music player, a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile, a vehicle component; avionics systems; a drone; and a multicopter.

28. The audio sink of claim 25, further comprising a multiplexer coupled to the LFSR and the XOR circuit.

29. The audio sink of claim 25, wherein the audio bus comprises a SOUND WIRE or

SOUNDWIRE NEXT audio bus.

Description:
SCRAMBLING DATA-PORT AUDIO IN SOUNDWIRE SYSTEMS

PRIORITY CLAIM

[0001] The present application claims priority to U.S. Provisional Patent Application Serial No. 62/745,534 filed on October 15, 2018 and entitled “SCRAMBLING DATA-PORT AUDIO IN SOUNDWIRE SYSTEMS,” the contents of which is incorporated herein by reference in its entirety.

[0002] The present application also claims priority to U.S. Patent Application Serial No. 16/597,902 filed on October 10, 2019 and entitled“SCRAMBLING DATA-PORT AUDIO IN SOUNDWIRE SYSTEMS,” the contents of which is incorporated herein by reference in its entirety.

BACKGROUND L Field of the Disclosure

[0003] The technology of the disclosure relates generally to audio systems and particularly for controlling noise for SOUND WIRE audio systems.

IL Background

[0004] Mobile communication devices have become increasingly common in current society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences.

[0005] The mobile communication devices commonly include at least one microphone and multiple speakers. The microphone and the speakers used in the mobile communication devices typically have analog interfaces which require a dedicated two-wire connection between each pair of devices. Since a mobile communication device is capable of supporting multiple audio devices, it may be desired to allow a microprocessor or other control device in the mobile communication device to communicate audio data to multiple audio devices over a common communication bus simultaneously. [0006] In this regard, the MIPI© Alliance initially developed the Serial Low-power

Inter-chip Media Bus (SLIMbus or SLIMBUS) to handle audio signals within a mobile communication device. The first release was published in October 2005 with vl.01 released on December 3, 2008 In response to industry feedback, MIPI has also developed SoundWire SM (SOUNDWIRE), a communication protocol for a processor in the mobile communication device (the“master”) to control distribution of digital audio streams between one or more audio devices (the “slave(s)”) via one or more SOUNDWIRE slave data ports. Version 1.1 was released June 27, 2016.

[0007] Many mobile communication devices that use SOUNDWIRE audio buses incorporate multiple microphones that are attached to the SOUNDWIRE audio bus. Even when the microphones are acoustically isolated from one another, the microphones may experience crosstalk. In particular, when a first microphone toggles a bit on a bus and thus drives current on the bus, that current may cause a minor current on an input/output pad on a second microphone, which may create heat in the cavity of the second microphone. This heat changes the operating condition of the sound capturing membrane of the second microphone. Current models indicate that this thermal change creates a low-pass filter for the second microphone allowing low' frequency signals from the first microphone to be modulated into signals from the second microphone. Such crosstalk, or crosstalk caused by other sources, may cause the resulting audio signal to be affected sufficiently to be detectable by the human ear and thus may negatively impact the audio experience. Accordingly, there is a need to mitigate this crosstalk.

SUMMARY OF THE DISCLOSURE

[0008] Aspects disclosed in the detailed description include systems and methods for scrambling data-port audio in SOUNDWIRE™ systems. In an exemplary aspect, a scramble enable feature allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS), such as, but not limited to, the PRBS defined in the SOUNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk. In a system where there is more than one microphone or a microphone with more than one port, a different offset of the output of the LFSR may be used for each port.

[0009] In this regard in one aspect, a method for reducing crosstalk in an audio system is disclosed. The method includes, at an audio source associated with an audio bus, enabling an output signal from a LFSR based on an enable signal. The output signal includes an offset output of a PRBS. The method also includes scrambling a data stream with the output signal of the LFSR to produce a scrambled stream of data. The method also includes providing the scrambled stream of data to the audio bus.

[0010] In another aspect, a method for reducing crosstalk in an audio system is disclosed. The method includes, at an audio sink associated with an audio bus, enabling an output signal from a LFSR based on an enable signal. The output signal includes an offset output of a PRBS. The method also includes descrambling an incoming data stream from the audio bus with the output signal of the LFSR to produce a descrambied stream of data. The method also includes outputting the descrambied stream of data.

[0011] In another aspect, an audio source is disclosed. The audio source includes an audio bus interface including a first data port coupled to an audio bus. The audio source also includes a control system coupled to the audio bus interface. The first data port includes a first LFSR. The first data port also includes a first offset circuit coupled to the first LFSR configured to provide a first offset signal to the first LFSR The first data port also includes a first exclusive OR (XOR) circuit coupled to the first LFSR to scramble a stream of data to be provided to the audio bus.

[0012] In another aspect, an audio system is disclosed. The audio system includes an audio bus, and audio sink coupled to the audio bus, and an audio source. The audio source includes an audio bus interface including a first data port coupled to the audio bus. The audio source also includes a control system coupled to the audio bus interface. The first data port includes a first LFSR. The first data port also includes a first offset circuit coupled to the first LFSR configured to provide a first offset signal to the first LFSR. The first data port also includes a first XOR circuit coupled to the first LFSR to scramble a stream of data to be provided to the audio bus.

[0013] In another aspect, an audio sink is disclosed. The audio sink includes an audio bus interface including a physical layer (PHY) coupled to an audio bus. The audio sink also includes a control system coupled to the audio bus interface. The PHY includes a LFSR coupled to an XOR circuit to descramble an incoming stream of data received from the audio bus.

BRIEF DESCRIPTION OF THE FIGURES

[0014] Figure 1 is a block diagram of an exemplary SOUNDWIRE audio system;

[0015] Figure 2 is a block diagram of a master device that may be associated with the SOUNDWIRE audio system of Figure 1;

[0016] Figure 3 is a block diagram of a slave device that may be associated with the SOUNDWIRE audio system of Figure 1 ;

[0017] Figure 4 is a block diagram of an exemplary mixed SOUNDWIRE and SOUNDWIRE NEXT audio system;

[0018] Figure 5 is a simplified block diagram of a data port for an audio source in an audio system showing a scrambling capability according to an exemplary aspect of the present disclosure;

[0019] Figure 6 is a simplified block diagram of a data port for an audio sink in an audio system showing a descrambling capability according to an exemplary aspect of the present disclosure;

[0020] Figure 7A is a flowchart illustrating an exemplary ' process for scrambling data at an audio data port for an audio source;

[0021] Figure 7B is a flowchart illustrating an exemplary' process for descrambling data at an audio data port for an audio sink;

[0022] F igure 8A is a system-level block diagram of an exemplary mobile terminal that can include the audio system of Figures 1 or 4;

[0023] Figure 8B is a system-level block diagram of an alternate exemplary' mobile terminal that can include the audio system of Figures 1 or 4;

[0024] Figure 8C is a system-level block diagram of another alternate exemplary' mobile terminal that can include the audio system of Figures 1 or 4;

[0025] Figure 9 is a table from the SOUNDWIRE specification showing a. predefined pseudo-random binary' sequence (PRBS) used in an exemplary scrambling and descrambling of the present disclosure; [0026] Figure 10 is a simplified block diagram of an audio system with multiple microphone ports connected to an audio sink; and

[0027] Figure 11 is a flowchart illustrating configuration and offset assignment before enabling signals on an audio bus

DETAILED DESCRIPTION

[0028] With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word“exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0029] Aspects disclosed in the detailed description include systems and methods for scrambling data-port audio in SOUNDW1RE™ systems. In an exemplary aspect, a scramble enable feature allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS) such as, but not limited to, the PRBS defined in the SOIJNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk. In a system where there is more than one microphone or a microphone with more than one port, a different offset of the output of the LFSR may be used for each port.

[0030] Exemplary aspects of the present disclosure are well-suited for use in both SOUNDWIRE and SOIJNDWIRE NEXT audio systems. A SOIJNDWIRE audio system is discussed with reference to Figure I while master and slave devices are discussed with reference to Figures 2 and 3, respectively. A mixed SOUNDWIRE/SOUNDWIRE NEXT audio system is discussed with reference to Figure 4. The audio sinks and audio sources within each system may include exemplary aspects of the present disclosure. A discussion of particular details of the present disclosure begins below with reference to Figure 5.

[003 ] In this regard. Figure 1 is a block diagram of an audio system 100 having a multi-drop differential audio bus 102. In particular, the bus 102 couples a master device 104 such as an audio codec or application processor to one or more slave devices 1G6(1)-106(N). For the purposes of illustration, N is four herein. The slave devices 106(1) and 106(2) may be microphones and include analog-to-digital converters (ADCs) while the slave devices 106(3) and 106(4) may be speakers and include digital - to-analog converters (DACs). The master device 104 includes an interface (historically called a downstream -facing interface (DFI), although this term is currently out of favor, this term may he used by some authors) 108, while the slave devices 106(1)-106(N) include respective interfaces (historically called upstream-facing interfaces (UFIs) although again, this term is currently out of favor) H0(l)-110(N). While any multi drop differential audio bus may use aspects of the present disclosure, exemplary aspects specifically contemplate a SOUNDWIRE or SOUND WIRE NEXT multi-drop differential audio bus.

[0032] As better illustrated in Figure 2, the master device 104 may include the interface 108, which may be a physical layer (PHY) including one or more transistors and/or a bus keeper circuit (not illustrated) that control signal levels on the bus 102. Further, the master device 104 may include a transceiver 112 coupled to the interface 108 and a control system (CS) 114. The control system 114 may be hardware based and/or operate software including drivers or the like and may interoperate with a memory ' (MEM) 116 which may include one or more registers. Similarly, a slave device 106 is illustrated in Figure 3 and may include an interface 1 10, which may be a PHY including one or more transistors (not illustrated) that control signal levels on the bus 102. Further, the slave device 106 may include a transceiver 118 coupled to the interface 110 and a control system (CS) 120. The control system 120 controls the transport response and access to a memory ' 122. The control system 120 may further control an input/output (I/O) device 124 (e.g., a microphone or speaker).

[0033] In an exemplary aspect, the slave devices 106(1) and 106(2) may act as audio sources in that an audio signal originates therefrom. Likewise, the slave devices 106(3) and 106(4) may act as audio sinks in that audio signals are sent thereto. The master device 104 may, relative to the slave devices 106(1) and 106(2) may be an audio sink, but may be an audio source relative to the slave devices 106(3) and 106(4). That is, a particular port within the master device 104 may be functioning as an audio source or audio sink depending on the nature of the link for the port. [0034] While the audio system 100 conforms in appearance to a SOUNDWIRE system, it should be appreciated that exemplar}- aspects of the present disclosure also are applicable to SOUNDWIRE NEXT systems. SOUNDWIRE NEXT was initially referred to as SOUNDWIRE-XL and may be renamed in future iterations. As of this writing, the latest published version is SOUNDWIRE-XL version 0.2-r01, with a new version expected shortly after this writing. In this regard. Figure 4 is a block diagram of an exemplary expanded SOUNDWIRE system 400 with a bridge 402 and a SOUNDWIRE NEXT segment 404 formed between an application processor 104 and the bridge 402 by a SOUNDWIRE NEXT cable 406. The SOUNDWIRE NEXT cable 406 is a two-wire cable configured to carry a differential signal thereover. The application processor 104 is a master device relative to the bridge 402. While described as an application processor 104, it should be appreciated that the master device may instead be a codec or other element as is well understood. The application processor 104 may be in a device such as a mobile computing device (not shown) that includes a receptacle 408 configured to receive a SOUNDWIRE NEXT cable such as the SOUNDWIRE NEXT cable 406. The SOUNDWIRE NEXT cable 406 may be up to two meters (2 m or 200 centimeters (cm)) long. The receptacle 408 may be operatively associated with an interface 410 (which may or may not be in the application processor 104) that includes appropriate electrical contacts to convey a differential data signal with an embedded clock signal to the two wires of the SOUNDWIRE NEXT cable 406. The interface 410 may further be operatively coupled to a control system (labeled CS in the Figures) 412 The function of the control system 412 is explored in greater detail below.

[0035] With continued reference to Figure 4, the bridge 402 is configured to operate as a slave device relative to the application processor 104, and translate SOUNDWIRE NEXT signals to SOUNDWIRE signals for use on a SOUNDWIRE system 100 In the SOUNDWIRE system 100, the bridge 402 acts as a master device and is configured to send and receive signals to slave devices I06(1)-I06(N) through a SOUNDWIRE bus 102. While Figure 4 illustrates one bridge arrangement, a reversed bridge changing from SOUNDWIRE to SOUNDWIRE NEXT may allow legacy SOUNDWIRE master devices to couple to slaves at a greater distance (e.g., a legacy application processor coupling to devices in a headset through a cable more than 50 cm long). [0036] Note further, SOUNDWIRE NEXT currently supports a multi-drop arrangement and would look similar to the SOUNDWIRE system 100 of Figure 1. Likewise, the block diagrams of the master device 104 and the slave device 106 of Figures 2 and 3 would also genericaliy apply to masters and slaves in a SOUNDWIRE NEXT system.

[0037] To provide the scrambling and deserambling functionality of the present disclosure, the data ports of the audio sources and audio sink are modified from conventional structures through the addition of certain elements within the respective data ports. In this regard, Figure 5 illustrates a source data port 500 associated with an audio source (e.g., the slave device 106(1), which is a microphone). The source data port 500 receives an outgoing stream of data 504, which is provided to an exclusive OR (XOR) circuit 506. The XOR circuit 506 is also coupled to a multiplexer 508. The multiplexer 508 selects between a zero input 510 and a one input 512 as enabled by an enable input 514 from a scramble enable register 516. Thus, the XOR circuit 506 outputs a scrambled stream of data 517. Additionally, a LFSR 518 may provide a signal 520 to the one input 512 of the multiplexer 508. An offset may be provided to the LFSR 518 through an offset circuit 522. The offset selects which value of the LFSR 518 is provided in the signal 520. In an exemplary aspect, the LFSR 518 is based on a PRBS defined by the SOUNDWIRE specification. That is, the LFSR 518 reuses a value already present in the source data port 500. The LFSR 518 includes a reset input 524, which, when a channel is activated, enables use of the LFSR 518 to output the signal 520.

[0038] Similarly, Figure 6 illustrates a sink data port 600 associated with an audio sink (e.g., the master device 104 or the slave device 106(3), which is a speaker). The sink data port 600 provides an incoming stream of data 604, which is provided from an XOR circuit 606. The XOR circuit 606 receives inputs from a stream of scrambled data, which may be the scrambled stream of data 517 of Figure 5. The XOR circuit 606 also receives an input from a multiplexer 608. The multiplexer 608 selects between a zero input 610 and a one input 612 as enabled by an enable input 614 from a scramble enable register 616. Additionally, a LFSR 618 may provide a signal 620 to the one input 612 of the multiplexer 608. An offset may be provided to the LFSR 618 through an offset circuit 622. The offset selects which value of the LFSR 618 is provided in the signal 620. In an exemplary aspect, the LFSR 618 is based on a PRBS defined by the SQUNDWIRE specification. That is, the LFSR 618 reuses a value already present in the sink data port 600. The LFSR 618 includes a reset input 624, which, when a channel is activated, enables use of the LFSR 618 to output the signal 620. The LFSR 618 will be programmed to match the LFSR 518 such that the scrambling added in the source data port 500 of the audio source is descrambled at the sink data port 600 of the audio sink. This scrambling will make the audio sources independent of one another such that the current induced crosstalk will be mitigated or eliminated.

[0039] Exemplary aspects of the present disclosure, use, for example, the hardware described in Figures 5 and 6 to provide corresponding methods 700 and 750 described with reference to Figures 7A and 7B, respectively. At the audio source, the method 700 enables the output signal 520 from the LFSR 518 (including any offset) (block 702) and then uses the XOR circuit 506 to scramble the data stream with the output signal 520 (block 704). The scrambled stream of data 517 is then provided to the audio bus (block 706). Similarly, at the audio sink, the method 750 enables the output signal 620 from the LFSR 618 (including any offset) (block 752) and uses the XOR circuit 606 to descramble the data stream with the output signal 620 (block 754) The descrambled stream of data 604 is then provided for use in the audio sink (block 756). It should be appreciated that there is an initial phase in which the LFSR value is synchronized across the ports. This synchronization occurs at a reset, which occurs following a successful bank-switch. Thus, while not illustrated, there is a reset of the LFSR just before the port is activated, such that the output of the LFSR is identical on both sides of the traffic [0040] The description of Figures 5-7B generally focuses on devices (e.g., audio sources or audio sinks) having a single port. The present disclosure is also applicable to situations where an audio source has multiple ports or situations where there are multiple audio sources (e.g., multiple microphones). In this regard, Figure 10 provides a simplified block diagram of a computing system 1000 that has multiple audio sources including at least one audio source having two ports. Figure 11 provides a flowchart illustrating a configuration process where offsets are varied for different ports within a system having multiple ports.

[0041] With reference to Figure 10, the computing system 1000 may include an application processor 1002 or other master device for an audio bus 1004, which may be a SOUNDWIRE, SOUND WIRE NEXT, or comparable audio bus. The application processor 1002 may act as an audio source, providing audio to an audio sink such as a speaker 1006. The application processor 1002 may also act as an audio sink, receiving audio from one or more audio sources, such as microphones 1008(1)-! 008(3). While microphone 1008(2) has a single port I008(2)A, microphones 1008(1) and 1008(3) each have two ports (e.g., ports 1008(1)A, 1008(1)B and 1008(3 )A, 1008(3 )B, respectively). It should be appreciated that each of the ports 1008(l)A-l 008(3 )B may be a source data port 500 as illustrated in Figure 5 with its own LFSR 518 which may provide respective signals 520 to the one input 512 of the respective multiplexer 508. Likewise, each port may include its own offset circuit 522 The offset circuit 522 selects which value of the LFSR 518 is provided in the signal 520. In an exemplary aspect, each port has a unique offset to help prevent potential crosstalk. That is, for example, the port 1008(l)A has a different offset than the port 1008(1)13 which has a different offset than the port 1008(2)A which has a different offset than the port 1008(3 )A which has a different offset the port 1008(3 )A. To enable transport of an audio stream from an audio source to audio sinks, on the master side, every sink port which corresponds with one of the source ports has to be configured to use a same offset value as configured in the corresponding source.

[0042] The offsets are set to be different during configuration as better illustrated by the flowchart of process 1 100 illustrated in Figure 11. In this regard, the process 1 100 begins at power start, power reset, or the like with the application processor 1002 (or other bus master) configuring the devices 1006, 1008 on the audio bus 1004 (block 1102). As part of the configuration, the application processor 1002 may set the offsets for the different ports of the audio sources (block 1104). The application processor 1002 may further match appropriate offsets in ports for the audio sinks (block 1106), and operation begins (block 1108) such as by beginning processes 700, 750.

[0043] The systems and methods for scrambling data-port audio in SOUNDWIRE, systems according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart wateh, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

[0044] Exemplary aspects of the present disclosure are well suited for use with a SOUNDWIRE NEXT bus. There are a variety of locations in a computing device at which a SOUNDWIRE NEXT bus may be placed. In this regard, Figures 8A-8C illustrate various placements. In most instances, the overall architecture is the same. In this regard, Figure 8A is system-level block diagram of an exemplary mobile terminal 800 such as a smart phone, mobile computing device tablet, or the like. While a mobile terminal is particularly contemplated as being capable of benefiting from exemplary' aspects of the present di sclosure, it should be appreciated that the present di sclosure is not so limited and may be useful in any system having a multi-drop differential bus without satisfactory wake-up and bus reset processes. For the sake of illustration, it is assumed that a SOUNDWIRE NEXT bus 826, which may be the bus 102, within the mobile terminal 800 is among multiple communication buses configured to use the in- band reset and wake-up processes on a differential audio bus according to the present disclosure.

[0045] With continued reference to Figure 8A, the mobile terminal 800 includes an application processor 804 (sometimes referred to as a host) that communicates with a mass storage element 806 through a universal flash storage (UFS) bus 808. The application processor 804 may further be connected to a display 810 through a display serial interface (DSI) bus 812 and a camera 814 through a camera serial interface (CSI) bus 816. Various audio elements such as a microphone 818, a speaker 820, and an audio codec 822 may be coupled to the application processor 804 through a serial low power interchip multimedia bus (SLIMbus) 824. Additionally, the audio elements may communicate with each other and the audio codec 822 through the SOUNDWIRE NEXT bus 826. A modem 828 may also be coupled to the SLIMbus 824 The modem 828 may further be connected to the application processor 804 through a peripheral component interconnect (PCI) or PCI express (PCIe) bus 830 and/or a system power management interface (SPMI) bus 832. Note that the SLIMbus 824 may be replaced by a SOUND WIRE bus in some implementations.

[0046] With continued reference to Figure 8 A, the SPMI bus 832 may also be coupled to a wireless local area network (WLAN) integrated circuit (IC) (WLAN IC) 834, a power management integrated circuit (PMIC) 836, a companion integrated circuit (sometimes referred to as a bridge chip) 838, and a radio frequency integrated circuit (RFIC) 840. It should be appreciated that separate PCI buses 842 and 844 may also couple the application processor 804 to the companion integrated circuit 838 and the WLAN IC 834. The application processor 804 may further be connected to sensors 846 through a sensor bus 848 The modem 828 and the RFIC 840 may communicate using a bus 850.

[0047] With continued reference to Figure 8A, the RFIC 840 may couple to one or more radio frequency front end (RFFE) elements, such as an antenna tuner 852, a switch 854, and a power amplifier 856 through an RFFE bus 857. Additionally, the RFIC 840 may couple to an envelope tracking power supply (ETPS) 858 through a bus 860, and the ETPS 858 may communicate with the power amplifier 856. Collectively, the RFFE elements, including the RFIC 840, may be considered an RFFE system 862. It should be appreciated that the RFFE bus 857 may be formed from a clock line and a data line (not illustrated).

[0048] Figure 8B illustrates an alternate placement of the SOUNDWIRE NEXT bus. While the majority of the elements are the same as the mobile terminal 800, the mobile terminal 800B illustrated in Figure 8B has a SOUNDWIRE bus 826B coupling the audio codec 822 to the microphone(s) 818 and the speaker(s) 820. The application processor 804 may be coupled to a SOUNDWIRE NEXT bus 870 that may couple to an optional bridge 872. If the bridge 872 is present, then the bus 874 may be a SOUNDWIRE bus. If the bridge 872 is not present, then the SOUNDWIRE NEXT bus 870 may couple directly to microphones 8I8B, speakers 820B, and/or an audio codec 822B

[0049] Similarly, Figure 8C illustrates another alternate placement of the SOUNDWIRE NEXT bus. In the mobile terminal 800C, the audio codec 822 may couple to a SOUNDWIRE bus 826C and a SOUNDWIRE NEXT bus 880. The SQUNDWIRE NEXT bus 880 may couple to microphones 818C and speakers 820C.

[0050] It should be appreciated that the LFSR 518 of Figure 5 and the LFSR 618 of Figure 6 may have the same PRBS stored therein. In an exemplary aspect, the PRBS is the PRBS defined by the SOUNDWIRE specification as illustrated by Table 105 of the specification and reproduced as Figure 9.

[0051] Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may he implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. The devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0052] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration). [0053] The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplar}' storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0054] It is also noted that the operational steps described in any of the exemplary' aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0055] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.