Title:
SEMICONDUCTOR CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2021/161681
Kind Code:
A1
Abstract:
In the present invention, at least one semiconductor chip (10) of all semiconductor chips (10) mounted on an insulating substrate (80) has, on the front surface thereof, a layout of electrode pads (21a, 21b, 22, 23a, 23b) that is different from other semiconductor chips, and therefore there are at least two layout patterns. The entire layout of the semiconductor chips (10) mounted on the insulating substrate (80) and the layout of the electrode pads (21a, 21b, 22, 23a, 23b) on the front surfaces of the semiconductor chips (10) are determined such that: the length of wiring (96) connecting main semiconductor elements (11) in parallel becomes as short as possible; the resistance component and the reactance component generated by the wiring (96) becomes substantially consistent between the same type of electrode pads (21b) of the plurality of semiconductor chips (10) connected in parallel; or both of the foregoing are satisfied. Due to this configuration, it is possible to suppress vibration of current waveforms between semiconductor devices (20) fabricated on the plurality of semiconductor chips (10).
Inventors:
HOSHI YASUYUKI (JP)
Application Number:
PCT/JP2020/049244
Publication Date:
August 19, 2021
Filing Date:
December 28, 2020
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD (JP)
International Classes:
H01L23/48; H01L21/3205; H01L21/336; H01L21/768; H01L21/822; H01L21/8234; H01L23/522; H01L25/07; H01L25/18; H01L27/04; H01L27/06; H01L27/088; H01L29/12; H01L29/78
Foreign References:
| JP2014120638A | 2014-06-30 | |||
| JP2019149477A | 2019-09-05 | |||
| JP2018117025A | 2018-07-26 | |||
| JP2011254387A | 2011-12-15 |
Attorney, Agent or Firm:
SAKAI, Akinori (JP)
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