SEMICONDUCTOR DEVICE, ELECTRONIC EQUIPMENT, AND ARTIFICIAL SATELLITE

WIPO Patent Application WO/2020/128673

A1

The purpose of the present invention is to provide a low power consumption semiconductor device. According to the present invention, a retention transistor is provided between a control circuit and an output transistor. An output terminal of the control circuit is electrically connected to one of the source and the drain of the retention transistor, and the other of the source and the drain of the retention transistor is electrically connected to the gate of the output transistor. The node at which the other of the source and the drain of the retention transistor is electrically connected to the gate of the output transistor is set as a retention node. When the retention transistor is set in an ON state, a potential corresponding to the potential output from the control circuit is written to the retention node. Then if the retention transistor is set in an OFF state, the potential at the retention node is retained. Therefore, the gate potential of the output transistor can be maintained at a constant value even if the control circuit is turned off. Accordingly, for example, a constant potential can continue to be output from either the source or the drain of the output transistor even if the control circuit is turned off.

SATO KEITA
YAKUBO YUTO (JP)
OIKAWA YOSHIAKI (JP)
YAMAZAKI SHUNPEI (JP)

PCT/IB2019/059860

June 25, 2020

November 18, 2019

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SEMICONDUCTOR ENERGY LAB (JP)

G05F1/56

JP2009032278A	2009-02-12
JPH11224496A	1999-08-17
JP2003029854A	2003-01-31
JP2013235564A	2013-11-21
US8954767B2	2015-02-10

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