Title:
SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING SAME
Document Type and Number:
WIPO Patent Application WO/2020/080124
Kind Code:
A1
Abstract:
This semiconductor element comprises an element substrate having an element region at a central portion thereof and a peripheral region outside the element region, and a readout circuit board facing the element substrate, the element substrate including: a first semiconductor layer provided in the element region and containing a compound semiconductor material; a wiring layer provided between the first semiconductor layer and the readout circuit board and electrically connecting the first semiconductor layer and the readout circuit board; a first passivation film provided between the wiring layer and the first semiconductor layer; and a second passivation film facing the first passivation film with the first semiconductor layer interposed therebetween, wherein the peripheral region of the element substrate has a bonding surface with the readout circuit board.
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Inventors:
MATSUMOTO RYOSUKE (JP)
Application Number:
PCT/JP2019/039139
Publication Date:
April 23, 2020
Filing Date:
October 03, 2019
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L31/10; H01L27/146; H04N5/369
Domestic Patent References:
| WO2018139110A1 | 2018-08-02 | |||
| WO2018016181A1 | 2018-01-25 |
Foreign References:
| JP2017126738A | 2017-07-20 | |||
| JP2015115420A | 2015-06-22 | |||
| JP2009065163A | 2009-03-26 | |||
| US20080308888A1 | 2008-12-18 | |||
| JP2013135123A | 2013-07-08 | |||
| JP2018037611A | 2018-03-08 | |||
| JP2014521216W | ||||
| JP2018195110A | 2018-12-06 |
Other References:
See also references of EP 3869561A4
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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