Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2021/075434
Kind Code:
A1
Abstract:
According to the present invention, a terminal cell (C11) is provided with: nano sheets (122a, 123a) which are respectively formed at the same positions as nano sheets (22a, 23a) in a Y-direction; and dummy gate wirings (143, 146) which respectively surround the peripheries of the nano sheets (122a, 123) in the Y-direction. Side surfaces on one side in the Y-direction of the nano sheets (22a, 122a) are respectively exposed from a gate wiring (41) and the dummy gate wiring (142). Side surfaces on one side in the Y-direction of the nano sheets (23a, 123a) are respectively exposed from a gate wiring (43) and the dummy gate wiring (146).
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Inventors:
NAKAOKA YASUHIRO (JP)
Application Number:
PCT/JP2020/038662
Publication Date:
April 22, 2021
Filing Date:
October 13, 2020
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H01L21/82
Domestic Patent References:
WO2018025580A1 | 2018-02-08 | |||
WO2018003634A1 | 2018-01-04 | |||
WO2018074172A1 | 2018-04-26 |
Foreign References:
US20160111337A1 | 2016-04-21 | |||
JP2009016525A | 2009-01-22 | |||
JPH0567634A | 1993-03-19 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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