Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2020/250334
Kind Code:
A1
Abstract:
A semiconductor integrated circuit has: an output buffer that outputs a memory control signal to an external terminal; a power source control unit that controls the supply of power source voltage to the output buffer; a pull-up control unit that controls the pull-up of the external terminal; and a control signal generation unit. The control signal generation unit: during an output period for outputting the memory control signal to the external terminal, generates a power source control signal that causes power source voltage to be supplied to the output buffer by the power source control unit, and a pull-up control signal that stops pull-up by the pull-up control unit; and, during an idle period in which the memory control signal is not outputted to the external terminal, generates a power source control signal that stops the supply of the power source voltage to the output buffer by the power source control unit, and a pull-up control signal that pulls up the external terminal. This makes it possible to prevent the output terminal from being in a high-impedance state when the output terminal is set to a prescribed voltage in accordance with the output signal outputted from the output terminal.
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Inventors:
OKINOI MASANORI (JP)
OGAWA SACHIO (JP)
AZUMAI RYO (JP)
HAMASAKI KIICHI (JP)
OGAWA SACHIO (JP)
AZUMAI RYO (JP)
HAMASAKI KIICHI (JP)
Application Number:
PCT/JP2019/023240
Publication Date:
December 17, 2020
Filing Date:
June 12, 2019
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
G11C7/22; G06F12/00; G11C16/32; H03K19/0175
Foreign References:
JP2006279273A | 2006-10-12 | |||
JP2015011730A | 2015-01-19 | |||
JPH1050070A | 1998-02-20 | |||
JPH10320089A | 1998-12-04 | |||
JP2012230621A | 2012-11-22 |
Attorney, Agent or Firm:
ITOH, Tadashige et al. (JP)
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