Title:
SEMICONDUCTOR WAFER POLISHING AUXILIARY SHEET AND PRODUCTION METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2020/095883
Kind Code:
A1
Abstract:
Provided are: a semiconductor wafer polishing auxiliary sheet that can be prevented from being polished away along with a semiconductor wafer and that is capable of preventing a semiconductor wafer from being contaminated or damaged due to contact with polishing chips; and a production method therefor. This semiconductor wafer polishing auxiliary sheet 21 is used to prevent a semiconductor wafer 1 from sticking out during polishing in a CMP process performed on the semiconductor wafer 1 by a polishing apparatus 10, and is obtained by directly stacking a plurality of polyether ether ketone resin sheets 22 and integrally molding the same by fusion-bonding. Since the polishing auxiliary sheet 21 is made from the polyether ether ketone resin sheets 22 having excellent abrasion resistance, sliding properties and the like, it is possible to prevent the polishing auxiliary sheet 21 from being polished away along with the surface 2 of the semiconductor wafer 1 and to reduce the amount of polishing chips generated.
Inventors:
ASO TSUTOMU (JP)
SUDA NOBUMITSU (JP)
TAKISE KIYOSHI (JP)
SUDA NOBUMITSU (JP)
TAKISE KIYOSHI (JP)
Application Number:
PCT/JP2019/043227
Publication Date:
May 14, 2020
Filing Date:
November 05, 2019
Export Citation:
Assignee:
SHINETSU POLYMER CO (JP)
International Classes:
B24B37/30; H01L21/304
Domestic Patent References:
| WO2010119847A1 | 2010-10-21 |
Foreign References:
| JP2006255861A | 2006-09-28 | |||
| JPH06341012A | 1994-12-13 |
Attorney, Agent or Firm:
FUJIMOTO Eisuke et al. (JP)
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