Title:
SIGNAL PROCESSING USING TIMING COMPARISON
Document Type and Number:
WIPO Patent Application WO/2010/032184
Kind Code:
A3
Abstract:
A signal processing module with a timing comparator such as a time to digital converter is provided. The module may be part of a phase locked loop with a fractional frequency divider that acts to produce a divided down signal modulated with jitter in its timing. The timing comparator comprises an error cancellation stage (30, 24.1, 2060) to remove a predicted effect of the imparted jitter from the timing comparator output signal. A jitter detector (80, 1046, 2064) is used to detect the jitter from the comparator output signal, preferably residual jitter after the predicted effect of the jitter has been removed. Synchronous detection, such as correlation with the predicted jitter may be used to detect the jitter. The jitter detector (80, 1046, 2064) adjusts a calibration factor of the timing comparator dependent on the detected jitter. Adjustment of the calibration factor may involve adjustment of a reference time delaydefined by a time delay element in a time to digital converter, application of a calibration factor to the result of timing comparison or application of a calibration factor to the predicted jitter.
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Inventors:
LUCAS MICKAEL (FR)
UGUEN EMERIC (FR)
UGUEN EMERIC (FR)
Application Number:
PCT/IB2009/053984
Publication Date:
June 24, 2010
Filing Date:
September 11, 2009
Export Citation:
Assignee:
NXP BV (NL)
LUCAS MICKAEL (FR)
UGUEN EMERIC (FR)
LUCAS MICKAEL (FR)
UGUEN EMERIC (FR)
International Classes:
H03L7/197
Domestic Patent References:
| WO2003088485A1 | 2003-10-23 |
Foreign References:
| US20080048791A1 | 2008-02-28 | |||
| US20070075785A1 | 2007-04-05 |
Attorney, Agent or Firm:
KROTT, Michel Willy François Maria (Intellectual Property & Licensing DepartmentHigh Tech Campus 32, AE Eindhoven, NL)
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