Field of the Invention

This invention relates to a spatial light modulator that comprises a pixel array having a plurality of pixels whereby each pixel in this array is communicatively coupled to a digital pixel circuit which are in turn all coupled to a bit-plane control circuit. The bit-plane control circuit is configured to generate, using a Pulse Code Modulation (PCM) algorithm, bit-plane signals that are used to control the sample and hold functions performed by each of the digital pixel circuits so that the pixel array may carry out its scanning function accurately and in a power efficient manner.

Summary of the Prior Art

A Spatial Light Modulator (SLM) is an electronic device that is used to modulate amplitude, phase, and/or polarization of light waves in space and time. Phase-only SLMs are commonly used in adaptive focus depth devices and/or holographic 3D displays that are found in near-eye augmented reality (AR) glasses, automotive heads-up displays (HUDs), holotables/boxes, or focal surface virtual reality (VR) head-mounted displays (HMDs).

Currently, most of the fast response time SLM-based systems utilize optical microelectromechanical systems (MEMS) or Liquid Crystal Display (LCD) techniques. Due to the binary phase modulation utilized by the MEMS systems, the quality of the reconstructed image is compromised due to the occurrence of significant quantization noise. As a result, liquid crystal based technology has been widely adopted as it provides a good balance between the modulation of light intensity, phase, polarization rotation, and electrically controlled birefringence (ECB) of the signals that are to be displayed. This technology also allows a large number of pixels to be provided on a small display panel due to the use of a silicon backplane.

In conventional LCD systems, high driving voltages are usually required due to the low electron mobility of Thin Film Transistors (TFT), which are typically in the range between 0.2 and 1.5 cm ² /Vs for TFTs. As a reference, the mobility of Complementary Metal Oxide Semiconductor (CMOS) transistors are usually between 10 and 50 cm ² /Vs. However, in order to achieve the required phase modulation of the driving signals, the thickness of the liquid crystal layer has to be double the thickness of a liquid crystal layer that is designed to achieve the required amplitude modulation of the driving signals. Those skilled in the art have also proposed the use of pixel circuits that are each coupled to a pixel in the pixel array whereby each pixel circuit comprises a Dynamic Random Access Memory (DRAM) circuit that is coupled to a capacitor. The downside of such a DRAMbased circuit is that it is sensitive to charge leakage as such, large capacitors are usually utilized to supress the influence of charge leakage, thereby increasing the overall size of the circuit.

For those above reasons, those skilled in the art are constantly trying to implement CMOS driving schemes that do not require a thick liquid crystal layer and do not require pixel arrays with overly large sizes.

Summary of the Invention

The above and other problems are solved and an advance in the art is made by systems and methods provided by embodiments in accordance with the invention.

A first advantage of embodiments of a spatial light modulator and a method for modulating spatial light in accordance with the invention is that the pixel array is small in size and does not require large areas on an integrated circuit (IC) chip.

A second advantage of embodiments of a spatial light modulator and a method for modulating spatial light in accordance with the invention is that modulator consumes less power due to its lower clock frequency.

A third advantage of embodiments of a spatial light modulator and a method for modulating spatial light in accordance with the invention is a voltage driver circuit used to drive a voltage at the top plate of the liquid crystal layer of the pixel array may be integrated into the modulator thereby saving space on the IC chip.

A fourth advantage of embodiments of a spatial light modulator and a method for modulating spatial light in accordance with the invention is that the modulator does not require the use of a complicated Digital-to-Analog converter array thereby reducing the overall size of the modulator and reducing the overall power consumption of the system.

The above advantages are provided by embodiments of a modulator or a method of using the modulator in accordance with the invention operating in the following manner.

According to a first aspect of the invention, a spatial light modulator is disclosed, the spatial light modulator comprising: a pixel array having a plurality of pixels whereby each pixel is communicatively connected to a digital pixel circuit whereby each digital pixel circuit comprises: a Static Random Access Memory (SRAM) circuit configured to receive column data signals and a clock row enable signal, ck row, whereby the SRAM circuit is triggered by the clock row enable signal, ck row, to sample the received column data signals; a hold buffer circuit coupled to an output of the SRAM circuit, the hold buffer circuit configured to receive a clock hold signal, ck_hold, whereby the hold buffer circuit is triggered by the clock hold signal, ck_hold, to receive and store the sampled signal from the output of the SRAM circuit.

With regard to the first aspect of the invention, the spatial light modulator further comprises a bit-plane control circuit communicatively connected to all the digital pixel circuits, the bit-plane control circuit being configured to: generate, using a pulse code modulation (PCM) scheme, bit-plane signals, whereby each bit-plane signal comprises a variable holding time component for triggering the hold buffer circuit in each of the digital pixel circuits for a variable time period THOICLN, and a predetermined addressing time component for triggering the SRAM circuit in each of the digital pixel circuits for a predetermined time period T dd.

With regard to the first aspect of the invention, the addressing time component is predetermined based on a unit duration of a Least Significant Bit (LSB) of a bit-plane signal and a pixel multiplier, OP wherein the pixel multiplier, OP is based on numbers of rows and columns, and data input-output ports of the pixel array.

With regard to the first aspect of the invention, the pixel multiplier, OP, is defined as

With regard to the first aspect of the invention, each pixel in the pixel array comprises a liquid crystal layer provided between an indium tin oxide (ITO) electrode and a pixel electrode, whereby the ITO electrode is configured to receive an alternating voltage and the pixel electrode is connected to an output of the digital pixel circuit.

With regard to the first aspect of the invention, each pixel in the pixel array comprises a liquid crystal layer provided between an indium tin oxide (ITO) electrode and a pixel electrode, whereby the pixel electrode is connected to an output of the digital pixel circuit and the ITO electrode is configured to receive an alternating voltage from the bit-plane control circuit, whereby the alternating voltage is synchronized with an output signal at the output of the digital pixel circuit.

With regard to the first aspect of the invention, the spatial light modulator according to claim 1 whereby the hold buffer circuit comprises: a first and a third transistor having input gates coupled to the output of the SRAM circuit; a second and a fourth transistor having input gates configured to receive a clock hold signal, ck_hold, whereby a drain node of the second transistor is coupled to a source node of the first and third transistors.

With regard to the first aspect of the invention, a transistor of the hold buffer circuit is shared between two or more digital pixel circuits.

According to a second aspect of the invention, a method for modulating spatial light using a spatial light modulator that has a pixel array which comprises a plurality of pixels whereby each pixel is communicatively connected to a digital pixel circuit is disclosed, the method comprising receiving, using a Static Random Access Memory (SRAM) circuit provided within each digital pixel circuit, column data signals and a clock row enable signal, ck_row, whereby the SRAM circuit is triggered by the clock row enable signal, ck_row, to sample the received column data signals; receiving, using a hold buffer circuit coupled to an output of the SRAM circuit, a clock hold signal, ck_hold, whereby the hold buffer circuit is triggered by the clock hold signal, ck_hold, to receive and store the sampled signal from the output of the SRAM circuit.

With regard to a second aspect of the invention, the method further comprises the step of generating, using a bit-plane control circuit communicatively connected to all the digital pixel circuits, bit-plane signals based on a pulse code modulation (PCM) scheme, whereby each bit-plane signal comprises a variable holding time component for triggering the hold buffer circuit in each of the digital pixel circuits for a variable time period THOICLN, and a predetermined addressing time component for triggering the SRAM circuit in each of the digital pixel circuits for a predetermined time period TACM.

With regard to a second aspect of the invention, the addressing time component is predetermined based on a unit duration of a Least Significant Bit (LSB) of a bit-plane signal and a pixel multiplier, a _P wherein the pixel multiplier, a _P is based on numbers of rows and columns, and data input-output ports of the pixel array.

With regard to a second aspect of the invention, the pixel multiplier, a _P , is defined as

With regard to a second aspect of the invention, each pixel in the pixel array comprises a liquid crystal layer provided between an indium tin oxide (ITO) electrode and a pixel electrode, whereby the ITO electrode is configured to receive an alternating voltage and the pixel electrode is connected to an output of the digital pixel circuit. With regard to a second aspect of the invention, each pixel in the pixel array comprises a liquid crystal layer provided between an indium tin oxide (ITO) electrode and a pixel electrode, whereby the pixel electrode is connected to an output of the digital pixel circuit and the ITO electrode is configured to receive an alternating voltage from the bit-plane control circuit, whereby the alternating voltage is synchronized with an output signal at the output of the digital pixel circuit.

With regard to a second aspect of the invention, the hold buffer circuit comprises: a first and a third transistor having input gates coupled to the output of the SRAM circuit; a second and a fourth transistor having input gates configured to receive a clock hold signal, ck_hold, whereby a drain node of the second transistor is coupled to a source node of the first and third transistors.

With regard to a second aspect of the invention, a transistor of the hold buffer circuit is shared between two or more digital pixel circuits.

Brief Description of the Drawings

The above advantages and features in accordance with this invention are described in the following detailed description and are shown in the following drawings:

Figure 1 illustrating a block diagram of a spatial light modulator system in accordance with embodiments of the invention;

Figure 2 illustrating a circuit diagram of a digital pixel circuit in accordance with embodiments of the invention;

Figure 3 illustrating bit-plane signals generated by a pulse code modulation (PCM) algorithm in accordance with embodiments of the invention;

Figure 4 illustrating a timing diagram of bit-plane signals generated by the PCM algorithm in accordance with embodiments of the invention;

Figure 5 illustrating timing diagrams of pixel addressing and holding in accordance with an embodiment of the invention;

Figure 6 illustrating a side cut-out view of a pixel array in accordance with embodiments of the invention;

Figure 7 illustrating a timing diagram of a voltage driver in accordance with embodiments of the invention; and Figure 8 illustrating a timing diagram of a voltage driver when the voltage driver is synchronized with the system clock of the modulator in accordance with embodiments of the invention.

Detailed Description

This invention relates to a spatial light modulator that comprises a pixel array having a plurality of pixels whereby each pixel in this array is communicatively coupled to a digital pixel circuit which are in turn all coupled to a bit-plane control circuit. Each digital pixel circuit comprises a Static Random Access Memory (SRAM) circuit coupled to a hold buffer circuit. The SRAM circuit is configured to sample received signals when triggered with an appropriate clock signal and the hold buffer circuit is configured to receive and hold the sampled signal from the SRAM circuit when triggered with another appropriate clock signal.

The bit-plane control circuit is configured to generate, using a Pulse Code Modulation (PCM) algorithm, bit-plane signals that are used to trigger the sample and hold functions performed by each of the digital pixel circuits so that the pixel array may carry out its scanning function accurately and in a power efficient manner.

Figure 1 illustrates a block diagram of a spatial light modulator (SLM) system in accordance with embodiments of the invention. SLM system 100 in general comprises controller 105 which is configured to control the signals generated by data multiplier 115 and bit-plane control circuit 110, and pixel array 130 which comprises a plurality of digital pixel circuits 132 that are each in turn connected to liquid crystal (LC) layer 133. Pixel array 130 is the most important block in SLM system 100, as its performance influences the system’s optical response directly. In embodiments of the invention, digital pixel circuits 132 are SRAMbased thereby negating the need for large holding capacitors as those used in Dynamic Random Access Memory (DRAM)-based pixel circuit designs, which make such digital pixel circuits 132 compact and suitable for process scaling.

As illustrated in Figure 1 , pixel array 130 is configured to receive data and/or information from data multiplier 1 15 and bit-place control circuit 110. In particular, data multiplier 115 is configured to provide a plurality of column data signal pairs 120a and 120b to the plurality of pixel circuits 132 in pixel array 130. As for bit-plane control circuit 1 10, this circuit is configured to provide bit-plane signals 122a/122b that are generated using a Pulse Code Modulation (PCM) algorithm to the plurality of pixel circuits 132 to control the sample and hold functions performed by each of pixel circuits 132. In embodiments of the invention, controller 105 may comprise a state machine, counters, data registers, decoders, a deserializer, a clock generator, driving circuits, memories and all other modules required by a controller to perform functions known in the art. The exact operation and workings of controller 105 is omitted for brevity as its functions and internal modules/circuits are known to those skilled in the art.

In conventional SLM systems, the driving voltages used to drive pixel circuits 132 are usually greater than 5 volts. As such, there exists a trade-off between the power consumption of the modules in the SLM system and the system’s driving ability (e.g. the LC layer’s settling time, etc.) of the pixel circuits. In other words, when pixel circuits 132 are driven with a high voltage, this boosts the switching speed of the liquid crystal layer, but negatively causes an increase in power dissipation of the driving circuits. As such, in view of the above trade-off, level shifters (not shown) are included in SLM system 100 to accommodate the supply voltage difference between the voltage used by controller 105 and the voltages used to drive pixel circuits 132 in pixel array 130. For example, when standard 40nm CMOS processes are employed, the typical digital voltage DD of controller 105 would be around 1.1 volts. As such, when the voltage threshold of the liquid crystal layer is greater than 3 volts (e.g. for typical twisted nematic effect (TN-effect) liquid crystal layers), the level shifters would be employed to convert the driving signals (which are at 1 .1 . volts) as received from controller 105 to 5 volts.

In embodiments of the invention, SLM system 100 may also include voltage driver VCOM circuit 125 which is configured to generate and provide an alternating voltage to a top layer of the liquid crystal display in pixel array 130. Voltage driver circuit 125 is used to implement field inversion at the liquid crystal layer of pixel array 130 (this is also known as DC balancing), and this is done to prevent the unidirectional flow of ions in the liquid crystal layer. When unidirectional flow of ions occur in the LC layer, a constant charge may be built at the surface of the LC layer and consequently, cause electrolytic degradation of the liquid crystal mixture and affect the modulating properties of pixel array 130. The use of the alternating voltage generated by voltage driver circuit 125 effectively prevents this from happening.

In operation, each row of pixels in pixel array 130 may be addressed by one “wordline” (WL) (e.g. comprising bit-plane signals 122a/122b) and each column of pixels in pixel array 130 may be addressed by a pair of bit-lines (BLs) (i.e. column data signal pairs 120a/120b). As all the pixels in a row are selected and written sequentially, in order to synchronize the addressing of these pixels, all column data that is to be sampled by these pixels should be refreshed every system clock cycle whereby each row of pixels are also addressed based on the same system clock. After all the rows are addressed, pixel array 130 will then be flashed (illuminated), and the flashing of pixel array 130 is controlled by bit-plane signals 122a/122b as generated by bit-plane control circuit 110.

Figure 2 illustrates a digital pixel circuit 200, whereby each digital pixel circuit is communicatively coupled to a pixel in the pixel array to control the pixel in accordance with embodiments of the invention. In particular, digital pixel circuit 200 comprises a Static Random Access Memory (SRAM) circuit 210 and hold buffer circuit 230. SRAM circuit 210 comprises transistors 208, 209, 211 , 212, 216, and 217, whereby the drain of transistors 21 1 and 216 are connected to a high voltage VDDA and the source of transistors 212 and 217 are connected to voltage V _S SA that is relatively lower than the voltage VDDA. One skilled in the art will recognize that these transistors may comprise Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) or any other types of transistors without departing from the invention.

In embodiments of the invention, as illustrated in Figure 2, transistors 211 , 212, 216 and 217 are configured as two cross-coupled inverters. During normal operation of the SRAM circuit, transistors 208 and 209 act as access transistors, controlling the access to the “storage-transistors” 211 , 212, 216 and 217. In particular, access to SRAM circuit 210 is enabled by the ck_row input port 204 which controls the access transistors 208 and 209. When these access transistors 208 and 209 are enabled, SRAM circuit 210 will sample signals from col_data input port 202 and col_datan input port 206 and the sampled signals will be stored at nodes QB and Q respectively. Typically, the signal sampled at node QB will be the inverse of the signal sampled at Q and this is done in order to improve noise margins.

Hold buffer circuit 230 comprises transistors M1 , M2, M3 and M4. As illustrated in Figure 2, the inputs to transistors M1 and M3 are coupled to node Q of SRAM circuit 210 while the inputs of transistors M2 and M4 are coupled to cknjiold port 238. A drain node of the transistor M2 is coupled to a source node of transistors M1 and M3. This means that when ckn hold port 238 is at a high voltage level, transistor M2 will be switched on and as a result, the output node V _L c will be reset to ground, i.e. the pixel will be in a reset mode. Conversely, when ckn_hold port 238 is at a low voltage level, transistor M4 will be switched on and transistor M2 will be switched off. This causes the voltage level at node Q to be transferred to the output node V _L c through transistors M1 and M3.

In operation, in a first phase, ck row port 204 will receive a high voltage level thereby enabling the addressing function of circuit 200. When this happens, data signals provided at col_data port 202 and col_datan port 206 will be sampled by SRAM circuit 210. These sampled signals will be stored at nodes QB and Q respectively. At this time, a high voltage level will be provided to ckn hold port 238 ensuring that the voltage level at node V _L c is reset to ‘ground’ by transistor M ₂ .

In a second phase, a low voltage level is provided to ck_row port 204 thereby disabling the addressing function of circuit 200. When a low voltage level is provided to ckn hold port 238, circuit 200 will now be in its holding phase. When this happens, the sampled signal at node Q of SRAM circuit 210 will be transferred to hold buffer circuit 230 by transistor M3 and depending of the sampled signal at node Q, the voltage level at node V c will be toggled high (from the ground state) or will remain low.

Additionally, as highlighted by a circle, transistor M4 is different from the other transistors in hold buffer circuit 230. As the source of M ₄ is always connected to a high voltage VDDA, and as the gate of M ₄ is controlled by ckn_hold, transistor M ₄ can be shared by two or more digital pixel circuits 200. This means that in certain embodiments of the invention, two adjacent pixels may share a single transistor M ₄ thereby reducing the number of transistors required and thus the IC layout area of the pixel array. The sharing of transistor M ₄ between two or more digital pixel circuits also reduces the overall power consumption of the pixel array due to the reduced switching load applied to ckn_hold port 238 and also reduces the amount of surge current drawn from the voltage source VDDA when the cknjiold voltage transients from high-to-low.

For example, in embodiments of the invention, each digital pixel circuit may only require 9.5 transistors, two data pins, and two clock pins thereby simplifying the design of the circuit and reducing the layout area of all the digital pixel circuits in the pixel array.

Generation of Bit-Plane signal using Pulse Code Modulation (PCM) algorithm

In embodiments of the invention, when an alternating current (AC) driving voltage is applied to the liquid crystal (LC) layer of the pixel array through the pixel circuits, the response of the LC layer is dependent on the root-mean-square (RMS) voltage of the signals provided to the pixel circuit. As known to those skilled in the art, when the pulse width is controlled, i.e. when the duty-cycle value of a square wave signal is controlled, the equivalent RMS value of the signal will be related to the square root of the duty-cycle as given by equation (1 ) below. ... Equation (1 ) where V _PP is the peak-to-peak voltage of the applied square wave (which is VDD as illustrated in Figure 2), and the duty-cycle value comprises a percentage value. For example, in order to achieve a V _RM s of 0.5*V _PP , the duty cycle of the modulated pulses should be 25%. Additionally, the equivalent RMS value of the signal may be defined by equations (2a) - (2d) as derived below: where T is the total duration of a complete frame, N is the total number of bit-plane signals, A is the signal-dependent coefficient of each bit-plane, T _D is the duration of a high voltage level in every frame cycle, Tu is the unit duration (i.e. the least significant bit (LSB)) of V _PP , and n is the sum of all signal-dependent coefficients. In embodiments of the invention, when the total resolution of a grey scaled image is 8 bits, N would be equal to 256 (2 ⁸ ), and the maximum pulse duration T corresponding to 256 is 256 ² , which equals to (65536) x Tu.

When a PCM algorithm is used to generate conventional bit-plane signals for a pixel array, a sequence of bit-plane signals will be generated whereby the pulse duration of the first bit-plane signal will have a duration of 2°Tu, the second bit-plane signal will have a duration of 2 ¹ Tu and so on until the 16 ^th bit-plane signal has a pulse duration of 2 ¹⁵ Tu (i.e. for a 16-bit bitplane). As a result, it can been calculated that the total length of the 16-bit bit-plane signal is the sum of all the individual bit-plane pulse durations, which equal to (65535) x Tu.

The generated bit-plane signals may then be used to control the illumination of the pixel array. When the first bit-plane signal having a pulse width 2°Tu is illuminated by the pixel array, the second bit-plane signal having a pulse width 2 ¹ Tu will be addressed or scanned by the pixel circuits. This means that the data relating to the second bit-plane signal will be transferred to each pixel and scanned row by row for the duration of the second bit-plane signal, e.g. 2 ¹ Tu, until the whole pixel array is addressed.

At the next duration, the second bit-plane signal having a pulse width 2 ¹ Tu will be illuminated by the pixel array, and the third bit-plane signal having a pulse width 2 ² Tu will be addressed or scanned by the pixel circuits. This means that the data relating to the third bitplane signal will be transferred to each pixel and scanned row by row for the duration of the third bit-plane signal, e.g. 2 ² Tu, until the whole pixel array is addressed. This repeats until all the bit-plane signals (i.e. 16-bit bit-plane signals in the example above) have been addressed and illuminated by the pixel array.

For example, when a pixel array having 1024 x 768 pixels is utilized, the entire 1024 rows have to be scanned within a time duration of 2 ₀ T ^u , i.e. the pulse duration of the first bitplane signal. Therefore, the shortest addressing time T _rO w for each row has to be Tu/1024. If the frame rate is taken to be 60 hertz, the total addressing time (65535 x Tu) for a 8-bit grey level would equal to a quarter of 1/60, which is 4.17 milliseconds. Hence, Tu would equal to 63.6 nanoseconds, and T _row would be 62.1ps, corresponding to 16.1 GHz. As known to one skilled in the art, the power consumption of digital circuits are proportional to the frequency of the system’s clock. As such, when the system’s clock frequency is 16.1 GHz, this results in considerable power consumption which is not ideal.

In accordance with embodiments of the invention, the PCM algorithm is used to generate new bit-plane signals that are to be used together with digital pixel circuit 200 and the bit-plane signals generated are illustrated in Figure 3. In order to have a system clock that has relatively low frequency, the PCM algorithm is used to generate bit-plane signals that have a fixed addressing time TADD. AS a result, the total duration of a frame, Tf _rame , may be defined in equation (3) below.

Tframe = 2 ¹⁶ T„ + 16 x T _ADD ... Equation (3)

Where it can be seen that in order to achieve a frame rate of 60 hertz, and if the fixed addressing time T DD is set as (1000 x Tu), the value of Tu would be equal to 51.1 ns, i.e. 19.55MHz. Therefore, it can be seen that when the addressing time is fixed, this greatly reduces the system’s clock frequency.

As illustrated in Figure 3, it can be seen that the addressing times for all the bit-plane signals are now fixed and this can be seen from pulse widths 304, 314, 324, 334, 344 which all employ fixed addressing time TADD.

At step 302, when the first bit-plane signal 303 having a pulse width 2°Tu is held by digital pixel circuit 200 for illumination by the pixel array, the second bit-plane signal will be addressed or scanned by pixel circuits 200 for a fixed addressing time TADD, i.e. pulse width 304. This means that the data relating to the second bit-plane signal will be transferred to each pixel and scanned row by row for the duration of the fixed addressing time TADD until the whole pixel array has been addressed. At the next step 312, the second bit-plane signal 313 having a pulse width 2 ¹ Tu will be illuminated by the pixel array, and the third bit-plane signal having a pulse width 2 ² Tu will be addressed by pixel circuits 200 for a fixed addressing time TADD, i.e. pulse width 314. This means that the data relating to the second bit-plane signal will be transferred to each pixel and scanned row by row for the duration of the fixed addressing time TADD until the whole pixel array has been addressed.

This repeats until all the bit-plane signals (i.e. 16-bit bit-plane signals as illustrated in Figure 3) have been addressed and illuminated by the pixel array. At the final step, 342, it can be seen the 16 ^th bit-plane signal 343 having a pulse width 2 ¹⁵ Tu will be illuminated by the pixel array, and the first bit-plane signal belonging to a new set of bit-plane signals having a pulse width 2°Tu will be addressed by pixel circuits 200 for a fixed addressing time TADD, i.e. pulse width 344.

The bit plane signals generated by the PCT algorithm may be summarized into a serial timing diagram as illustrated in Figure 4 where each bit-plane signal comprises a variable holding time component that is used to trigger the hold buffer circuit in each of the digital pixel circuits for a variable time period “BP N” or THoid_N, where “N" represents the number of the bitplane signal, and a predetermined addressing time component for triggering the SRAM circuit in each of the digital pixel circuits for a predetermined time period T DD.

For the avoidance of doubt, the first bit-plane signal is made up of TADD which represents the fixed address period and BP 0 which represents the pulse width 2°Tu of the first bit-plane signal, the second bit-plane signal is made up of TADD and BP 1 which represents the pulse width 2 ¹ T _U of the second bit-plane signal, the third bit-plane signal is made up of TADD and BP 2 which represents the pulse width 2 ² Tu of the third bit-plane signal, the fourth bit-plane signal is made up of T DD and BP 3 which represents the pulse width 2 ³ Tu of the fourth bit-plane signal, the fifth bit-plane signal is made up of TADD and BP 4 which represents the pulse width 2 ⁴ Tu of the fifth bit-plane signal, and so on.

Example 1 : Timing Calculation for a 768 x 1024 Pixel Array having 32 data inputs/outputs.

When the method of generating the bit-plane signals as illustrated in Figures 3 and 4 are used, the total duration of a frame Tf _ra me for a 768 x 1024 pixel array may be computed as follows. The total duration of a frame may be obtained by equation (3) as: If the system clock is 150MHz, 7; is 1/150MHz=6.7ns, where TADD is a _P x Tu, where a _P is the pixel multiplier and may be defined as: Number of rows) x (Number of columns) a _n = -

¹ (Number of data input /output ports)

As a result, TADD = 768 x (1024/32) x Tu = 24576Tu. Hence, T _frame = 2 ¹⁶ T _U + 16 x T _ADD = 65535T _U + 16 x T _ADD = 458753T _U = 3.06ms. So the equivalent frame rate is found to be 163Hz (2 sub-frame per frame) or 82Hz (4 sub-frame per frame).

Example 2: Timing Calculation for a 480 x 640 Pixel Array having 32 data inputs/outputs.

When the method of generating the bit-plane signals as illustrated in Figures 3 and 4 are used, the total duration of a frame Tf _ram e for a 480 x 640 pixel array may be computed as follows. The total duration of a frame may be obtained by equation (3) as: frame ~ 655357^ + i X T DD

If the system clock is 100MHz, T _u is 1/150MHz = 10ns, where TADD is a _P x Tu, and as a result, TADD = 480 x (640/32) x Tu = 9600Tu = 96ps. Hence, 219136T _U = 2.19ms. So the equivalent frame rate is found to be 228Hz (2 sub-frame per frame) or 1 Hz (4 sub-frame per frame).

Figure 5 illustrates an exemplary timing diagram that may be applied to the ports of digital pixel circuit 200 to control the addressing and illumination (holding) of the respective pixels in the pixel array. The first row 511 of the timing diagram illustrates the system clock timing diagram, the second row 512 illustrates the timing diagram of the inputs provided to the pixel, i.e. col_data and col_datan, and the third group of rows 513 illustrates the timing diagrams of the various rows of enable clock of ck_row[n], where n is the n ^,h row and it can be seen that from the first row to the next row, the ck_row is shifted by one system clock cycle. It can also be seen that when ck_row [0] is toggled to a high voltage level, the values stored in Q and QB nodes of the SRAM circuit will be updated based on the data from the col_data and col_datan input ports. Once all the pixels in row[n] have been updated, the whole pixel array’s addressing step has been completed as such, cknjiold’s falling edge appears and this enables the hold buffer circuit in all the digital pixel circuits thereby illuminating the pixel array with the content from the SRAM circuits. The flashing (holding) duration of the pixels depends on the length of the variable holding time component of the bit-plane signal, which increases from 2°Tu to 2 ¹⁵ Tu. One skilled in the art will recognize that the bit-plane signals generated in Figures 3 and 4 may be provided as the signals to the ck row input port and ckn hold input port of the digital pixel circuit whereby the variable holding time component is applied to the ckn_hold input port and the predetermined addressing time component is applied to the ck_row input port thereby generating the exemplary timing diagrams shown in Figure 5.

A side view of a pixel array is illustrated in Figure 6. In particular, a pixel array comprises CMOS circuitry 612 that is fabricated on top of substrate 614. Connecting bonds/wires are then used to connect the CMOS circuitry to electrodes 606 whereby the electrodes are separated from one another by via holes 607. Liquid crystal layer 604 is then provided between electrodes 606 and indium tin oxide (ITO) electrodes 602. A layer of glass 610 is then used to cover the surface of the ITO electrodes 602. In other words, it can be said that a pixel comprises a liquid crystal layer 604 that is provided between one of electrodes 606 and one of ITO electrodes 602.

As mentioned in the earlier sections, field inversion is implemented at the liquid crystal layer 604 (this is also known as DC balancing), and this is done to prevent the unidirectional flow of ions in the liquid crystal layer. In accordance with embodiments of the invention, this may be achieved by reversing a voltage level that is applied to ITO electrodes 602 every subframe. In other words, the voltage provided at ITO electrodes 602, V o may be configured to toggle between GND voltage level and a higher VDDA voltage level to maximize the voltage difference across the liquid crystal layer.

This is illustrated in Figure 7 whereby in the first sub-frame 701 , the ITO electrode is connected to GND and as a result, the voltage at the ITO electrodes, VITO is at the GND voltage level. Under the assumption that the final RMS voltage after all the bit-plane’s addressing has been completed by digital code D _ir is x, the voltage x is the voltage difference between electrode 606 and ITO electrode 602 of the liquid crystal layer (i.e. electrode 606: x volts, ITO electrode 602: GND voltage level).

In the second sub-frame, 702 the applied digital signal becomes 2i ₆ -D _in (under the assumption that the full scale VDDA is in relation to 2 ¹⁶ in the digital domain). As the voltage difference between 2 ¹⁶ -D _in and VDDA is still x, a negative x is realized (electrode 606: y volts, ITO electrode 602: VDDA volts, whereby the difference between the two electrodes is y - VDDA = 2 ¹⁶ - Di _n - 2 ¹⁶ = -x). The behaviour of the sub-frames 703 and 704 are also illustrated in Figure 7 with the variation in voltage levels for electrode 606 being shown as sub-frame 704 and the variation in voltage levels for ITO electrode 602 being shown as sub-frame 703. In embodiments of the invention, the toggling of the voltage at electrode 606, V _C OM, may be synchronized with the toggling of the voltage at ITO electrode 602, VITO (from GND to VDDA) and this may be done by generating the voltage provided to ITO electrode 602, VITO using the bit-plane control circuit.

Verification results

As an exemplary embodiment of the invention, the design as illustrated in the drawings and as described in the sections above was fabricated using a CMOS process and the results obtained from the SLM system 100 was compared against SLM systems known in the art as shown in Table 1 below.

TABLE 1

FOR PHASE RETARDATION OF 2lt: FOM = - formatxFFxfr -a -me _ra t _e xresolution

It can be seen that although the panel size of SLM 100 was the smallest amongst all the SLM systems, SLM 100 did not sacrifice its display format, resolution, and frame rate. The above is a description of embodiments of a circuit and method in accordance with the present invention as set forth in the following claims. It is envisioned that others may and will design alternatives that fall within the scope of the following claims.