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Title:
STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICON REGIONS
Document Type and Number:
WIPO Patent Application WO2006009613
Kind Code:
A3
Abstract:
Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

Inventors:
STEIGERWALT MICHAEL (US)
KUMAR MAHENDER (US)
HO HERBERT L (US)
DOBUZINSKY DAVID (US)
FALTERMEIER JOHNATHAN (US)
Application Number:
PCT/US2005/019815
Publication Date:
April 13, 2006
Filing Date:
June 06, 2005
Export Citation:
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Assignee:
IBM (US)
STEIGERWALT MICHAEL (US)
KUMAR MAHENDER (US)
HO HERBERT L (US)
DOBUZINSKY DAVID (US)
FALTERMEIER JOHNATHAN (US)
International Classes:
H01L21/308; H01L21/311; H01L21/762; H01L21/316; (IPC1-7): H01L27/12; H01L27/01; H01L31/0392
Foreign References:
US20030057487A12003-03-27
US20030201512A12003-10-30
US6825545B22004-11-30
Other References:
See also references of EP 1782473A4
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