FIELD OF THE INVENTION

The present invention relates generally to voltage references in transistor circuitry, and particularly to the use of switch capacitors in BGREF circuitry.

BACKGROUND OF THE INVENTION

With advances in Internet of Thing (IoT) applications and the expansion of mobile devices, energy consumption has become a primary focus of attention in integrated circuits design. These mobile battery operated devices need to operate for extended periods without recharging and therefore requiring ultra-low energy consumption. Many IoT devices require operation in a wide range of frequencies that are dynamically defined by the application. Low voltage operation in the "near-threshold" region has been shown to be the ideal way to dramatically reduce energy dissipation, still achieving reasonable performance. However, an aggressive scaling of supply voltage results in performance degradation and a much higher sensitivity to process variations and temperature fluctuations.

In addition to the reduction in supply voltage, many of the circuits are duty cycled, and turned off during sleep states. However, there are several types of circuits which need to be "always-on" and operate during standby mode. Among these circuits are real-time- clocks (RTC) and power management circuits, such as low drop out regulators (LDO) and DC-to-DC converters. All of these always-on elements require analog voltage and current references. To meet these requirements, there has been significant recent interest in ultra- low power references.

One such reference known in the prior art is the so-called 2T (two terminal) transistor-based voltage reference, which uses two MOSFET transistors sized such that the temperature coefficients of their threshold voltages (Vth) cancel out, thereby yielding a voltage reference which is temperature independent. Another 2T version uses native zero threshold devices which can produce a reference voltage independent of Vdd with only two transistors. Although the 2T references are very attractive due to their simplicity and ultra-low power (pW range), they have not yet found acceptance in most IOT systems. This is because the temperature coefficient of Vth is not necessarily guaranteed by the process, especially in advanced nodes. In general the use of the temperature dependence of Vth in MOS devices is not considered reliable in real products, since it can change over the course of the product lifetime, due to speed up of the process . Many computer systems utilize reference voltages produced by the parasitic Bipolar Junction Transistor (BJT), a.k.a. diode based references. The most common of these is shown in Fig. 1 which is a sub-bandgap reference. To first order, the current and voltage across the BJT are as follows:

I _c = I _s exp(^) and V _BE = V _g00 - XT [1]

where I _c is the collector current, V _be is the base-emitter voltage, V _g oo is the extrapolated V _be at OK, K=Boltzmann constant, q = electron charge, λ is its linear temperature coefficient and T is the absolute temperature. Using equation 1, the CTAT (complimentary to absolute temperature) and PTAT (proportional to absolute temperature) terms can be calculated for the circuit in Fig. 1 to be:

^V ref = ^ ^ \ N) [2]

The utility of this circuit is that both the voltage and temperature coefficient of Vref can be trimmed by digitally adjusting R3 and R2* respectively. Note that the terms PN diode and BJT are used interchangeably throughout the specification and claims. Essentially, the PN Junction Diode is the parasitic PNP BJT in the CMOS process whose base and collector are both connected to Vss (or ground).

Fig. 2 shows a prior-art switched-capacitor BGREF (bandgap voltage reference) circuit which consumes only 32nW and operates at 0.5V. The two V _be terms are generated by a charge pump circuit, while the delta- V _be terms are derived using a switch capacitor addition. It is important to note that in the prior art, the switch capacitor circuits are only used to perform mathematical functions by summing up the charge in the capacitor. The Vbe and delta- Vbe voltage can be summed by the switch-cap network.

One of the limitations and disadvantages of prior art nW BGREF' s is very large area, since the low currents necessitate the use of very large resistors in order to generate a significant voltage across them. Another disadvantage is that due to the low currents, the wakeup times of these references can be in the milli-second range.

SUMMARY OF THE INVENTION

The present invention seeks to provide a novel use of switch capacitors in BGREF circuitry.

Since analog circuits do not scale very well as technology advances, it is important to develop new architectures which can enable the analog portions to shrink. In addition, the IoT space requires integrated circuits which can operate at different power/performance levels and which are also low cost. The present invention provides novel voltage references which have low area/cost, ultra-low-current and are configurable in terms of their power. The power in the circuit can be easily adjusted over a large range to provide fast wakeup and higher drive currents when needed, and lower current operation for the "always-on" ultra-low power states. The novel circuit concepts can be optimized for the emerging IoT market.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the drawings in which:

Fig. 1 is a circuit diagram of a prior art BGREF circuit that uses large area resistors;

Fig. 2 is a circuit diagram of a prior-art switched-capacitor BGREF circuit, in which the switch capacitor circuits are only used to perform mathematical functions by summing up the charge in the capacitor;

Fig. 3 is a simplified circuit diagram of a switch-cap circuit, in accordance with a non-limiting embodiment of the present invention, which is an impedance element that can be used to implement functionality of a resistor;

Fig. 4 is a simplified circuit diagram of a BGREF circuit using the switch-cap circuits of Fig. 3, in accordance with a non-limiting embodiment of the invention;

Fig. 5 is a simplified circuit diagram of a (binary) capacitor bank for use as the capacitors in Fig. 4, in accordance with a non-limiting embodiment of the present invention;

Fig. 6 is a simplified circuit diagram of a BGREF circuit using switch-cap circuits, in accordance with another non-limiting embodiment of the invention; and

Figs. 7A-7D are graphical illustrations of simulations of the BGREF circuit of Fig. 6 for VCC=1.2V, wherein Fig. 7A shows a low power mode in several corners, Fig. 7B shows the power consumption at these corners, Fig. 7C shows the Vref voltage at different switching frequencies, and the power consumption at these frequencies is shown in Fig. 7D for the typical corner.

DETAILED DESCRIPTION OF EMBODIMENTS

In an embodiment of the present invention, the BGREF includes a switched capacitor (also referred to as switch-cap) circuit.

The impedance Z of a switch-capacitor can be expressed as where C is the capacitance and s is the frequency. As opposed to resistors, a high impedance switch-cap requires little area, thereby providing a much more compact solution as opposed to the prior art circuitry that uses resistors, which are very large devices in advanced CMOS processes.

The impedance of the switch-cap can be controlled by the frequency (of the switch), and is thus adjustable.

Reference is made to Fig. 3, which illustrates a switch-cap circuit, in accordance with an embodiment of the present invention, which is an impedance element that can be used to implement functionality of a resistor.

The non-limiting circuitry of Fig. 3 is now described. In general, throughout the specification and claims, the term "connected" means a direct electrical connection between the things that are connected, without any intermediary devices. The term "coupled" means either a direct electrical connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term "circuit" or "circuitry" means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" means at least one current signal, voltage signal or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on." For purposes of the embodiments, the transistors are metal oxide semiconductor (MOS) transistors, which include drain, source, gate, and bulk terminals, but the transistors may include any device implementing transistor functionality, such as without limitation, bi-polar junction transistors-BJT PNP/NPN, BiCMOS, CMOS, eFET, etc.

A capacitor C2 (fixed decoupling capacitor C2) is coupled at one side to an anode and at the other side to a cathode. Two switch capacitor elements SCx and SCy (also referred to as switch capacitor impedance elements), each switch capacitor element including a capacitor CI coupled with overlapping switches SW1 and SW2, which receive an input frequency from clocks PI and P2, are each coupled between the anode and cathode in parallel to C2. In SCx, clock P2 is coupled between the anode side of CI and the anode and the other clock PI is coupled to the cathode and to the anode side of CI. In SCy, clock PI is coupled between the anode side of CI and the anode and the other clock P2 is coupled to the cathode and to the anode side of CI.

Accordingly, there are two non-overlapping switches SW1 and SW2 with frequency inputs from clocks PI and P2 which are placed in anti-phase over two switched capacitors CI (also referred to as flying capacitors CI). The capacitors CI may be, without limitation, metal finger capacitors (MFC), e.g., with a capacitance density of 2 ff/μιη . The fixed decoupling capacitor C2 may be, without limitation, a hybrid gate and metal capacitor, e.g., with a capacitance of 8-10 ff/μιη . C2 is placed there to reduce the ripple caused by the switching action. Note that in Fig. 3, SCx and SCy are each complete switch-capacitor elements. They are placed in anti-phase to reduce the overall ripple in the anode voltage. The switch capacitor element used in the embodiments of the invention may refer to either a single element, such as SCx or SCy of Fig. 3, or to the composite of two anti-parallel elements, which is SCx and SCy and C2 of Fig. 3.

Reference is now made to Fig. 4, which illustrates BGREF circuitry in accordance with an embodiment of the invention, incorporating the switch capacitor circuits of Fig. 3.

A source of PMOS transistor M2B is coupled to a voltage source (Vcc), its drain is coupled to node Vband and its gate is coupled to node PG1. Node PG1 is coupled to the output of an amplifier Al, whose positive input is coupled to Vband and whose negative input is coupled to node Vbe. A source of PMOS transistor M2C is coupled to a voltage source (Vcc), its drain is coupled to node Vbe and its gate is coupled to node PG1.

A switch capacitor element SCI is coupled at a first terminal (such as, but not necessarily, its anode side) to Vband and at a second terminal (such as, but not necessarily, its cathode side) to a first terminal (such as, but not necessarily, an anode) of a diode Dl. The second terminal (such as, but not necessarily, the cathode) of diode Dl is coupled to a negative voltage supply (Vss). A switch capacitor element SC2a is coupled at a first terminal (such as, but not necessarily, its anode side) to Vband and at a second terminal (such as, but not necessarily, its cathode side) to a negative voltage supply (Vss). A switch capacitor element SC2b is coupled at a first terminal (such as, but not necessarily, its anode side) to Vbe and at a second terminal (such as, but not necessarily, its cathode side) to a negative voltage supply (Vss). A first terminal (such as, but not necessarily, an anode) of a diode D2 is coupled to node Vbe and a second terminal (such as, but not necessarily, its cathode) is coupled to a negative voltage supply (Vss). The area ratio of the two diodes is N, which can be, for example, 8 without limitation.

Note that the diode in a more general sense can be any "diode element" which has an electrical behavior similar to a diode. An example of this would be a transistor whose gate is connected to its drain - this type of connection is referred to as a diode-connected device to those skilled in the art. In the case of an NMOS, the gate-drain connection would be the anode, while its source would be the cathode and this would behave like a PN junction diode. In the case of a PMOS, a similar connection would be true; the gate would be connected to the drain, and the gate-drain connection would be the cathode, while the source would be the anode. Thus when we refer to a diode element we mean the generalized definition including a PN junction diode (or parasitic BJT) or the MOS diode-connected devices, and the term "diode" in the specification and claims encompasses such diode elements as well.

A source of PMOS transistor M2A is coupled to a voltage source (Vcc), its drain is coupled to node Vref and its gate is coupled to the gate of M2C. A switch capacitor element SC3 is coupled at its anode side to Vref and at its cathode side to a negative voltage supply (Vss).

Accordingly, the resistors of the prior art circuitry of Fig. 1 have been replaced with switch capacitor elements of Fig. 3, thereby creating a nW BGREF at minimal size. For example, without limitation, the size of the BGREF circuit using this method can be < 6000 μηι with power ~ 3-5nW. As mentioned before, the switch-cap is used as an impedance element, which is different from the prior-art switch-cap BGREF of Fig. 2, which uses switched-capacitors in an entirely different way, namely to perform mathematical functions by summing up the charge on the capacitor.

It is possible to construct the BGREF circuit with one switch capacitor element and one diode; however, the preferred embodiment has a plurality of switch capacitors and diodes.

In the embodiment of Fig. 4, the voltages at Vbe and Vband are made equal by the feedback circuit comprised of the amplifier Al and current sources. Vband is coupled to a first input of the Al, which may be the positive input and Vbe is coupled to the second input of Al, which may be the negative input. Diode Dl is a multiple of diode D2 and since the currents are equal the current density in D2 is a multiple of Dl. Note that the anode of Dl (the P of the PN junction) is connected to switched-capacitor impedance element SCI while its cathode (N of the PN junction) is connected to the negative supply, Vss. Similarly the anode (P) of D2 is connected to Vbe, while its cathode (N) is connected to Vss. The equation for the reference voltage Vref of this circuit can be expressed as:

Vre _f = ^ [V _T * SC ₁ \n(N) + SC ₂ * Vbe] (3)

wherein V _T = voltage at a certain absolute temperature T

N = the ratio between the two diodes SCi = capacitance of the ith switch capacitor

Vbe = base-emitter voltage

The current in the output stage can be expressed as

ef = Vref * sSC3 = s[V _T * SCj ln(N) + SC ₂ * Vbe] (4)

Similarly, the currents in all of the PMOS current sources can be scaled versions of this and are thus highly dependent on the switching frequency and the capacitance values, thereby providing an additional degree of configurability. The voltage can be calibrated by trimming SC3, and the temperature coefficient can be calibrated by trimming SC2(a or b). Since a switch is placed in series with each capacitor element, the trim works by making the switch conducting or non-conducting, such that the capacitance connected to the switch may or may not be connected to the active node of the circuit. Thus the values of CI, C2 and C3 can be controlled digitally by activating these switches and the Vbe, Vref and delta- Vbe terms can each be trimmed independently.

One or all of the capacitors in Fig. 4 may be replaced with a capacitor bank (e.g., binary capacitor bank), as shown in Fig. 5 to enable calibration. As seen in Fig. 5, the capacitor bank includes 1-N circuit elements coupled in parallel between the anode and the cathode, wherein the circuit element is a capacitor with one side coupled to the cathode and the other side coupled to a clock which is coupled to the anode.

The bias for the amplifier in Fig. 4 may be taken from the PMOS current sources M2* (that is, M2A or M2B). The circuit can be started up by pulling down node PGl with a digital pulse. The temperature coefficient trim (SC2 a or b) can be used to rectify the PTAT non-linearity at ultra-low currents; reversed biased diode methods may also be used to achieve this.

Reference is now made to Fig. 6, which is a simplified circuit diagram of a BGREF circuit using switch-cap circuits, in accordance with another non-limiting embodiment of the invention. In this embodiment, the amplifier is replaced by a voltage and current mirror formed by NMOS transistors Ml(b,c) and M2(b,c).

Specifically, the source of an NMOS transistor Mlb is coupled to node Vband, and its drain and gate are coupled to node NG1. The source of an NMOS transistor Mlc is coupled to node Vbe, its drain is coupled to node PGl and its gate is coupled to the gate of Mlb.

The currents are equal because of the current mirrors M2b and M2c. The voltages at Vband and Vbe are equal due to the source follower action of Ml(b,c). In order to improve the gain of the voltage/current mirror circuit, self-biased cascodes may be formed in both Ml(b,c) and M2(a, b,c) as shown in the upper left of Fig. 6 (such as two NMOS transistors Mlb-LVth and Mlb-HVth, the drain of Mlb-HVth being coupled to the source of Mlb-LVth). This technique exploits the fact that there are multiple Vth's in advanced nodes such that both transistors shown in the upper left of Fig. 6 can be saturated which increases the overall gain of the circuit and hence its accuracy. Since the transistors in the circuit may operate in the deep subthreshold mode, the Vgs voltages can be relatively small and the circuit can operate at 1.1V or even lower. The advantage of the version of Fig. 6 over that of Fig. 4 is that it does not require additional bias currents for the amplifier. However, the version with the amplifier can operate at lower voltages, albeit at slightly higher currents.

The largest flying capacitor of the group may be SCI since it has the smallest impedance, with a value of ~ 0.5- lpF. The capacitance of SC2(a or b) may be very small, which could result in matching issues. This can be solved by stacking two switch-caps in series and enlarging their size by 2x as shown at SC2a and SC2b in Fig. 6.

A comparison of the Fig. 6 BGREF to some prior art ultra-low power BJT -based references is shown in Table 1. The BGREF of Fig. 6 has the lowest power and smallest area by a factor of > 5 compared to the prior art. The BGREF of Fig. 6 can be placed in high-power mode temporarily to achieve a relatively fast settling time. The BGREF of Fig. 6 exhibits a high degree of configurability, since its output voltage can be adjusted over a wide range by trimming the output switch-cap and also has a temperature coefficient trim capability. The amount of current in the circuit, and hence its wakeup time, can be adjusted by changing the reference frequency of the switch-capacitors.

TABLE 1

The prior art includes:

Y. Osaki, T. Hirose, N. Kuroki and M. Numa, " 1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs," in IEEE Journal of Solid-State Circuits, vol. 48, no. 6, pp. 1530- 1538, June 2013

J. M. Lee, et. al. "A 29nW Bandgap Reference Circuit", IEEE ISSCC Dig. Tech. Papers, pp. 100-101, Feb. 2015

Y. Ji et. al. "A 9.3nW All-in-One Bandgap Voltage and Current Reference Circuit", IEEE ISSCC Dig. Tech. Papers, pp. 100-101, Feb. 2017

A. Shrivastava, K. Craig, N. E. Roberts, D. D. Wenzloff, and B. H. Calhoun, "A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-Low Power Systems" IEEE ISSCC Dig. Tech. Papers, pp. 94-95, Feb, 2015 Preliminary Results

Simulations of the Fig. 6 version of the BGREF are shown in Figs. 7A-7D for VCC=1.2V. Fig. 7A shows a low power mode in several corners, while Fig. 7B shows the power consumption at these corners. The power consumption at room temperature is 2nW in all of these corners. In the fast corner (ff), the power rises at high temperature, presumably due to leakage. The ff corner also exhibits a more positive temperature coefficient, which may also be associated with leakage currents. The Vref voltage is shown at different switching frequencies in Fig. 7C, while the power consumption at these frequencies is shown in Fig. 7D for the typical corner. Fig. 7C shows that at very low power modes, the temperature coefficient of the BGREF is affected, presumably due to the PTAT constant term. This can be corrected using the temperature coefficient trim or by other methods. Also note that at the frequency rises, so does the Vref value. This is because Vbe has some dependency on current. This can be calibrated using the voltage trimming between different modes. The output ripple at all frequencies is 8mV.