Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SWITCHED CAPACITOR BANDGAP REFERENCE
Document Type and Number:
WIPO Patent Application WO/1982/002806
Kind Code:
A1
Abstract:
A temperature stable bandgap voltage reference source (10) utilizing two substrate bipolar transistors (12 and 14) biased at different emitter current densities. Switched capacitors (28 and 34) are used to input the Vbe and the (Alpha)Vbe of the transistors (12 and 14) (NTC and PTC voltages, respectively) into an amplifier (42) to provide a reference voltage VREF proportional to the weighted sum of the PTC and NTC voltages. Proper selection of the ratio of the switched capacitors (28 and 34) renders the reference voltage VREF substantially independent of temperature. In a modified form of the reference (10), the reference amplifier (22) is implemented by an auto-zeroed operational amplifier (42) which uses switched capacitor techniques and an integrated capacitor (44) to achieve the auto-zeroing function.

Inventors:
ULMER RICHARD WALTER (US)
WHATLEY ROGER A (US)
Application Number:
PCT/US1982/000093
Publication Date:
August 19, 1982
Filing Date:
January 25, 1982
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MOTOROLA INC (US)
International Classes:
G05F1/56; G05F3/30; H03K3/26; (IPC1-7): H03K3/26
Foreign References:
US4249122A1981-02-03
US4307333A1981-12-22
US4071813A1978-01-31
US4317054A1982-02-23
US4295089A1981-10-13
Other References:
See also references of EP 0070315A4
Download PDF:
Claims:
CLAIMS
1. A circuit 22 for producing a substantially temperature independent reference voltage VRE , the circuit 22 comprising: first and second bipolar transistor means 12 and 14 having a predetermined base voltage and biased at different current densities to develop first and second emitter voltages, respectively, on the emitters thereof; clock means 16 for alternately providing first and second nonoverlapping clock signals; first switched capacitance means 28 coupled to said base voltage in response to the first clock signal A and to said first emitter voltage in response to the second clock signal B, for providing a first charge related to the Vτ,e of the first transistor means; second switched capacitance means 34 coupled to said second emitter voltage in response to the first clock signal A and to said first emitter voltage in response to the second clock signal B, for providing a second charge related to the differ¬ ence in the V*,e of the first and second bipolar transistor means 12 and 14; and amplifier means 22 coupled to the first and second switched capacitance means 28 and 34 for providing a reference voltage REF proportional to the sum of the first and second charges.
2. The circuit 22 of claim 1 wherein each of said switched capacitance means 28 and 34 comprises a capacitor and switching means 30, 32 and 36, 38, respectively, responsive to said clock signals A and B.
3. ".
4. ΛI/" 3 The circuit 22 of claim 2 wherein said amplifier means 22 comprise an operational amplifier 42, a feedback capacitor 44, and switching means 48 for periodically coupling the input and output portions of the feedback capacitor.
5. A method of producing a substantially temperature independent reference voltage VREF comprising the steps of: biasing first and second bipolar transistor means 14 and 12, respectively, having the same predeter¬ mined base voltage, at different current densities to develop first and second emitter voltages; providing first and second nonoverlapping clock signals A and B; coupling an input portion of first capacitance means 28 to said base voltage in response to the first clock signal and to the first emitter voltage in response to the second clock signal B, whereby an output portion of said first capacitance means 28 couples a first charge related to the V >e of the first transistor means; coupling an input portion of second capacitance means 34 to said second emitter voltage in response to the first clock signal A and to said first emitter voltage in response to the second clock signal B, whereby an output portion of said second capacitance means 34 couples a second charge related to the difference in the V*,e of the first and second transistor means 14 and 12, respectively; and amplifying the sum of the charges coupled from the output portions of the first and second capaci tance means 28 and 34 to provide a reference voltage ^ Proportional to the sum of the first and second charges.
6. • A circuit 22 for producing a substantially temperature independent reference voltage VREp, the circuit 22 comprising: first and second transistors 14 and 12 having the bases thereof coupled to a predetermined bias voltage VAQ; the collectors coupled to a positive supply VDD and the emitters thereof open; biasing means 24 and 26 coupled between the emitters of the first and second transistors 14 and 12 and a negative supply Vgg biasing said first and second transistors 14 and 12 at different current densities; a first capacitor 28 having a first portion coupled alternately to the predetermined bias voltage VAG a ** emi ter of the first transistor 14, for providing a first charge related to the Vtøg of the first transistor 14; a second capacitor 34 having a first portion coupled alternately to the emitter of the first transistor 14 and the emitter of the second transistor 12, for providing a second charge related to the difference in the Vj,e of the first and second transistors 14 and 12; and an amplifier 22 coupled to the first and second capacitors 28 and 34 for providing a reference voltage VREF proportional to the sum of the first and second charges.
7. The circuit 22 of claim 5 wherein the first portions of the first and second capacitors 28 and 34 are alter nately coupled to the first and second transistors 14 and 12 by clocked switches in response to nonoverlapping clock signals A and B.
8. The circuit 22 of claim 5 wherein the amplifier 22 comprises an operational amplifier 42, a feedback capacitor 44, and switching means 48 for periodically discharging the feedback capacitor.
Description:
SWITCHΞD CAPACITOR 3ANDGAP REFERENCE

BACKGROUND OF THE INVENTION

Field of the Invention

This invention relates generally to bandgap reference circuits and more particularly to CMOS bandgap reference circuits.

Description of the Prior Art

Typically, the best reference for a good reproducible, stable voltage below three volts has been the bandgap reference circuit. As discussed in Analysis and Design of Analog Integrated Circuits by Paul R. Gray and Robert G. Meyer (John Wiley and Sons, 1977, pp. 239-261), the base to emitter voltage *- )e , of a bipolar transistor exhibits a negative temperature coefficient with respect to temperature. Thus, the sum of the base to emitter voltage, v be' °^ a bipolar transistor and a differential voltage Δ tø g in be relatively independent of temperature when the sum voltage equals the energy gap of silicon. Such temperature stable references have been created by generating a V_ e and summing a AV ] -^ of such value that the sum substantially equals the bandgap voltage of 1.205 volts.

A standard CMOS process can be used to fabricate open emitter NPN bipolar transistors for use in a bandgap refer¬ ence circuit such as that taught in U.S. Patent Application No. 034513. To create a stable temperature independent CMOS bandgap voltage with amplifying means, such as an operational amplifier, two transistors of varying current density were used as emitter followers having resistors in their emitter circuits from which a differential voltage was obtained. An output voltage having a positive, negative or zero coefficient was thereby produced.

-2-

Several " factors in the CMOS circuit, however, affected the initial tolerance variation and temperature variation of the bandgap voltage. The dominant initial tolerance error was caused by the offset voltage associated with the 5 operational amplifier being multiplied by the ratio of two resistors in the emitter circuit of the transistor with lowest current density. Further disadvantages of the prior art are problems with P-resistor matching and a 2:1 variation in the P-resistivity over temperature. Previous 10 CMOS bandgap circuits also required a startup circuit.

Summary of the Invention

It is an object of the present invention to provide a

15 bandgap reference utilizing substrate bipolar transistors and MOS transistors to provide a reference voltage which is substantially temperature stable and substantially independent of process variations.

It is a further object of the invention to provide a

20 bandgap reference fabricated using a standard CMOS process and switched capacitor techniques, which sums the V*-> e and ΔVJ- JQ of substrate bipolar transistors to derive a near zero temperature coefficient reference voltage.

According to an (P.A.) aspect of the invention, there

25 are provided a first and a second substrate bipolar transistor wherein the emitter area of the first transistor is much larger than the emitter area of the second transistor. Since the second transistor is operated at a higher current density than the first transistor, the

30 V- Qe of the second transistor is greater than the

Vb e of the first transistor. Using switched capacitors coupled to the emitters of the transistors, the base to emitter voltages of the devices are sampled. When the difference between the two sampled voltages are added in

35 the correct proportion, the result is a voltage with a substantially zero temperature coefficient. The above and

other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

Brief Description of the Drawings

Figure 1 is a schematic diagram illustrating one preferred embodiment of the invention. Figure 2 is a graphic timing diagram for the schematic embodiment shown in Figure 1.

Figure 3 is a schematic diagram illustrating another embodiment of the amplifier used in the present invention. Figure 4 is a graphic timing diagram for the schematic embodiment shown in Figure 3.

Description of the Preferred Embodiment

Shown in Figure 1, is a switched capacitor bandgap reference circuit 10 constructed in accordance with the preferred embodiment of this invention. The bandgap reference circuit 10 is comprised generally of first and second bipolar transistors 12 and 14, respectively, a clock circuit 16, a first switched capacitance circuit 18, a second switched capacitance circuit 20, and an amplifier circuit 22.

Each of the first and second bipolar transistors 12 and 14 has the collector thereof connected to a positive supply V ( _ < _ !• the base thereof connected to a common reference voltage, say analog ground V ag , and the emitter thereof connected to a negative supply V ss via respective current sources 24 and 26. In the preferred form, the current sources 24 and 26 are constructed to sink a predetermined ratio of currents, and transistor 12 is fabricated v/ith a larger emitter area than the transistor 14. Since the transistors 12 and 14 are biased at different

current densities they will thus develop different base-to-emitter voltages, V^ e . Because the transistors 12 and 14 are connected as emitter followers, the preferred embodiment may be fabricated using the substrate NPN in a standard CMOS process.

In the first switched capacitance circuit 18, a capacitor 28 has an input connected via switches 30 and 32 to the common reference voltage V ag and the emitter of transistor 14, respectively. In the second switched capaci- tance circuit 20, a capacitor 34 has an input connected via switches 36 and 38 to the emitter of transistors 12 and 14, respectively. Capacitors 28 and 34 have the outputs thereof connected to a node 40. In the preferred embodiment, switches 30, 32, 36 and 38 are CMOS transmission gates which are clocked in a conventional manner by the clock circuit 16. Switches 30 and 36 are constructed to be conductive when a clock signal A applied to the control inputs thereof is at a high state, and non-conductive when the clock signal A is at a low state. In contrast, switches 32 and 38 are preferably constructed to be conductive when a clock signal B applied to the control inputs thereof is at a high state and non-conductive when the clock signal B is at a low state.

In this configuration, switches 30 and 32 will cooperate to charge capacitor 28 alternately to the base voltage of transistor 14 and the emitter voltage of transistor 14, thus providing a charge related to Vtø e of transistor 14. Simultaneously, switches 36 and 38 cooperated to charge capacitor 34 alternately to the emitter voltage of transistor 12 and the emitter voltage of transistor 14, thus providing a charge related to the difference between the base to emitter voltages, i.e., the ΔV j - jg , of the transistors 12 and 14. As will be clear to those skilled in the art, the voltage, { -, e , will exhibit a negative temperature coefficient (NTC) . On the other hand, it is well known that the voltage Δ.V*-, e

exhibits a positive temperature coefficient (PTC). Thus, it will be clear that the weighted sum of these voltages, fae + ^A^be' where K = C34/C28 ma Y be made substantially temperature independent by appropriate selection of the ratio of capacitors 28 and 34.

In the amplifier circuit 22, an operational amplifier 42 has its negative input coupled to node 40 ' and its positive input coupled to the reference voltage v ag • A feedback capacitor 44 is coupled between the output of operational amplifier 42 at node 46 and the negative input of the operational amplifier at node 40. In the preferred form, a switch 48 is coupled across feedback capacitor 44 with the control input thereof coupled to clock signal C provided by clock circuit 16. By periodically closing switch 48, the operational amplifier 42 is placed in unity gain, and any charge on capacitor 44 is removed.

As shown in Figure 2, the clock circuit 16 initially provides the clock signal A in a high state to close switches 30 and 36, and clock signal B in a low state to open switches 32 and 38. Simultaneously, the clock circuit 16 provides the clock signal C in a high state to close the switch 48. During this precharge period, feedback capacitor 44 is discharged, and, ignoring any amplifier offset, capacitors 28 and 34 are charged to the reference voltage, V ag , and the V De of the transistor 12, respectively. A short time before the end of the precharge period, the clock circuit 16 opens switch 48 by providing the clock signal C in a low state. Shortly thereafter, but still before the end of the precharge period, the clock 16 opens switches 30 and 36 by providing the clock signal A in the low state. At the end of the precharge period and the start of a valid output reference period, the clock circuit 16 closes switches 32 and 38 by providing the clock signal B in the high state. At this time, the voltage on the terminals of capacitor 28 changes by -V j - je of transistor

14 and the voltage on the terminals of capacitor 34 changes

by the difference between the base to emitter voltages of the transistors 12 and 14, ( t) e τ_2 ~ V b e^-"* This switching event causes an amount of charge Q ÷ (Vbel2 ~ v bel ) c 34 to be transferred to capacitor 44 resulting in an output voltage of V re f = -I/C44C-Vbel4 c 28 + < v bel2 " v bel4) C34] on node 46. In the preferred form, this positive bandgap reference voltage, +V re f is made substantially temperature independent by making the ratio of capacitors 28 and 34 equal to the ratio of the temperature coefficients of Δv*-- e and V De . If desired, a negative bandgap reference voltage, -V re fr may be obtained by inverting clock signal C so that the precharge and valid output reference periods are reversed.

In general, the accuracy of the bandgap circuit 10 will be adversely affected by the offset voltage of the operational amplifier. Figure 3 illustrates in schematic form, a modified form of amplifier circuit 22' which can be substituted for the amplifier circuit 22 of Figure 1 to substantially eliminate the offset voltage error. Amplifier circuit 22' is comprised of the operational amplifier 42 which has its positive input coupled in parallel to feedback capacitor 44 and periodically discharges the feedback capacitor. However, one terminal of the feedback capacitor 44 is now connected via a switch 52 to the output of the operational amplifier 42 at node 46. Capacitor 44 is also coupled to an input signal, j ^, at node 40. In addition, an offset storage capacitor 54 is coupled between node 40 and the negative input terminal of operational amplifier 42, and a switch 56 is connected between node 40 and the reference voltage V aq . In this embodiment, the clock circuit 16' generates the additional clock signals D and E, as shown in Figure 4 for controlling the switches 56 and 50, respectively, with the inverse of clock signal D controlling switch 52. In this configura- tion, the bandgap reference circuit 10 has three distinct periods of operation. During the precharge period, the

clock circuit 16' provides clock signals C, D, and E in the high state to close switches 48, 56 and 50 and open switch 52. During this period, capacitor 44 is discharged by switch 48. The operational amplifier 42 is placed in unity gain by switch 50, and the offset storage capacitor 54 is charged to the offset voltage, V os , of the operational amplifier 42. Near the end of the precharge period, the clock circuit 16' provides clock signal E in the low state to open switch 50, leaving capacitor 54 charged to the offset voltage of the oeprational amplifier 42. A short time thereafter, the clock circuit 16' provides clock signal D in the low state to open switch 56 and close switch 52. Since this switching event tends to disturb the input node 40, a short settling time is preferably provided before clock circuit 16 ' provides clock signal C in the low state to open switch 48. Thereafter, the charge stored on feedback capacitor 44 will be changed only by a quantity of charge coupled from the switched capacitor sections 13 and 20. During this third period of circuit operation, labeled the valid output reference period, the reference voltage developed on the node 46 will be substantially free of any offset voltage error. If the offset capacitor 54 is periodically charged to the offset voltage, V os , the operational amplifier 42 is effectively autozeroed, with node 40 being the zero-offset input node.

While the invention has been described in the context of a preferred embodiment, it will be apparent to those skilled in the art that the present invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.