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Patent Searching and Data


Title:
SWITCHED EMITTER FOLLOWER CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2021/205592
Kind Code:
A1
Abstract:
This switched emitter follower circuit comprises: a transistor (M1) in which a base is connected to a signal input terminal, a power source voltage (VCC) is applied to a collector, and an emitter is connected to a signal output terminal; a capacitor (Chold) in which one end is connected to the collector of the transistor (M1), and the other end is connected to the emitter of the transistor (M1); and a Gilbert cell multiplier circuit (10) in which a positive phase clock output terminal is connected to the emitter of the transistor (M1), a negative phase clock output terminal is connected to the base of the transistor (M1), and the result of multiplying an externally input differential clock signal (ck1) and a differential clock signal (ck2) is output to the positive phase clock output terminal and the negative phase clock output terminal.

Inventors:
TERAO NAOKI (JP)
NAGATANI MUNEHIKO (JP)
NOSAKA HIDEYUKI (JP)
Application Number:
PCT/JP2020/015940
Publication Date:
October 14, 2021
Filing Date:
April 09, 2020
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
H03M1/12; H03K17/00
Attorney, Agent or Firm:
YAMAKAWA, Shigeki et al. (JP)
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