CROSS REFERENCE TO RLEATED APPLICATIONS

[0001] This application claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 63/146,261 , entitled “Systems and Methods for Digital Signal Chirp Generation Using Frequency Multipliers” to Yu et al., filed February 5, 2021 , and that is hereby incorporated by reference in its entirety.

FIELD OF THE INVENTION

[0002] The present invention relates to chirp generators and more specifically to a using a digitally synthesized chirp signal and processing the signal using frequency multipliers to generate a higher frequency signal for radar applications.

BACKGROUND

[0003] A chirp is a signal in which the frequency increases (up-chirp) or decreases (down-chirp) with time. In some sources, the term chirp can be used interchangeably with sweep signal. It can be applied to sonar, radar, and laser systems, among various other applications. For automotive radar applications, it is usually called linear frequency modulated waveform (LFMW). LFMW signal can be specified in the following equation: [0004] (Equation 1 ): f _Q : initial frequency of the chirp signal a: frequency ramp rate of the chirp signal

0 _O : initial phase of the chirp signal

[0005] A chirp signal can be generated with analog circuitry via a voltage-controlled oscillator (VCO), and a linearly or exponentially ramping control voltage. SUMMARY OF THE INVENTION

[0006] Chirp generators that can utilize a digitally synthesized chirp signal in a low intermediate frequency (IF) band and process the chirp signal using frequency multipliers to generate a higher frequency signal for radar applications in accordance with embodiments of the invention are disclosed. In an embodiment of the invention, a chirp signal generator includes: a direct digital frequency synthesizer (DDFS) that is configured to receive an input sync signal and a frequency reference signal and generate several chirp signals at a first frequency that is in a low intermediate frequency (IF) band; several frequency multipliers that are configured to increase the chirp signals that are in the IF band to higher frequencies that are multiples of the first frequency; and several bandpass filter circuits that are configured to remove nonlinearities from the plurality of chirp signals to generate a clean output signal.

[0007] In a further embodiment, the chirp generator further includes: a first frequency doubler circuit that receives the first frequency and doubles the first frequency to generate a second frequency that is double the first frequency; a second frequency doubler circuit that receives the second frequency and doubles the second frequency to generate a third frequency that is double the second frequency; a third frequency doubler circuit that receives the third frequency and doubles the third frequency to generate a fourth frequency that is double the fourth frequency; a fourth frequency doubler circuit that receives the fourth frequency and doubles the fourth frequency to generate a fifth frequency that is double the fourth frequency.

[0008] In a further embodiment, the first frequency is in the 1562.5-1750 MHz range, the second frequency is in the 3125-3500 MHz range, the third frequency is in the 6250- 7000 MHz range, the fourth frequency is in the 12.5-14 GHz range, and the fifth frequency is in the 25-28 GHz range.

[0009] In a further embodiment, the several bandpass filter stages includes a first bandpass filter circuit after the first frequency doubler circuit, a second bandpass filter circuit after the second frequency doubler circuit, and a third bandpass filter circuit after the third frequency doubler circuit. [0010] In a further embodiment, the direct frequency synthesizer includes a high speed resonator that generates a frequency signal and an oscillator that receives the frequency signal and generates an output signal.

[0011] In a further embodiment, the chirp signal generator further includes several amplifier circuits that amplify an input chirp signal to generate an amplified output signal. [0012] In a further embodiment, a chirp signal is denoted as x(t) where:

/ ₀ : initial frequency of the chirp signal, a: frequency ramp rate of the chirp signal,

0 _O : initial phase of the chirp signal,

<p _n (t)'. phase noise added in a digital-to-analog (DAC) process; where a chirp signal is generated that is twice a carrier frequency of x(t) by passing x(t) through a frequency doubler circuit, where the frequency doubler circuit output is y(t) where:

[0013] In a further embodiment, a band-pass filter is used to select the desired 2 ^nd order harmonic from a frequency doubler, wherein a band-pass filter output is z(t) where: k: scale factor, where the several frequency multipliers include four (4) frequency doubler stages, where the output of each stage is denoted as z _£ (t), (i = 1,2, 3, 4), where: [0014] In a further embodiment, the chirp signal generator further includes: a first frequency quadrupler circuit that receives the first frequency and quadruples the first frequency to generate a second frequency that is four times the first frequency; a second frequency quadrupler circuit that receives the second frequency and quadruples the second frequency to generate a third frequency that is quadruple the second frequency. [0015] In a further embodiment, the chirp signal generator further includes filtering out harmonics and intermodulation components that do not fall within a particular frequency band to preserve a signal linearity during frequency multiplication stages.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 illustrates an architecture of a chirp generator with frequency multipliers in accordance with an embodiment of the invention.

[0017] Fig. 2 illustrates an architecture of a chirp generator with band-pass filters in accordance with an embodiment of the invention.

[0018] Fig. 3 illustrate an architecture of a 1 ^st stage amplifier noise in accordance with an embodiment of the invention.

[0019] Fig. 4 illustrates an architecture of a chirp generator with band-pass filter modeling in accordance with an embodiment of the invention.

[0020] Fig. 5 illustrates a doubler modeling in accordance with an embodiment of the invention.

[0021] Fig. 6 illustrates graphs of doubler output spectrums in accordance with an embodiment of the invention.

[0022] Fig. 7 illustrates graphs of band-pass filter frequency responses in accordance with an embodiment of the invention.

[0023] Fig. 8 illustrates a graph of an RF output spectrum in accordance with an embodiment of the invention.

[0024] Fig. 9 illustrates a graph of chirp output frequency in accordance with an embodiment of the invention.

[0025] Fig. 10 illustrates a graph of RF carrier phase noise in accordance with an embodiment of the invention. DETAILED DESCRIPTION

[0026] Turning now to the drawings, systems and methods for using digitally synthesized chirp signals and frequency multipliers to generate higher frequency RF chirp signals as appropriate for various applications including radar in accordance with various embodiments of the invention are illustrated. In many embodiments, a digital chirp signal can be generated using a digital direct-frequency synthesizer (DDFS) at a relatively low intermediate frequency (IF) band and the signal can be increased to a higher frequency using multiple stages of frequency multipliers as appropriate for radar applications.

[0027] In many embodiments, direct frequency synthesizers that provide a clean input signal can be utilized as described in U.S. Patent 10,530,372 entitled “Systems and Methods for Digital Synthesis of Output Signals Using Resonators” filed March 27, 2017, by Yu et al. (the Yu et al. patent), the relevant portions of which is incorporated by reference herein. In many embodiments, utilizing a DDFS as described by the Yu et al. patent can provide ultra-low phase noise and a pristine output signal. In many embodiments, the direct digital frequency synthesizer (DDFS) can include a high speed resonator that generates a frequency signal, an oscillator that receives the frequency signal and generates an output signal, a clock generator that receives the output signal of the oscillator and generates a clock signal from the output signal, a controller that generates a frequency control word describing a desired output digital signal, and a direct digital frequency synthesizer that receives the clock signal and the frequency control word and generates a desired digital output signal based on the clock signal and frequency control word.

[0028] In accordance with some embodiments, the output frequency may be controlled by a frequency control word (FCW) provided to the DDFS. In accordance with many embodiments, the frequency synthesizer can be equivalent to a voltage controlled oscillator (VCO) and can be used in a PLL for clock generation and/or jitter attenuation applications. In many embodiments, a direct digital frequency synthesizer (DDFS) block in accordance with various embodiments of this invention may be used for frequency and phase tracking. [0029] A direct frequency synthesizer in accordance with some embodiments of the invention may provide a programmable oscillator. The programmable oscillator may be used to replace many existing standard crystal and quartz based oscillators providing numerous benefits including, but not limited to, a significant cost savings. In particular, the programmable oscillator may be used to replace many of the existing high performance crystal oscillators (XO) and voltage controlled oscillators (VCXO) available on the market.

[0030] The programmable frequency of the programmable oscillator provided by a direct frequency synthesizer in accordance with a number of embodiments of the invention may range from 1 MHz to 2 GHz (or higher) and be programmable with a frequency control word (FCW), which can be at least 32 bits in length. The frequency of the programmable oscillator provided by a direct frequency synthesizer in accordance with a number of embodiments of the invention may be factory programmable as a single frequency and/or limited to multiple selectable frequencies. In some embodiments, the programmable oscillator may be inter-integrated circuit (I2C) programmable and/or programmable using any other appropriate interface. In certain embodiments, the programmable frequency may be voltage controlled. The programmable oscillator may have less than 100 fs Jitter, integrated from 12 KHz - 20 MHz, and have a +/- 10 ppm frequency drift, with operating range in -40 to 85 degrees Celsius.

[0031] Furthermore, a programmable oscillator provided by a direct frequency synthesizer in accordance with some of embodiments of the invention may provide ultralow phase noise (e.g., <= 50 fs. Integrated from 12 KHz to 20 MHz). The programmable oscillator may have a single voltage supply (e.g., 3.3V, 2.5V, or 1.8V), and use an industry-standard package (e.g., 5x7, 3.2x5). As can readily be appreciated, the specific characteristics of a programmable oscillator provided by a direct frequency synthesizer in accordance with some of embodiments of the invention are not limited to any specific characteristics and can be determined based upon the requirements of specific applications in accordance with embodiments of the invention.

[0032] In many embodiments, a DDFS circuit may include lookup tables that store sine and cosine values. Furthermore, a control word may be used to set the output frequency of DDFS circuit in accordance with some embodiments. The DDFS circuit may provide a very high tuning range as the DDFS is used to set the frequency. Furthermore, a programmable oscillator is able to provide low phase noise with the ability to tune the output frequency of the programmable oscillator. In accordance with some embodiments, the DDFS circuit may use logic and memory to digitally construct the desired output signal, and an HS DAC may be used to convert the DDFS circuit output signal from the digital to the analog domain. Therefore, the DDFS method of constructing a signal may be almost entirely digital, and the precise amplitude, frequency, and phase may be known and controlled at all times.

[0033] In many embodiments, a chirp signal can be generated digitally by a digital signal processor (DSP) and digital to analog converter (DAC), using a direct digital frequency synthesizer (DDFS) and by varying the step in the numerically controlled oscillator. For example, digital codeword x _n can be specified in the following equation: [0034] Equation 2:

[0035] Digital codeword can be converted into analog signal with a high-speed DAC. Digital frequency synthesis architecture can offer many advantages over the analog VCO implementation, including up to a perfectly linear frequency modulation, ultra-low phase noise, and ultra-fast frequency modulation rate.

[0036] Following the Nyquist sampling theorem, a sample rate for a high-speed DAC may need to be at least twice of the highest frequency contained in the signal. For an automotive radar application that operates in, for example, the 77 GHz band, the sample rate for digital synthesis DAC can be close to 200 GHz. Implementing a design with these specifications can be difficult to build and not power efficient. Accordingly, many embodiments of the invention provide for digitally synthesizing a chirp signal in a low intermediate frequency (IF) band and converting this low IF signal to a higher frequency RF signal through a series of frequency multipliers. The system architecture in accordance with many embodiments of the invention offers substantial power saving without compromising the benefit of digital frequency synthesis. [0037] In several embodiments, a relatively low frequency (e.g., 1.5 to 2 GHz) chirp signal can be generated by a DDFS and processed through several stages of frequency doublers to convert the chirp signal from, for example, 1.75 GHz to a higher frequency range of 25-28 GHz, which may be appropriate for many radar applications, including automotive radar. In comparison, many currently existing radar applications may utilize an LC oscillator analog signal generated at e.g., 28GHz or may use a phase-lock-loop (PLL) that is mixed in with a 28 GHz signal to generate the chirp signal, however, these signals generally suffer from non-linearities and have problems with phase noise. Accordingly, to improve the phase noise and increase the linearity of a chirp signal, many embodiments use a digitally synthesized chirp signal rather than an analog signal, and maintain the linearity of the digital signal by filtering phase noise and non-linearities at each stage of the frequency multiplication. Accordingly, many embodiments are able to preserve the frequency linearity of the chirp generation and thereby increase the accuracy of many radar applications. [ _{0038] Denote a low IF chirp signal as where:} [0039] Equation 3: [0040] To generate a chirp signal that is twice a carrier frequency of x(t), pass x(t) through a frequency doubler. Denote the frequency doubler output as y(t) where: [0041] Equation 4:

[0042] As shown in equation 4 above, the frequency doubler output includes the chirp signal with twice the carrier frequency, bandwidth, and chirp rate of the input chirp signal and a DC component. In several embodiments, the output can also have the attenuated input signal due to signal leakage and the chirp signal at three times the carrier frequency due to circuit non-linearity. This is illustrated in Fig. 6 in accordance with an embodiment of the invention and can be shown in the following equation:

[0043] Equation 5:

[0044] In many embodiments, a band-pass filter can be used to select the desired 2 ^nd order harmonic from the frequency doubler. Denote band-pass filter output as z(t) where:

[0045] Equation 6: k: scale factor [0046] For a frequency multiplier that includes four (4) doublers, denote the output of each stage z _£ (t), (i = 1,2, 3, 4) and they are represented in the following equations: [0047] Equations ?:

[0048] As shown in these equations, the filtered frequency multiplier output comprises of the desired chirp output. The phase noise at the higher frequencies can be the phase noise at the IF frequency multiplied by the frequency multiplier ratio. In many embodiments, there is no additional phase noise in the frequency multiplier data path.

[0049] To preserve the signal linearity during frequency multiplication stages, many embodiments filter out any harmonics and intermodulation components that do not fall within a particular frequency band. In many embodiments, the frequency bands can be pre-planned as the artifacts and non-linearities during digital synthesis are known in advance and can be planned for during the filtering stages. Many embodiments use band pass filtering at each frequency multiplier stage to filter out the noise and preserve the signal linearity. A chirp generator with frequency multiplier in accordance with an embodiment of the invention is illustrated in Fig. 1.

[0050] As illustrates, an IF chirp generator which can be a direct digital frequency synthesizer (DDFS) that synthesizes a low intermediate frequency (IF) chirp signal and converts it to an analog signal through a high-speed DAC at a particular frequency, for example centered around 1 .6 GHz. In many embodiments, the DDFS can be a frequency synthesizer that provides a clean input signal as described in U.S. Patent 10,530,372 entitled “Systems and Methods for Digital Synthesis of Output Signals Using Resonators” filed March 27, 2017, by Yu et al. (the Yu et al. patent), the relevant portions of which is incorporated by reference herein. In many embodiments, the low IF chirp signal is up converted into higher RF frequencies with multiple stages, e.g., 4 stages of frequency doubling operations. In certain embodiments, four stages of frequency doubling operation can be implemented as two frequency quadruples.

[0051] The signal can be processed through several stages of frequency multipliers and amplifiers in order to obtain a frequency at a particular desired range, for example, a range of 25-28 GHz. In many embodiments, the architecture can include two stages of frequency quadruples that convert a chirp signal from, for example 1 .75 GHz to 28 GHz. In many embodiments, after each stage of frequency multiplication, the 2 ^nd order harmonics of the signal can be selected for further doubling. In many embodiments, the chirp generator architecture does not add an IQ imbalance and there is no phase noise degradation due to the charge pump.

[0052] As illustrated in Fig. 1 , the IF chirp generator can receive a sync_in signal and a reference signal, for example a 40 MHz reference signal, and generate chirp #1 that is provided to an amplifier and a chirp #2 that is provided to an amplifier. Each chirp can be provided to a quadrupler (x4) and a subsequent amplifier. After a first stage, a signal can be increased from e.g., 1562.5-1750 MHz range to e.g., 6250-7000 MHz range. The signals can be provided to another quadrupler to increase the frequency to e.g., 25-28 GHz range.

[0053] Although Fig. 1 illustrates a particular chirp generator architecture with two stages of frequency quadruples at a particular frequency, any of a variety of chirp generator architectures and frequences can be utilized, including chirp generators with four stages of frequency doublers among others as appropriate to the requirements of specific applications in accordance with an embodiment of the invention. Filtering and pre-planning techniques for preserving signal linearity in accordance with many embodiments of the invention include using band pass filtering to remove non-linearities after each stage of frequency multiplication.

[0054] Fig. 2 illustrates a chirp generator architecture with band pass filtering to remove non-linearities in accordance with an embodiment of the invention. As illustrated, the chirp generator can include a DDFS, several frequency doublers, and several band pass filters. As illustrates the IF chirp generator can be a frequency synthesizer that provides a clean input signal as described in U.S. Patent 10,530,372 entitled “Systems and Methods for Digital Synthesis of Output Signals Using Resonators” filed March 27, 2017, by Yu et al. (the Yu et al. patent), the relevant portions of which is incorporated by reference herein. As illustrated, the chirp signals can be provided to four stages of frequency doublers (x2), with each stage including an amplifier circuit and a bandpass filter circuit for harmonics filtering and that can remove nonlinearities at each stage. Accordingly, a chirp signal can be increased at each of the four stages as follows: from, for example, 1562.5-1750 MHz to 3125-3500 MHz, from 3125-3500 MHz to 6250-7000 MHz, from 6250-7000 MHz to 12.5-14 GHz, and from 12.5-14 GHz to 25-28 GHZ.

[0055] Although Fig. 2 illustrates a particular chirp generator architecture with band pass filters to remove non-linearities any of a variety of chirp generator architectures can be utilized as appropriate to the requirements of specific applications in accordance with an embodiment of the invention.

[0056] Fig. 3 illustrates a 1 ^st stage amplifier noise architecture in accordance with an embodiment of the invention. In many embodiments, the DAC output power = -10 dBm with -154 dBc/Hz noise floor. In many embodiments, the amplifier output noise floor in Amplifier noise in dBx/Hz = -174+NF - DAC output power. As illustrated, the low IF chirp signal noise floor can determine the noise performance of the final RF signal.

[0057] Although Fig. 3 illustrates a particular 1 ^st stage amplifier noise architecture, any of a variety of amplifier noise architecture can be utilized as appropriate to the requirements of specific applications in accordance with an embodiment of the invention. [0058] Fig. 4 illustrates a chirp generator with band pass filtering in accordance with an embodiment of the invention. As illustrated, the chirp generator includes a DDFS, four stages of frequency doublers, several low pass filters and several band-pass filters. In particular, a chirp generator can receive a sync_in signal and a frequency_ref signal and generator several chirp signals, including chirp_out1 and chirp_out2. The chirp signals can be amplified and passed through a low pass filter stage, and then provided to four stages of frequency doubler circuits. The chirp signals can also be provided to a series of band pass filter circuits as illustrated in Fig. 4.

[0059] [0060] Although Fig. 4 illustrates a particular chirp generator with band pass filtering architecture, any of a variety of chirp generator architectures can be utilized as appropriate to the requirements of specific applications in accordance with an embodiment of the invention.

[0061] Fig. 5 illustrates a model of a frequency doubler with intermodulation in accordance with an embodiment of the invention. In many embodiments, intermodulation can generate un-wanted harmonics in the frequency doubling operation. In many embodiments, the doubler can be modeled as the sum of IM2 product and IM3 product with a gain passing through a tilt filter. In many embodiments, the gain models the 3 ^rd order non-linearity of the doubler. In several embodiments, the tilt filter models power delta between a fundamental tone and 3x frequency tone. Although Fig. 6 illustrates a particular doubler modeling, any of a variety of doubler models can be utilized as appropriate to the requirements of specific applications in accordance with an embodiment of the invention.

[0062] Fig. 6 illustrates several graphs of a doubler output spectrum in accordance with an embodiment of the invention. As illustrated, each graph corresponds to a particular input (1.65 GHz, 3.3 GHz, 6.6 GHz, and 13.2 GHz) with the X-axis corresponding to a particular frequency and the Y-axis corresponding to dB. As illustrated, each graph shows the simulated output spectrum at each frequency doubler. As illustrated, these output spectrums match well with the specification of certain components being used in the chirp generator design in accordance with various embodiments of the invention.

[0063] Fig. 7 illustrates several graphs of a band-pass filter frequency response in accordance with an embodiment of the invention. Each graph corresponds to a particular a simulated band-pass filter frequency response (e.g., 2975, 5540, 1262, and 2582). These frequency responses can match well with the specification of certain components used in the chirp generator design in accordance with several embodiments of the invention.

[0064] Fig. 8 illustrates a graph of an RF output spectrum in accordance with an embodiment of the invention. As illustrated, the graph shows the output spectrum of a generated chirp signal at RF frequency. As illustrated, the RF chirp signal is between 26 GHz to 26.75 GHz. This synthesized RF chirp signal can be evaluated for signal generation performance.

[0065] Fig. 9 illustrates a graph of chirp output frequency in accordance with an embodiment of the invention. The X-axis of the graph corresponds to time and the Y-axis corresponds to a frequency. As illustrated, the graph illustrates the output frequency offset of a synthesized RF chirp signal. Offset frequency 0 corresponds to the center of chirp frequency band. The chirp frequency band center is 26.8 GHz. There are 2 chirps in this example. The first chirp frequency ranges from 26.4 GHz to 27.2 GHz or -400 MHz to 400 MHz in frequency offset from 26.8 GHz. The second chirp frequency ranges from 26.56 GHz to 27.36 GHz or -240 MHz to 560 MHz in frequency offset from 26.8 GHz. Since the low IF chirp signal is synthesized digitally and has perfectly linear frequency ramp, the corresponding RF chirp signal also has perfectly linear frequency ramp as illustrated in the Fig. 9. Furthermore, the digital synthesized chirp can change frequency ramp direction instantaneously. Accordingly, the same property can be preserved in the RF chirp signal.

[0066] Fig. 10 illustrates a graph of RF carrier phase noise in accordance with an embodiment of the invention. The X-axis of the graph corresponds to an offset frequency (Hz) and the Y-axis corresponds to dBc/Hz. As illustrated, there is a difference of 24 dB between the RF output @ 25.6 GHz and the DAC output @ 1 .6 GHz. As illustrated, the graph shows carrier phase noises of the low IF signal and RF signal. The delta between the two phase noises is about 24 dB or 20*log10(16). In the example illustrated in Fig. 10, 16 is the frequency multiplication ratio. As illustrated, the phase noise performance of the low IF chirp is also preserved in the RF chirp signal.

[0067] Although the present invention has been described in certain specific aspects, many additional modifications and variations would be apparent to those skilled in the art. It is therefore to be understood that the present invention may be practiced otherwise than specifically described, including various changes in the implementation. Thus, embodiments of the present invention should be considered in all respects as illustrative and not restrictive.