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Patent Searching and Data


Title:
TECHNIQUES AND CONFIGURATIONS TO IMPART STRAIN TO INTEGRATED CIRCUIT DEVICES
Document Type and Number:
WIPO Patent Application WO/2011/087609
Kind Code:
A3
Abstract:
Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a first barrier layer coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier layer, the quantum well channel comprising a first material having a first lattice constant, and a source structure coupled to the quantum well channel, the source structure comprising a second material having a second lattice constant, wherein the second lattice constant is different than the first lattice constant to impart a strain on the quantum well channel. Other embodiments may be described and/or claimed.

Inventors:
RADOSAVLJEVIC MARKO (US)
DEWEY GILBERT (US)
MUKHERJEE NILOY (US)
PILLARISETTY RAVI (US)
Application Number:
PCT/US2010/058778
Publication Date:
October 27, 2011
Filing Date:
December 02, 2010
Export Citation:
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Assignee:
INTEL CORP (US)
RADOSAVLJEVIC MARKO (US)
DEWEY GILBERT (US)
MUKHERJEE NILOY (US)
PILLARISETTY RAVI (US)
International Classes:
H01L29/772; H01L21/335
Foreign References:
US20050145882A12005-07-07
US20080064157A12008-03-13
US20070138565A12007-06-21
US20080116485A12008-05-22
Other References:
See also references of EP 2517252A4
Attorney, Agent or Firm:
AUYEUNG, Aloysius T.C. et al. (Williamson & WyattPacwest Center 1211 SW 5th Avenue,Suite 1600-190, Portland Oregon, US)
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