WITH HARDWARE ACCELERATION

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The present disclosure claims priority to U.S. Provisional Patent Application

Serial No. 62/633,397, filed February 21, 2018, which is incorporated by reference herein.

BACKGROUND

[0002] Service assurance is important to network functions virtualization (NFV) and software defined networking (SDN) technologies. Generally, service assurance relates to an application of policies and processes to ensure that services provided over a network satisfies a specified service quality level. For instance, determining a quality of service (QoS) at an endpoint and another endpoint provides a measure of service assurance. Doing so involves monitoring service infrastructure performance at virtualized network functions (VNFs), adherence to performance targets, alerts for threshold violation and appropriate actions. Further, a NFV workload is typically associated with a network QoS requirement, violation of which may result in a provider compensating a customer. Currently, solutions are available to guarantee QoS for aspects such as compute resources and performance, but comprehensive service assurance for a VNF often requires a fine-grained tuning of processor, memory, and network controls per virtual central processing unit (vCPU) and per thread. Service assurance may also require a constant feedback loop to maintain a QoS.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

[0004] FIG. 1 is a simplified diagram of at least one embodiment of a data center for executing workloads with disaggregated resources;

[0005] FIG. 2 is a simplified diagram of at least one embodiment of a pod that may be included in the data center of FIG. 1;

[0006] FIG. 3 is a perspective view of at least one embodiment of a rack that may be included in the pod of FIG. 2;

[0007] FIG. 4 is a side elevation view of the rack of FIG. 3; [0008] FIG. 5 is a perspective view of the rack of FIG. 3 having a sled mounted therein;

[0009] FIG. 6 is a is a simplified block diagram of at least one embodiment of a top side of the sled of FIG. 5;

[0010] FIG. 7 is a simplified block diagram of at least one embodiment of a bottom side of the sled of FIG. 6;

[0011] FIG. 8 is a simplified block diagram of at least one embodiment of a compute sled usable in the data center of FIG. 1;

[0012] FIG. 9 is a top perspective view of at least one embodiment of the compute sled of FIG. 8;

[0013] FIG. 10 is a simplified block diagram of at least one embodiment of an accelerator sled usable in the data center of FIG. 1;

[0014] FIG. 11 is a top perspective view of at least one embodiment of the accelerator sled of FIG. 10;

[0015] FIG. 12 is a simplified block diagram of at least one embodiment of a storage sled usable in the data center of FIG. 1;

[0016] FIG. 13 is a top perspective view of at least one embodiment of the storage sled of FIG. 12;

[0017] FIG. 14 is a simplified block diagram of at least one embodiment of a memory sled usable in the data center of FIG. 1; and

[0018] FIG. 15 is a simplified block diagram of a system that may be established within the data center of FIG. 1 to execute workloads with managed nodes composed of disaggregated resources.

[0019] FIG. 16 is a simplified block diagram of a system providing a quality of experience (QoE) software stack representative of a network service framework used to deploy, orchestrate, and manage services provided by a virtualized network function (VNF);

[0020] FIG. 17 is a simplified block diagram of at least one embodiment of an orchestrator server in the system described relative to FIG. 16;

[0021] FIG. 18 is a simplified block diagram of at least one embodiment of an environment that may be established by the orchestrator server of FIGS. 16 and 17; and

[0022] FIG. 19 is a simplified flow diagram of at least one embodiment of a method for managing service assurance in a network environment, such as the system described relative to FIG. 16. DETAILED DESCRIPTION OF THE DRAWINGS

[0023] While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.

[0024] References in the specification to“one embodiment,”“an embodiment,”“an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of“at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

[0025] The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine- readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).

[0026] In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.

[0027] Referring now to FIG. 1, a data center 100 in which disaggregated resources may cooperatively execute one or more workloads (e.g., applications on behalf of customers) includes multiple pods 110, 120, 130, 140, each of which includes one or more rows of racks. Of course, although data center 100 is shown with multiple pods, in some embodiments, the data center 100 may be embodied as a single pod. As described in more detail herein, each rack houses multiple sleds, each of which may be primarily equipped with a particular type of resource (e.g., memory devices, data storage devices, accelerator devices, general purpose processors), i.e., resources that can be logically coupled to form a composed node, which can act as, for example, a server. In the illustrative embodiment, the sleds in each pod 110, 120, 130, 140 are connected to multiple pod switches (e.g., switches that route data communications to and from sleds within the pod). The pod switches, in turn, connect with spine switches 150 that switch communications among pods (e.g., the pods 110, 120, 130, 140) in the data center 100. In some embodiments, the sleds may be connected with a fabric using Intel Omni-Path technology. In other embodiments, the sleds may be connected with other fabrics, such as InfiniBand or Ethernet. As described in more detail herein, resources within sleds in the data center 100 may be allocated to a group (referred to herein as a “managed node”) containing resources from one or more sleds to be collectively utilized in the execution of a workload. The workload can execute as if the resources belonging to the managed node were located on the same sled. The resources in a managed node may belong to sleds belonging to different racks, and even to different pods 110, 120, 130, 140. As such, some resources of a single sled may be allocated to one managed node while other resources of the same sled are allocated to a different managed node (e.g., one processor assigned to one managed node and another processor of the same sled assigned to a different managed node).

[0028] A data center comprising disaggregated resources, such as data center 100, can be used in a wide variety of contexts, such as enterprise, government, cloud service provider, and communications service provider (e.g., Telco’s), as well in a wide variety of sizes, from cloud service provider mega-data centers that consume over 100,000 sq. ft. to single- or multi-rack installations for use in base stations.

[0029] The disaggregation of resources to sleds comprised predominantly of a single type of resource (e.g., compute sleds comprising primarily compute resources, memory sleds containing primarily memory resources), and the selective allocation and deallocation of the disaggregated resources to form a managed node assigned to execute a workload improves the operation and resource usage of the data center 100 relative to typical data centers comprised of hyperconverged servers containing compute, memory, storage and perhaps additional resources in a single chassis. For example, because sleds predominantly contain resources of a particular type, resources of a given type can be upgraded independently of other resources. Additionally, because different resources types (processors, storage, accelerators, etc.) typically have different refresh rates, greater resource utilization and reduced total cost of ownership may be achieved. For example, a data center operator can upgrade the processors throughout their facility by only swapping out the compute sleds. In such a case, accelerator and storage resources may not be contemporaneously upgraded and, rather, may be allowed to continue operating until those resources are scheduled for their own refresh. Resource utilization may also increase. For example, if managed nodes are composed based on requirements of the workloads that will be running on them, resources within a node are more likely to be fully utilized. Such utilization may allow for more managed nodes to run in a data center with a given set of resources, or for a data center expected to run a given set of workloads, to be built using fewer resources.

[0030] Referring now to FIG. 2, the pod 110, in the illustrative embodiment, includes a set of rows 200, 210, 220, 230 of racks 240. Each rack 240 may house multiple sleds (e.g., sixteen sleds) and provide power and data connections to the housed sleds, as described in more detail herein. In the illustrative embodiment, the racks in each row 200, 210, 220, 230 are connected to multiple pod switches 250, 260. The pod switch 250 includes a set of ports 252 to which the sleds of the racks of the pod 110 are connected and another set of ports 254 that connect the pod 110 to the spine switches 150 to provide connectivity to other pods in the data center 100. Similarly, the pod switch 260 includes a set of ports 262 to which the sleds of the racks of the pod 110 are connected and a set of ports 264 that connect the pod 110 to the spine switches 150. As such, the use of the pair of switches 250, 260 provides an amount of redundancy to the pod 110. For example, if either of the switches 250, 260 fails, the sleds in the pod 110 may still maintain data communication with the remainder of the data center 100 (e.g., sleds of other pods) through the other switch 250, 260. Furthermore, in the illustrative embodiment, the switches 150, 250, 260 may be embodied as dual-mode optical switches, capable of routing both Ethernet protocol communications carrying Internet Protocol (IP) packets and communications according to a second, high-performance link- layer protocol (e.g., Intel’s Omni-Path Architecture’s, InfiniBand, PCI Express) via optical signaling media of an optical fabric.

[0031] It should be appreciated that each of the other pods 120, 130, 140 (as well as any additional pods of the data center 100) may be similarly structured as, and have components similar to, the pod 110 shown in and described in regard to FIG. 2 (e.g., each pod may have rows of racks housing multiple sleds as described above). Additionally, while two pod switches 250, 260 are shown, it should be understood that in other embodiments, each pod 110, 120, 130, 140 may be connected to a different number of pod switches, providing even more failover capacity. Of course, in other embodiments, pods may be arranged differently than the rows-of-racks configuration shown in FIGS. 1-2. For example, a pod may be embodied as multiple sets of racks in which each set of racks is arranged radially, i.e., the racks are equidistant from a center switch.

[0032] Referring now to FIGS. 3-5, each illustrative rack 240 of the data center 100 includes two elongated support posts 302, 304, which are arranged vertically. For example, the elongated support posts 302, 304 may extend upwardly from a floor of the data center 100 when deployed. The rack 240 also includes one or more horizontal pairs 310 of elongated support arms 312 (identified in FIG. 3 via a dashed ellipse) configured to support a sled of the data center 100 as discussed below. One elongated support arm 312 of the pair of elongated support arms 312 extends outwardly from the elongated support post 302 and the other elongated support arm 312 extends outwardly from the elongated support post 304.

[0033] In the illustrative embodiments, each sled of the data center 100 is embodied as a chassis-less sled. That is, each sled has a chassis-less circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage, etc.) are mounted as discussed in more detail below. As such, the rack 240 is configured to receive the chassis less sleds. For example, each pair 310 of elongated support arms 312 defines a sled slot 320 of the rack 240, which is configured to receive a corresponding chassis-less sled. To do so, each illustrative elongated support arm 312 includes a circuit board guide 330 configured to receive the chassis-less circuit board substrate of the sled. Each circuit board guide 330 is secured to, or otherwise mounted to, a top side 332 of the corresponding elongated support arm 312. For example, in the illustrative embodiment, each circuit board guide 330 is mounted at a distal end of the corresponding elongated support arm 312 relative to the corresponding elongated support post 302, 304. For clarity of the Figures, not every circuit board guide 330 may be referenced in each Figure. [0034] Each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 configured to receive the chassis-less circuit board substrate of a sled 400 when the sled 400 is received in the corresponding sled slot 320 of the rack 240. To do so, as shown in FIG. 4, a user (or robot) aligns the chassis-less circuit board substrate of an illustrative chassis-less sled 400 to a sled slot 320. The user, or robot, may then slide the chassis-less circuit board substrate forward into the sled slot 320 such that each side edge 414 of the chassis-less circuit board substrate is received in a corresponding circuit board slot 380 of the circuit board guides 330 of the pair 310 of elongated support arms 312 that define the corresponding sled slot 320 as shown in FIG. 4. By having robotically accessible and robotically manipulable sleds comprising disaggregated resources, each type of resource can be upgraded independently of each other and at their own optimized refresh rate. Furthermore, the sleds are configured to blindly mate with power and data communication cables in each rack 240, enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. As such, in some embodiments, the data center 100 may operate (e.g., execute workloads, undergo maintenance and/or upgrades, etc.) without human involvement on the data center floor. In other embodiments, a human may facilitate one or more maintenance or upgrade operations in the data center 100.

[0035] It should be appreciated that each circuit board guide 330 is dual sided. That is, each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 on each side of the circuit board guide 330. In this way, each circuit board guide 330 can support a chassis-less circuit board substrate on either side. As such, a single additional elongated support post may be added to the rack 240 to turn the rack 240 into a two-rack solution that can hold twice as many sled slots 320 as shown in Fig. 3. The illustrative rack 240 includes seven pairs 310 of elongated support arms 312 that define a corresponding seven sled slots 320, each configured to receive and support a corresponding sled 400 as discussed above. Of course, in other embodiments, the rack 240 may include additional or fewer pairs 310 of elongated support arms 312 (i.e., additional or fewer sled slots 320). It should be appreciated that because the sled 400 is chassis-less, the sled 400 may have an overall height that is different than typical servers. As such, in some embodiments, the height of each sled slot 320 may be shorter than the height of a typical server (e.g., shorter than a single rank unit,“1U”). That is, the vertical distance between each pair 310 of elongated support arms 312 may be less than a standard rack unit“1U.” Additionally, due to the relative decrease in height of the sled slots 320, the overall height of the rack 240 in some embodiments may be shorter than the height of traditional rack enclosures. For example, in some embodiments, each of the elongated support posts 302, 304 may have a length of six feet or less. Again, in other embodiments, the rack 240 may have different dimensions. For example, in some embodiments, the vertical distance between each pair 310 of elongated support arms 312 may be greater than a standard rack until“1U”. In such embodiments, the increased vertical distance between the sleds allows for larger heat sinks to be attached to the physical resources and for larger fans to be used (e.g., in the fan array 370 described below) for cooling each sled, which in turn can allow the physical resources to operate at increased power levels. Further, it should be appreciated that the rack 240 does not include any walls, enclosures, or the like. Rather, the rack 240 is an enclosure-less rack that is opened to the local environment. Of course, in some cases, an end plate may be attached to one of the elongated support posts 302, 304 in those situations in which the rack 240 forms an end-of- row rack in the data center 100.

[0036] In some embodiments, various interconnects may be routed upwardly or downwardly through the elongated support posts 302, 304. To facilitate such routing, each elongated support post 302, 304 includes an inner wall that defines an inner chamber in which interconnects may be located. The interconnects routed through the elongated support posts 302, 304 may be embodied as any type of interconnects including, but not limited to, data or communication interconnects to provide communication connections to each sled slot 320, power interconnects to provide power to each sled slot 320, and/or other types of interconnects.

[0037] The rack 240, in the illustrative embodiment, includes a support platform on which a corresponding optical data connector (not shown) is mounted. Each optical data connector is associated with a corresponding sled slot 320 and is configured to mate with an optical data connector of a corresponding sled 400 when the sled 400 is received in the corresponding sled slot 320. In some embodiments, optical connections between components (e.g., sleds, racks, and switches) in the data center 100 are made with a blind mate optical connection. For example, a door on each cable may prevent dust from contaminating the fiber inside the cable. In the process of connecting to a blind mate optical connector mechanism, the door is pushed open when the end of the cable approaches or enters the connector mechanism. Subsequently, the optical fiber inside the cable may enter a gel within the connector mechanism and the optical fiber of one cable comes into contact with the optical fiber of another cable within the gel inside the connector mechanism. [0038] The illustrative rack 240 also includes a fan array 370 coupled to the cross support arms of the rack 240. The fan array 370 includes one or more rows of cooling fans 372, which are aligned in a horizontal line between the elongated support posts 302, 304. In the illustrative embodiment, the fan array 370 includes a row of cooling fans 372 for each sled slot 320 of the rack 240. As discussed above, each sled 400 does not include any on board cooling system in the illustrative embodiment and, as such, the fan array 370 provides cooling for each sled 400 received in the rack 240. Each rack 240, in the illustrative embodiment, also includes a power supply associated with each sled slot 320. Each power supply is secured to one of the elongated support arms 312 of the pair 310 of elongated support arms 312 that define the corresponding sled slot 320. For example, the rack 240 may include a power supply coupled or secured to each elongated support arm 312 extending from the elongated support post 302. Each power supply includes a power connector configured to mate with a power connector of the sled 400 when the sled 400 is received in the corresponding sled slot 320. In the illustrative embodiment, the sled 400 does not include any on-board power supply and, as such, the power supplies provided in the rack 240 supply power to corresponding sleds 400 when mounted to the rack 240. Each power supply is configured to satisfy the power requirements for its associated sled, which can vary from sled to sled. Additionally, the power supplies provided in the rack 240 can operate independent of each other. That is, within a single rack, a first power supply providing power to a compute sled can provide power levels that are different than power levels supplied by a second power supply providing power to an accelerator sled. The power supplies may be controllable at the sled level or rack level, and may be controlled locally by components on the associated sled or remotely, such as by another sled or an orchestrator.

[0039] Referring now to FIG. 6, the sled 400, in the illustrative embodiment, is configured to be mounted in a corresponding rack 240 of the data center 100 as discussed above. In some embodiments, each sled 400 may be optimized or otherwise configured for performing particular tasks, such as compute tasks, acceleration tasks, data storage tasks, etc. For example, the sled 400 may be embodied as a compute sled 800 as discussed below in regard to FIGS. 8-9, an accelerator sled 1000 as discussed below in regard to FIGS. 10-11, a storage sled 1200 as discussed below in regard to FIGS. 12-13, or as a sled optimized or otherwise configured to perform other specialized tasks, such as a memory sled 1400, discussed below in regard to FIG. 14. [0040] As discussed above, the illustrative sled 400 includes a chassis-less circuit board substrate 602, which supports various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that the circuit board substrate 602 is“chassis less” in that the sled 400 does not include a housing or enclosure. Rather, the chassis-less circuit board substrate 602 is open to the local environment. The chassis-less circuit board substrate 602 may be formed from any material capable of supporting the various electrical components mounted thereon. For example, in an illustrative embodiment, the chassis-less circuit board substrate 602 is formed from an FR-4 glass-reinforced epoxy laminate material. Of course, other materials may be used to form the chassis-less circuit board substrate 602 in other embodiments.

[0041] As discussed in more detail below, the chassis-less circuit board substrate 602 includes multiple features that improve the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602. As discussed, the chassis-less circuit board substrate 602 does not include a housing or enclosure, which may improve the airflow over the electrical components of the sled 400 by reducing those structures that may inhibit air flow. For example, because the chassis-less circuit board substrate 602 is not positioned in an individual housing or enclosure, there is no vertically- arranged backplane (e.g., a backplate of the chassis) attached to the chassis-less circuit board substrate 602, which could inhibit air flow across the electrical components. Additionally, the chassis-less circuit board substrate 602 has a geometric shape configured to reduce the length of the airflow path across the electrical components mounted to the chassis-less circuit board substrate 602. For example, the illustrative chassis-less circuit board substrate 602 has a width 604 that is greater than a depth 606 of the chassis-less circuit board substrate 602. In one particular embodiment, for example, the chassis-less circuit board substrate 602 has a width of about 21 inches and a depth of about 9 inches, compared to a typical server that has a width of about 17 inches and a depth of about 39 inches. As such, an airflow path 608 that extends from a front edge 610 of the chassis-less circuit board substrate 602 toward a rear edge 612 has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of the sled 400. Furthermore, although not illustrated in FIG. 6, the various physical resources mounted to the chassis-less circuit board substrate 602 are mounted in corresponding locations such that no two substantively heat-producing electrical components shadow each other as discussed in more detail below. That is, no two electrical components, which produce appreciable heat during operation (i.e., greater than a nominal heat sufficient enough to adversely impact the cooling of another electrical component), are mounted to the chassis-less circuit board substrate 602 linearly in-line with each other along the direction of the airflow path 608 (i.e., along a direction extending from the front edge 610 toward the rear edge 612 of the chassis-less circuit board substrate 602).

[0042] As discussed above, the illustrative sled 400 includes one or more physical resources 620 mounted to a top side 650 of the chassis-less circuit board substrate 602. Although two physical resources 620 are shown in FIG. 6, it should be appreciated that the sled 400 may include one, two, or more physical resources 620 in other embodiments. The physical resources 620 may be embodied as any type of processor, controller, or other compute circuit capable of performing various tasks such as compute functions and/or controlling the functions of the sled 400 depending on, for example, the type or intended functionality of the sled 400. For example, as discussed in more detail below, the physical resources 620 may be embodied as high-performance processors in embodiments in which the sled 400 is embodied as a compute sled, as accelerator co-processors or circuits in embodiments in which the sled 400 is embodied as an accelerator sled, storage controllers in embodiments in which the sled 400 is embodied as a storage sled, or a set of memory devices in embodiments in which the sled 400 is embodied as a memory sled.

[0043] The sled 400 also includes one or more additional physical resources 630 mounted to the top side 650 of the chassis-less circuit board substrate 602. In the illustrative embodiment, the additional physical resources include a network interface controller (NIC) as discussed in more detail below. Of course, depending on the type and functionality of the sled 400, the physical resources 630 may include additional or other electrical components, circuits, and/or devices in other embodiments.

[0044] The physical resources 620 are communicatively coupled to the physical resources 630 via an input/output (I/O) subsystem 622. The I/O subsystem 622 may be embodied as circuitry and/or components to facilitate input/output operations with the physical resources 620, the physical resources 630, and/or other components of the sled 400. For example, the I/O subsystem 622 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, waveguides, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In the illustrative embodiment, the I/O subsystem 622 is embodied as, or otherwise includes, a double data rate 4 (DDR4) data bus or a DDR5 data bus.

[0045] In some embodiments, the sled 400 may also include a resource-to-resource interconnect 624. The resource-to-resource interconnect 624 may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communications. In the illustrative embodiment, the resource-to-resource interconnect 624 is embodied as a high speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the resource-to-resource interconnect 624 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications.

[0046] The sled 400 also includes a power connector 640 configured to mate with a corresponding power connector of the rack 240 when the sled 400 is mounted in the corresponding rack 240. The sled 400 receives power from a power supply of the rack 240 via the power connector 640 to supply power to the various electrical components of the sled 400. That is, the sled 400 does not include any local power supply (i.e., an on-board power supply) to provide power to the electrical components of the sled 400. The exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the chassis less circuit board substrate 602, which may increase the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602 as discussed above. In some embodiments, voltage regulators are placed on a bottom side 750 (see FIG. 7) of the chassis-less circuit board substrate 602 directly opposite of the processors 820 (see FIG. 8), and power is routed from the voltage regulators to the processors 820 by vias extending through the circuit board substrate 602. Such a configuration provides an increased thermal budget, additional current and/or voltage, and better voltage control relative to typical printed circuit boards in which processor power is delivered from a voltage regulator, in part, by printed circuit traces.

[0047] In some embodiments, the sled 400 may also include mounting features 642 configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the sled 600 in a rack 240 by the robot. The mounting features 642 may be embodied as any type of physical structures that allow the robot to grasp the sled 400 without damaging the chassis-less circuit board substrate 602 or the electrical components mounted thereto. For example, in some embodiments, the mounting features 642 may be embodied as non-conductive pads attached to the chassis-less circuit board substrate 602. In other embodiments, the mounting features may be embodied as brackets, braces, or other similar structures attached to the chassis-less circuit board substrate 602. The particular number, shape, size, and/or make-up of the mounting feature 642 may depend on the design of the robot configured to manage the sled 400.

[0048] Referring now to FIG. 7, in addition to the physical resources 630 mounted on the top side 650 of the chassis-less circuit board substrate 602, the sled 400 also includes one or more memory devices 720 mounted to a bottom side 750 of the chassis-less circuit board substrate 602. That is, the chassis-less circuit board substrate 602 is embodied as a double sided circuit board. The physical resources 620 are communicatively coupled to the memory devices 720 via the I/O subsystem 622. For example, the physical resources 620 and the memory devices 720 may be communicatively coupled by one or more vias extending through the chassis-less circuit board substrate 602. Each physical resource 620 may be communicatively coupled to a different set of one or more memory devices 720 in some embodiments. Alternatively, in other embodiments, each physical resource 620 may be communicatively coupled to each memory device 720.

[0049] The memory devices 720 may be embodied as any type of memory device capable of storing data for the physical resources 620 during operation of the sled 400, such as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4. Such standards (and similar standards) may be referred to as DDR- based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.

[0050] In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include next-generation nonvolatile devices, such as Intel 3D XPoint™ memory or other byte addres sable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory device may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.

[0051] Referring now to FIG. 8, in some embodiments, the sled 400 may be embodied as a compute sled 800. The compute sled 800 is optimized, or otherwise configured, to perform compute tasks. Of course, as discussed above, the compute sled 800 may rely on other sleds, such as acceleration sleds and/or storage sleds, to perform such compute tasks. The compute sled 800 includes various physical resources (e.g., electrical components) similar to the physical resources of the sled 400, which have been identified in FIG. 8 using the same reference numbers. The description of such components provided above in regard to FIGS. 6 and 7 applies to the corresponding components of the compute sled 800 and is not repeated herein for clarity of the description of the compute sled 800.

[0052] In the illustrative compute sled 800, the physical resources 620 are embodied as processors 820. Although only two processors 820 are shown in FIG. 8, it should be appreciated that the compute sled 800 may include additional processors 820 in other embodiments. Illustratively, the processors 820 are embodied as high-performance processors 820 and may be configured to operate at a relatively high power rating. Although the processors 820 generate additional heat operating at power ratings greater than typical processors (which operate at around 155-230 W), the enhanced thermal cooling characteristics of the chassis-less circuit board substrate 602 discussed above facilitate the higher power operation. For example, in the illustrative embodiment, the processors 820 are configured to operate at a power rating of at least 250 W. In some embodiments, the processors 820 may be configured to operate at a power rating of at least 350 W.

[0053] In some embodiments, the compute sled 800 may also include a processor- to- processor interconnect 842. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the processor-to-processor interconnect 842 may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect 842 communications. In the illustrative embodiment, the processor-to-processor interconnect 842 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the processor-to-processor interconnect 842 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high speed point-to-point interconnect dedicated to processor-to-processor communications.

[0054] The compute sled 800 also includes a communication circuit 830. The illustrative communication circuit 830 includes a network interface controller (NIC) 832, which may also be referred to as a host fabric interface (HFI). The NIC 832 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, or other devices that may be used by the compute sled 800 to connect with another compute device (e.g., with other sleds 400). In some embodiments, the NIC 832 may be embodied as part of a system- on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 832 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 832. In such embodiments, the local processor of the NIC 832 may be capable of performing one or more of the functions of the processors 820. Additionally or alternatively, in such embodiments, the local memory of the NIC 832 may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and/or other levels.

[0055] The communication circuit 830 is communicatively coupled to an optical data connector 834. The optical data connector 834 is configured to mate with a corresponding optical data connector of the rack 240 when the compute sled 800 is mounted in the rack 240. Illustratively, the optical data connector 834 includes a plurality of optical fibers which lead from a mating surface of the optical data connector 834 to an optical transceiver 836. The optical transceiver 836 is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector. Although shown as forming part of the optical data connector 834 in the illustrative embodiment, the optical transceiver 836 may form a portion of the communication circuit 830 in other embodiments.

[0056] In some embodiments, the compute sled 800 may also include an expansion connector 840. In such embodiments, the expansion connector 840 is configured to mate with a corresponding connector of an expansion chassis-less circuit board substrate to provide additional physical resources to the compute sled 800. The additional physical resources may be used, for example, by the processors 820 during operation of the compute sled 800. The expansion chassis-less circuit board substrate may be substantially similar to the chassis-less circuit board substrate 602 discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion chassis-less circuit board substrate may depend on the intended functionality of the expansion chassis-less circuit board substrate. For example, the expansion chassis-less circuit board substrate may provide additional compute resources, memory resources, and/or storage resources. As such, the additional physical resources of the expansion chassis-less circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application- specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.

[0057] Referring now to FIG. 9, an illustrative embodiment of the compute sled 800 is shown. As shown, the processors 820, communication circuit 830, and optical data connector 834 are mounted to the top side 650 of the chassis-less circuit board substrate 602. Any suitable attachment or mounting technology may be used to mount the physical resources of the compute sled 800 to the chassis-less circuit board substrate 602. For example, the various physical resources may be mounted in corresponding sockets (e.g., a processor socket), holders, or brackets. In some cases, some of the electrical components may be directly mounted to the chassis-less circuit board substrate 602 via soldering or similar techniques.

[0058] As discussed above, the individual processors 820 and communication circuit

830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. In the illustrative embodiment, the processors 820 and communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those physical resources are linearly in-line with others along the direction of the airflow path 608. It should be appreciated that, although the optical data connector 834 is in-line with the communication circuit 830, the optical data connector 834 produces no or nominal heat during operation.

[0059] The memory devices 720 of the compute sled 800 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the processors 820 located on the top side 650 via the I/O subsystem 622. Because the chassis-less circuit board substrate 602 is embodied as a double sided circuit board, the memory devices 720 and the processors 820 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis less circuit board substrate 602. Of course, each processor 820 may be communicatively coupled to a different set of one or more memory devices 720 in some embodiments. Alternatively, in other embodiments, each processor 820 may be communicatively coupled to each memory device 720. In some embodiments, the memory devices 720 may be mounted to one or more memory mezzanines on the bottom side of the chassis-less circuit board substrate 602 and may interconnect with a corresponding processor 820 through a ball-grid array.

[0060] Each of the processors 820 includes a heatsink 850 secured thereto. Due to the mounting of the memory devices 720 to the bottom side 750 of the chassis-less circuit board substrate 602 (as well as the vertical spacing of the sleds 400 in the corresponding rack 240), the top side 650 of the chassis-less circuit board substrate 602 includes additional“free” area or space that facilitates the use of heatsinks 850 having a larger size relative to traditional heatsinks used in typical servers. Additionally, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602, none of the processor heatsinks 850 include cooling fans attached thereto. That is, each of the heatsinks 850 is embodied as a fan-less heatsink. In some embodiments, the heat sinks 850 mounted atop the processors 820 may overlap with the heat sink attached to the communication circuit 830 in the direction of the airflow path 608 due to their increased size, as illustratively suggested by FIG. 9.

[0061] Referring now to FIG. 10, in some embodiments, the sled 400 may be embodied as an accelerator sled 1000. The accelerator sled 1000 is configured, to perform specialized compute tasks, such as machine learning, encryption, hashing, or other computational-intensive task. In some embodiments, for example, a compute sled 800 may offload tasks to the accelerator sled 1000 during operation. The accelerator sled 1000 includes various components similar to components of the sled 400 and/or compute sled 800, which have been identified in FIG. 10 using the same reference numbers. The description of such components provided above in regard to FIGS. 6, 7, and 8 apply to the corresponding components of the accelerator sled 1000 and is not repeated herein for clarity of the description of the accelerator sled 1000.

[0062] In the illustrative accelerator sled 1000, the physical resources 620 are embodied as accelerator circuits 1020. Although only two accelerator circuits 1020 are shown in FIG. 10, it should be appreciated that the accelerator sled 1000 may include additional accelerator circuits 1020 in other embodiments. For example, as shown in FIG. 11, the accelerator sled 1000 may include four accelerator circuits 1020 in some embodiments. The accelerator circuits 1020 may be embodied as any type of processor, co processor, compute circuit, or other device capable of performing compute or processing operations. For example, the accelerator circuits 1020 may be embodied as, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), neuromorphic processor units, quantum computers, machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.

[0063] In some embodiments, the accelerator sled 1000 may also include an accelerator-to-accelerator interconnect 1042. Similar to the resource-to-resource interconnect 624 of the sled 600 discussed above, the accelerator-to-accelerator interconnect 1042 may be embodied as any type of communication interconnect capable of facilitating accelerator-to- accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect 1042 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the accelerator-to-accelerator interconnect 1042 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. In some embodiments, the accelerator circuits 1020 may be daisy-chained with a primary accelerator circuit 1020 connected to the NIC 832 and memory 720 through the I/O subsystem 622 and a secondary accelerator circuit 1020 connected to the NIC 832 and memory 720 through a primary accelerator circuit 1020. [0064] Referring now to FIG. 11, an illustrative embodiment of the accelerator sled

1000 is shown. As discussed above, the accelerator circuits 1020, communication circuit 830, and optical data connector 834 are mounted to the top side 650 of the chassis-less circuit board substrate 602. Again, the individual accelerator circuits 1020 and communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other as discussed above. The memory devices 720 of the accelerator sled 1000 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 600. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the accelerator circuits 1020 located on the top side 650 via the I/O subsystem 622 (e.g., through vias). Further, each of the accelerator circuits 1020 may include a heatsink 1070 that is larger than a traditional heatsink used in a server. As discussed above with reference to the heatsinks 870, the heatsinks 1070 may be larger than traditional heatsinks because of the“free” area provided by the memory resources 720 being located on the bottom side 750 of the chassis-less circuit board substrate 602 rather than on the top side 650.

[0065] Referring now to FIG. 12, in some embodiments, the sled 400 may be embodied as a storage sled 1200. The storage sled 1200 is configured, to store data in a data storage 1250 local to the storage sled 1200. For example, during operation, a compute sled 800 or an accelerator sled 1000 may store and retrieve data from the data storage 1250 of the storage sled 1200. The storage sled 1200 includes various components similar to components of the sled 400 and/or the compute sled 800, which have been identified in FIG. 12 using the same reference numbers. The description of such components provided above in regard to FIGS. 6, 7, and 8 apply to the corresponding components of the storage sled 1200 and is not repeated herein for clarity of the description of the storage sled 1200.

[0066] In the illustrative storage sled 1200, the physical resources 620 are embodied as storage controllers 1220. Although only two storage controllers 1220 are shown in FIG. 12, it should be appreciated that the storage sled 1200 may include additional storage controllers 1220 in other embodiments. The storage controllers 1220 may be embodied as any type of processor, controller, or control circuit capable of controlling the storage and retrieval of data into the data storage 1250 based on requests received via the communication circuit 830. In the illustrative embodiment, the storage controllers 1220 are embodied as relatively low-power processors or controllers. For example, in some embodiments, the storage controllers 1220 may be configured to operate at a power rating of about 75 watts. [0067] In some embodiments, the storage sled 1200 may also include a controller-to- controller interconnect 1242. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1242 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1242 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1242 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high speed point-to-point interconnect dedicated to processor-to-processor communications.

[0068] Referring now to FIG. 13, an illustrative embodiment of the storage sled 1200 is shown. In the illustrative embodiment, the data storage 1250 is embodied as, or otherwise includes, a storage cage 1252 configured to house one or more solid state drives (SSDs) 1254. To do so, the storage cage 1252 includes a number of mounting slots 1256, each of which is configured to receive a corresponding solid state drive 1254. Each of the mounting slots 1256 includes a number of drive guides 1258 that cooperate to define an access opening 1260 of the corresponding mounting slot 1256. The storage cage 1252 is secured to the chassis-less circuit board substrate 602 such that the access openings face away from (i.e., toward the front of) the chassis-less circuit board substrate 602. As such, solid state drives 1254 are accessible while the storage sled 1200 is mounted in a corresponding rack 204. For example, a solid state drive 1254 may be swapped out of a rack 240 (e.g., via a robot) while the storage sled 1200 remains mounted in the corresponding rack 240.

[0069] The storage cage 1252 illustratively includes sixteen mounting slots 1256 and is capable of mounting and storing sixteen solid state drives 1254. Of course, the storage cage 1252 may be configured to store additional or fewer solid state drives 1254 in other embodiments. Additionally, in the illustrative embodiment, the solid state drivers are mounted vertically in the storage cage 1252, but may be mounted in the storage cage 1252 in a different orientation in other embodiments. Each solid state drive 1254 may be embodied as any type of data storage device capable of storing long term data. To do so, the solid state drives 1254 may include volatile and non-volatile memory devices discussed above.

[0070] As shown in FIG. 13, the storage controllers 1220, the communication circuit

830, and the optical data connector 834 are illustratively mounted to the top side 650 of the chassis-less circuit board substrate 602. Again, as discussed above, any suitable attachment or mounting technology may be used to mount the electrical components of the storage sled 1200 to the chassis-less circuit board substrate 602 including, for example, sockets (e.g., a processor socket), holders, brackets, soldered connections, and/or other mounting or securing techniques.

[0071] As discussed above, the individual storage controllers 1220 and the communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. For example, the storage controllers 1220 and the communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those electrical components are linearly in-line with each other along the direction of the airflow path 608.

[0072] The memory devices 720 of the storage sled 1200 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the storage controllers 1220 located on the top side 650 via the I/O subsystem 622. Again, because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the storage controllers 1220 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Each of the storage controllers 1220 includes a heatsink 1270 secured thereto. As discussed above, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602 of the storage sled 1200, none of the heatsinks 1270 include cooling fans attached thereto. That is, each of the heatsinks 1270 is embodied as a fan-less heatsink.

[0073] Referring now to FIG. 14, in some embodiments, the sled 400 may be embodied as a memory sled 1400. The storage sled 1400 is optimized, or otherwise configured, to provide other sleds 400 (e.g., compute sleds 800, accelerator sleds 1000, etc.) with access to a pool of memory (e.g., in two or more sets 1430, 1432 of memory devices 720) local to the memory sled 1200. For example, during operation, a compute sled 800 or an accelerator sled 1000 may remotely write to and/or read from one or more of the memory sets 1430, 1432 of the memory sled 1200 using a logical address space that maps to physical addresses in the memory sets 1430, 1432. The memory sled 1400 includes various components similar to components of the sled 400 and/or the compute sled 800, which have been identified in FIG. 14 using the same reference numbers. The description of such components provided above in regard to FIGS. 6, 7, and 8 apply to the corresponding components of the memory sled 1400 and is not repeated herein for clarity of the description of the memory sled 1400.

[0074] In the illustrative memory sled 1400, the physical resources 620 are embodied as memory controllers 1420. Although only two memory controllers 1420 are shown in FIG. 14, it should be appreciated that the memory sled 1400 may include additional memory controllers 1420 in other embodiments. The memory controllers 1420 may be embodied as any type of processor, controller, or control circuit capable of controlling the writing and reading of data into the memory sets 1430, 1432 based on requests received via the communication circuit 830. In the illustrative embodiment, each memory controller 1420 is connected to a corresponding memory set 1430, 1432 to write to and read from memory devices 720 within the corresponding memory set 1430, 1432 and enforce any permissions (e.g., read, write, etc.) associated with sled 400 that has sent a request to the memory sled 1400 to perform a memory access operation (e.g., read or write).

[0075] In some embodiments, the memory sled 1400 may also include a controller- to- controller interconnect 1442. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1442 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1442 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1442 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high speed point-to-point interconnect dedicated to processor-to-processor communications. As such, in some embodiments, a memory controller 1420 may access, through the controller-to- controller interconnect 1442, memory that is within the memory set 1432 associated with another memory controller 1420. In some embodiments, a scalable memory controller is made of multiple smaller memory controllers, referred to herein as“chiplets”, on a memory sled (e.g., the memory sled 1400). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)). The combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels). In some embodiments, the memory controllers 1420 may implement a memory interleave (e.g., one memory address is mapped to the memory set 1430, the next memory address is mapped to the memory set 1432, and the third address is mapped to the memory set 1430, etc.). The interleaving may be managed within the memory controllers 1420, or from CPU sockets (e.g., of the compute sled 800) across network links to the memory sets 1430, 1432, and may improve the latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device.

[0076] Further, in some embodiments, the memory sled 1400 may be connected to one or more other sleds 400 (e.g., in the same rack 240 or an adjacent rack 240) through a waveguide, using the waveguide connector 1480. In the illustrative embodiment, the waveguides are 64 millimeter waveguides that provide 16 Rx (i.e., receive) lanes and 16 Tx (i.e., transmit) lanes. Each lane, in the illustrative embodiment, is either 16 GHz or 32 GHz. In other embodiments, the frequencies may be different. Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets 1430, 1432) to another sled (e.g., a sled 400 in the same rack 240 or an adjacent rack 240 as the memory sled 1400) without adding to the load on the optical data connector 834.

[0077] Referring now to FIG. 15, a system for executing one or more workloads (e.g., applications) may be implemented in accordance with the data center 100. In the illustrative embodiment, the system 1510 includes an orchestrator server 1520, which may be embodied as a managed node comprising a compute device (e.g., a processor 820 on a compute sled 800) executing management software (e.g., a cloud operating environment, such as OpenStack) that is communicatively coupled to multiple sleds 400 including a large number of compute sleds 1530 (e.g., each similar to the compute sled 800), memory sleds 1540 (e.g., each similar to the memory sled 1400), accelerator sleds 1550 (e.g., each similar to the memory sled 1000), and storage sleds 1560 (e.g., each similar to the storage sled 1200). One or more of the sleds 1530, 1540, 1550, 1560 may be grouped into a managed node 1570, such as by the orchestrator server 1520, to collectively perform a workload (e.g., an application 1532 executed in a virtual machine or in a container). The managed node 1570 may be embodied as an assembly of physical resources 620, such as processors 820, memory resources 720, accelerator circuits 1020, or data storage 1250, from the same or different sleds 400. Further, the managed node may be established, defined, or“spun up” by the orchestrator server 1520 at the time a workload is to be assigned to the managed node or at any other time, and may exist regardless of whether any workloads are presently assigned to the managed node. In the illustrative embodiment, the orchestrator server 1520 may selectively allocate and/or deallocate physical resources 620 from the sleds 400 and/or add or remove one or more sleds 400 from the managed node 1570 as a function of quality of service (QoS) targets (e.g., performance targets associated with a throughput, latency, instructions per second, etc.) associated with a service level agreement for the workload (e.g., the application 1532). In doing so, the orchestrator server 1520 may receive telemetry data indicative of performance conditions (e.g., throughput, latency, instructions per second, etc.) in each sled 400 of the managed node 1570 and compare the telemetry data to the quality of service targets to determine whether the quality of service targets are being satisfied. The orchestrator server 1520 may additionally determine whether one or more physical resources may be deallocated from the managed node 1570 while still satisfying the QoS targets, thereby freeing up those physical resources for use in another managed node (e.g., to execute a different workload). Alternatively, if the QoS targets are not presently satisfied, the orchestrator server 1520 may determine to dynamically allocate additional physical resources to assist in the execution of the workload (e.g., the application 1532) while the workload is executing. Similarly, the orchestrator server 1520 may determine to dynamically deallocate physical resources from a managed node if the orchestrator server 1520 determines that deallocating the physical resource would result in QoS targets still being met.

[0078] Additionally, in some embodiments, the orchestrator server 1520 may identify trends in the resource utilization of the workload (e.g., the application 1532), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application 1532) and pre-emptively identifying available resources in the data center 100 and allocating them to the managed node 1570 (e.g., within a predefined time period of the associated phase beginning). In some embodiments, the orchestrator server 1520 may model performance based on various latencies and a distribution scheme to place workloads among compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in the data center 100. For example, the orchestrator server 1520 may utilize a model that accounts for the performance of resources on the sleds 400 (e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA). As such, the orchestrator server 1520 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center 100 (e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and the sled 400 on which the resource is located). [0079] In some embodiments, the orchestrator server 1520 may generate a map of heat generation in the data center 100 using telemetry data (e.g., temperatures, fan speeds, etc.) reported from the sleds 400 and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in the data center 100. Additionally or alternatively, in some embodiments, the orchestrator server 1520 may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within the data center 100 and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes. The orchestrator server 1520 may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in the data center 100.

[0080] To reduce the computational load on the orchestrator server 1520 and the data transfer load on the network, in some embodiments, the orchestrator server 1520 may send self-test information to the sleds 400 to enable each sled 400 to locally (e.g., on the sled 400) determine whether telemetry data generated by the sled 400 satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). Each sled 400 may then report back a simplified result (e.g., yes or no) to the orchestrator server 1520, which the orchestrator server 1520 may utilize in determining the allocation of resources to managed nodes.

[0081] Referring now to FIG. 16, a block diagram is provided for a system 1600 for a quality of experience (QoE) software stack representative of a network service framework used to deploy, orchestrate, and manage services provided by a virtualized network function (VNF) that can execute in the system 1510. As further described herein, the network service framework uses compute-, network-, and memory-based performance scores and resource allocation remediation based thereon to provide service assurance in the system 1510. The system 1600 is mapped to an industry framework based on QoE. The system 1600 provides a quality of service (QoS) per virtualized network function (VNF) as a combination of QoS per CPU thread and data plane development library (e.g., Data Plane Development Kit (DPDK))- based QoS per poll mode driver (PMD) thread. Further, the network service framework provides a re-calibration per second using a monitoring and resource assessment agent on a QoS to QoE share. The resource assessment agent may adjust resources to maintain QoE in a VNF (or other virtual machine (VM)) within a given range.

[0082] The network service framework provided by the system 1600 includes the

QoE monitor, a service level objective (SLO) monitor, a predicted QoS monitor, an SLO agent, a predicted QoS agent, a CPU service compute unit (SCU) management agent, a network service network unit (SNU) management agent, a platform telemetry collector agent, a remediation agent, and a virtual machine manager (VMM), atop the underlying hardware (HW). Using one or more of such components, the system 1600 provides network and compute capability, performance QoS, reliability (e.g., in network bandwidth and CPU cycles), and availability (e.g., by a periodic management agent recalculation of SCUs and SNUs). In some embodiments, the system 1600 provides an autonomic environment that includes a QoE model for an end-user and a functional mapping of QoE parameters to workload SLO parameters. For instance, components in the system 1600 may divide a workload characteristic into a VNF resource and SLO definition which together may form a workload SLO. Further, the system 1600 provides a capacity planner that captures metrics and scores relating to resources such as compute, network, and acceleration. Doing so enables discovery of capacity, availability, and hardware suited to a given SLO. Further, the platform telemetry collector agent monitors and collects metrics used to detect instances where the metrics fall outside a range for a given SLO. The system 1600 includes components (e.g., the predicted QoS monitor and predicted QoS agent) that predict for an actual service level relative to a required (e.g., a target) service level based on the aforementioned mappings to a QoE. The remediation agent may perform actions to mitigate or restore resources to a desired service level.

[0083] In some embodiments, the sled devices described relative to FIGS. 1-15 may implement the network service framework of system 1600. Illustratively, the system 1600 provides the orchestrator server 1520, a compute sled 1610, memory sled 1620, and an accelerator sled 1640, each interconnected with a network 1640 (e.g., the internet). The orchestrator server 1520 includes a service management logic unit 1602, which may be embodied as any device or circuitry to carry out the functions described herein, such as receiving CPU and network metrics from agents 1614, 1624, and 1644 executing in the compute sled 1610, memory sled 1620, and accelerator sled 1640, respectively.

[0084] The illustrative compute sled 1610 includes an application 1612 (e.g., a workload to execute on behalf of a user) and an agent 1614 configured to collect compute and network metrics. The agent 1614 may then determine, from the compute and network metrics, service compute units (SCUs) and service network units (SNUs) which indicate available compute and network resources available to service a workload, e.g., an application.

[0085] The illustrative memory sled 1620 includes one or more memory devices 1622

(e.g., volatile and non-volatile memory devices) and an agent 1624. Similar to the agent 1614, the agent 1624 may collect compute and network metrics and calculate SCUs and SNUs. The illustrative accelerator sled 1630 includes one or more accelerator devices 1632 (e.g., field programmable gate arrays (FGPAs), application-specific integrated circuits (ASICs), graphical processing units (GPU), etc.) and an agent 1634 that collects compute and network metrics to calculate SCUs and SNUs. Note, the system 1600 may include multiple compute sleds 1610, memory sleds 1620, and accelerator sleds 1630.

[0086] Further, the components of the system 1600 (e.g., the agents, monitors, and telemetry collectors) may be implemented as accelerated entities, e.g., executed on one or more accelerator sleds 1630 or accelerators executing on other components in the system 1600. To avoid compute platform cycles from being consumed by those components, an accelerator device (e.g., a field-programmable gate array (FPGA) derivative or acceleration in package) may allow a given tenant of a system 1600 to register accelerated kernel bit streams for monitoring, predicting, and processing telemetry. The acceleration may include proprietary system QoE accelerated logic that is configured to route tenant telemetry from a converged telemetry architecture to each of the registered bit streams. Doing so allows a seamless routing of callbacks from the accelerated kernel bit streams to the CPU and other components. The accelerated logic includes accelerated kernel bit stream monitors, agents, and telemetry processors for each tenant. The accelerated logic also exposes accelerated functions that can be used by agents (e.g., for functions such as Fast Fourier Transform (FFT)). Further, the accelerated logic manages and routes flows between accelerated components and non-accelerated components.

[0087] Referring now to FIG. 17, the orchestrator server 1520 may be embodied as any type of compute device capable of performing the functions described herein. As shown, the illustrative orchestrator server 1520 includes a compute engine 1702, an input/output (I/O) subsystem 1708, communication circuitry 1710, and one or more data storage devices 1714. Of course, in other embodiments, the orchestrator server 1520 may include other or additional components, such as those commonly found in a computer (e.g., display, peripheral devices 1716, etc.). Additionally, in some embodiments, one or more of the illustrative components may be incorporated in, or otherwise form a portion of, another component.

[0088] The compute engine 1702 may be embodied as any type of device or collection of devices capable of performing various compute functions described below. In some embodiments, the compute engine 1702 may be embodied as a single device such as an integrated circuit, an embedded system, a field-programmable gate array (FPGA), a system- on-a-chip (SOC), or other integrated system or device. Additionally, in some embodiments, the compute engine 1702 includes or is embodied as a processor 1704 and a memory 1706. The processor 1704 may be embodied as any type of processor capable of performing the functions described herein. For example, the processor 1704 may be embodied as a single or multi-core processor(s), a microcontroller, or other processor or processing/controlling circuit. In some embodiments, the processor 1704 may be embodied as, include, or be coupled to an FPGA, an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein. As shown, the processor 1704 may also include the aforementioned service management logic unit 1602.

[0089] The memory 1706 may be embodied as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory or data storage capable of performing the functions described herein. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.

[0090] In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include nonvolatile devices, such as a three dimensional crosspoint memory device (e.g., Intel 3D XPoint™ memory), or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)- MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product.

[0091] In some embodiments, 3D crosspoint memory (e.g., Intel 3D XPoint™ memory) may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. In some embodiments, all or a portion of the memory 1706 may be integrated into the processor 1704. In operation, the memory 1706 may store various software and data used during operation such as task request data, kernel map data, telemetry data, applications, programs, libraries, and drivers.

[0092] The compute engine 1702 is communicatively coupled to other components of the orchestrator server 1520 via the I/O subsystem 1708, which may be embodied as circuitry and/or components to facilitate input/output operations with the compute engine 1702 (e.g., with the processor 1704 and/or the memory 1706) and other components of the orchestrator server 1520. For example, the I/O subsystem 1708 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem 1708 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with one or more of the processor 1704, the memory 1706, and other components of the orchestrator server 1520, into the compute engine 1702.

[0093] The communication circuitry 1710 may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications over the network 1640 between the orchestrator server 1520 and another compute device (e.g., the compute sled 1610, the memory sled 1620, the accelerator sled 1640, etc.). The communication circuitry 1710 may be configured to use any one or more communication technology (e.g., wired or wireless communications) and associated protocols (e.g., Ethernet, Bluetooth®, Wi Fi®, WiMAX, etc.) to effect such communication.

[0094] The illustrative communication circuitry 1710 includes a network interface controller (NIC) 1712, which may also be referred to as a host fabric interface (HFI). The NIC 1712 may be embodied as one or more add-in-boards, daughter cards, network interface cards, controller chips, chipsets, or other devices that may be used by the orchestrator server 1520 to connect with another compute device (e.g., the compute sled 1610, the memory sled 1620, the accelerator sled 1640, etc.). In some embodiments, the NIC 1712 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 1712 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 1712. In such embodiments, the local processor of the NIC 1712 may be capable of performing one or more of the functions of the compute engine 1702 described herein. Additionally or alternatively, in such embodiments, the local memory of the NIC 1712 may be integrated into one or more components of the orchestrator server 1520 at the board level, socket level, chip level, and/or other levels.

[0095] The one or more illustrative data storage devices 1714, may be embodied as any type of devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices. Each data storage device 1714 may include a system partition that stores data and firmware code for the data storage device 1714. Each data storage device 1714 may also include an operating system partition that stores data files and executables for an operating system. [0096] Additionally or alternatively, the orchestrator server 1520 may include one or more peripheral devices 1716. Such peripheral devices 1716 may include any type of peripheral device commonly found in a compute device such as a display, speakers, a mouse, a keyboard, and/or other input/output devices, interface devices, and/or other peripheral devices. Further, each of the sleds 1610, 1620, and 1630 may include comparable components to that of the orchestrator server 1520, with possibly the exception of the sleds 1610, 1620, and 1630 omitting the service management logic unit 1602.

[0097] Referring now to FIG. 18, the orchestrator server 1520 may establish an environment 1800 during operation. The illustrative environment 1800 includes a network communicator 1820 and a service manager 1830. Each of the components of the environment 1800 may be embodied as hardware, firmware, software, or a combination thereof. As such, in some embodiments, one or more of the components of the environment 1800 may be embodied as circuitry or a collection of electrical devices (e.g., network communicator circuitry 1820, service manager circuitry 1830, etc.). It should be appreciated that, in such embodiments, one or more of the network communicator circuitry 1820 or service manager circuitry 1830 may form a portion of one or more of the compute engine 1702, communication circuitry 1710, the I/O subsystem 1708, and/or other components of the orchestrator server 1520.

[0098] In the illustrative environment 1800, the network communicator 1820, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from the orchestrator server 1520, respectively. To do so, the network communicator 1820 is configured to receive and process data packets from one system or computing device (e.g., the compute sled 1610) and to prepare and send data packets to another computing device or system (e.g., the memory sled 1620, the accelerator sled 1630). Accordingly, in some embodiments, at least a portion of the functionality of the network communicator 1820 may be performed by the communication circuitry 1710, and, in the illustrative embodiment, by the NIC 1712.

[0099] The service manager 1830, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof, is configured to coordinate management of compute and network resources according to the techniques described herein. To do so, in the illustrative embodiment, the service manager 1830 includes a monitor component 1832, a prediction component 1834, and a remediation component 1836.

[00100] The monitor component 1832, in the illustrative embodiment, is configured to receive a CPU and network metrics from sleds in the system 1600. In addition, the monitor component 1832 is to receive an indication of an amount of available service compute units (SCUs) and service network units (SNUs). Each of the SCUs and SNUs are logical representations in the service manager 1830 of available compute units and network units on compute devices (e.g., the compute sled 1610) in the system 1600. To receive the metrics, the monitor component 1832 may communicate with the agents executing on devices in the system 1600, such as the agents 1614, 1624, and 1634. The monitor component 1832 is also to determine whether a given resource is satisfying SLO (service level objective) requirements, e.g., specified within a service level agreement (SLA).

[00101] The prediction component 1834, in the illustrative embodiment, is configured to receive available SNU data and SCU data and determine compute devices in the system 1600 that are capable of providing resources, such as in launching a virtual machine (VM) instance. The prediction component 1834 may evaluate, for example, an SLA and quality of service (QoS) requirements associated with a given user to determine a suitable compute device, of the compute devices associated with available SCU and SNU units that satisfies SLOs, which may also be representative of SLO units in the service manager 1830.

[00102] The remediation component 1836, in the illustrative embodiment, is configured to, upon a determination that one of the compute or network resources is not satisfying (or is predicted to not satisfy) a given SLO, determine and generate one or more remediation actions. Example remediation actions include allocating compute and network resources to a given compute sled, relocating a VM to another compute sled, allocating resources to an accelerator sled, and the like. The remediation component 1836 may also cause affected devices to perform the remediation action generated.

[00103] Referring now to LIG. 19, the orchestrator server 1520 (e.g., one or more of the sleds in system 1600) incorporating the components of the system 1600, in execution, may perform a method 1900 to manage service assurance in the system 1600. Lor example, the method 1900 may be performed in launching a given virtual machine (VM) on a compute sled. In block 1902, available SCUs and SNUs are determined. Lor instance, to do so, in block 1904, the orchestrator server 1520 determines available SCUs and SNUs as a function of collected CPU and network metrics from agents executing on compute devices. Particularly, the agents executing in compute sleds determine an amount of available SCUs and SNUs at the host and publish the amount to quality of experience (QoE) and SLO monitors executing in the system 1600. An SCU defines a compute capability. An SNU defines network bandwidth required for a VM. The QoE and SLO monitors, for example, may execute on the orchestrator server 1520. The amount of free SCETs and SNUs can be determined by using CPU and network metrics collected by a platform telemetry collection agent.

[00104] In block 1906, a class of service (CLoS) of a QoE is selected for a given VM to be launched (e.g., by a scheduler in the system 1600). In block 1908, the orchestrator server 1520 matches hosts on which the VM can be launched to service levels for the VM. In block 1910, a selected CLoS is mapped to SLO units. In block 1912, the available SNUs, SCUs, and a predicted QoS are evaluated for each host compute device (e.g., compute sled 1610). Based on such, in block 1914, the orchestrator server 1520 places the VM in the appropriate host compute device. In block 1916, the orchestrator server 1520 launches the VM at the host compute device. The result of the prediction by the QoS agent is sent to the remediation agent. In block 1918, the orchestrator server 1520 generates one or more scores associated with the performance of the VM launched in the host compute device.

[00105] In block 1920, the SLO agent may determine whether the performance of the VM satisfies the requested SLO. To do so, the SLO agent calculates metrics received from a performance monitor. The SLO agent may send the results to the remediation agent. The remediation agent may flag the VM if the VM consumes resources of other VMs. If the SLO is not satisfied, then in block 1922, the remediation agent may generate a remediation action. The SCU and SNU agents may receive the remediation action and perform accordingly. The QoE monitor is notified of QoS values per VNL on a periodic basis (e.g., every two seconds).

[00106] An example use case for managing service assurance in a customer NLV environment is now described. A quality solution stack (QSS) monitor at the orchestrator server 1520 may include modules to define a QoE and process templates. The QSS monitor may also include a mapping processor to map QoE to SLO requirements and a module to define SLOs. The QSS monitor may also include a capacity planner module that interfaces with QSS agents at each host. An analytics module provided by the QSS monitor may also evaluate specialized metrics. The QSS monitor also provides a capacity calculator to estimate capacity at cluster level. A QSS agent includes a capacity calculator at the host level. The QSS agent also monitors telemetry and QoE at a per- VNL level. The QSS agent also enforces SLO requirements. For example, the QSS agent includes the SCU and SNU agents and the remediation agents previously described. The SCU and SNU agents may allocate and adjust compute/network resources. The remediation agent may enforce policy based on output by the SCU and SNU agents. Further, a virtualized infrastructure manager (VIM) layer may include filters and weights for a scheduler based on metrics calculated by the QSS monitor. The VIM layer also provides configurations and databases for the system 1510.

[00107] An example mapping of QoE to SLO to QoS is now described relative to the application QoE to VMs. QoS is calculated at each control plane aggregate based on an infrastructure VM aggregate and an application compute and data VM aggregate. These values are mapped to an application QoE. Monitoring and remediation are performed at each aggregate. QoE management may also be conducted via DPDK controls and HW performance hooks.

[00108] In terms of hardware, embodiments may be adapted based on a software and hardware co-design management and orchestration approach. Doing so allows a lower total cost of ownership (TCO) due to less amount of software management overhead, improved response times by being able to process data in an accelerated fashion, and multi-tenant support.

[00109] In some embodiments, QoS may be defined as a function of delay, jitter, latency, and bandwidth, and QoE may be defined as a function of the QoS. QoE parameters may include round trip time (RTT) and mean opinion score (MOS) at user level. For example, for the RTT of 10,000 UDP packets sent over a network, where PING is defined as the average of all RTTs and JITTER as the 99.9% quantile of all RTT’s minus the minimum RTT may be expressed as: Jitter = 99% of åj ^l l\ ⁰⁰⁰ RTT— min(R7T). MOS at user level translates to decoding time at application level and breaks down to CPU and RAM consumption at the workload level and delays, hops, and packet losses at the network level to retransmissions and delay at the link level. Given Throughput = the control mechanism at each layer may be carried out in the following manner. An expected SLO at that layer for RTT is calculated by PING and based on RFC 6928, or SampleRTT = (1— alpha) * SRTT + alpha * R'. After two RTT measurements are made, the first measurement, SRTT, is initialized to the value of the first measurement, i.e., SRTT = R'. A typical RTT value for voice as ITU-T G. 114 recommends is a maximum of 150 ms one-way latency. If a window size of 64 KB = 0.5 MBits, throughput is 0.5 / 0.15 = 3.3.33 Mbits/s - minimum.

[00110] There is a possibility of a network load of a VNF throttling other VNF (on a same host or compute sled) throughput on the same tenant interface. To handle such scenarios and to ensure a minimum bandwidth to the VNFs, the bandwidth share that each VNF receives in a host may be controlled on the tenant interface. This control parameter may be set using SNU as part of the SLO. Each SNU can be defined as a lowest acceptable throughput (e.g., 1 SNU = 100 kbps).

[00111] The following provides an example SLO definition:

'slo': {

'slo_definition': {

'slos': [

{

‘SCU: 'GIPS',

//

}

{

'value': [‘100: 200: 400: 500'],

'type': 'SNU',

'id': 29,

‘Description’:‘service network unit‘

}

]

}

}

[00112] The following provides an example QoE template definition:

QOE_CLOS:{

‘HICritical’ : {

‘RTT’: {

‘value’: [10,20]

‘units’:‘ms’

}

} ‘MedCritical’ : {

‘RTF: {

‘value’: [21,30]

‘units’:‘ms’

}

}

‘MinCritical’:]

‘RTT’: {

‘value’: [40,50]

‘units’:‘ms’

}

}

}

[00113] In the above, the“value” tag of the SNU has the following format:‘value’: [Min guaranteed downlink SNU : Max downlink SNU: Min guaranteed uplink SNU: Max uplink SNU]

[00114] The following is an example algorithm for QoE class mapping to SLP parameters:

If QOE_CLOS is“HiCrtical”

Assign 2 to 4 SCUs

Assign 400-500 SNUs

If RTT is > max value at the QOE monitor, send an alert to SLO agent.

At the host, Check IPC and cache metrics from performance monitor agent to categorize VNF as compute heavy.

If true, SLO agent is notified which increase SCU resulting in more CPU cycles. If cache misses are high, allocate Cache in BDX systems

If not compute heavy, check IOjxans counter and RX-TX > 90% of SNU categorize as network heavy.

If true, SLO agent increases SNUs.

Use libvirt to add ports to VMs..

Monitor the RTT and jitter at QOE monitor and establish ratios If thresholds for example VM1 are crossed:

Calculate the latency throughput needed. Apply a proportional throttling by DPDK vhost egress policer and ingress policer

Weighted throttling of VMs based on the following ratios. (TBD) ratio of SLO to QOE achieved

If more than 10% VMs are suffering, migrate.

Allocating dynamic pNIC PF in RSD environments

Load balancing by adding pmd threads for the socket which hosts the most suffering VMs.

[00115] Advantageously, VNFs that are launched in the same or different host will get the same bandwidth limits depending on the defined SNFT. In a particular host, the sum of the minimum bandwidth set for all the VNFs in a particular tenant interface should not go beyond the actual throughput achieved by that interface. However, the sum of the maximum bandwidth set may be more than the actual throughput of the tenant interface. The minimum and maximum throughput set cannot go beyond actual throughput of the tenant interface. A particular VNF with a SNFT will have the minimum bandwidth guaranteed and can use up to the maximum throughput provided that the SNU is not used by other VNFs in the same host on that tenant interface.

[00116] In some embodiments, each host or compute sled advertises available SNUs per tenant interfaces periodically to a service assurance manager. The system 1600 may centralize control of all the hosts and help with scheduling the VNFs. The network metrics of each of the VMs in the host are also displayed as graphs for monitoring. The VNF network throughput performance can be increased and latency can be minimized by using a DPDK library. Further, network drivers and forwarding threads are moved to the userspace, which results in increased performance. The physical ports (ethO) attached to tenant bridges are occupied by the poll mode driver, resulting in the kernel losing control of the ports. The VNF interfaces (vnet) attaching to the integration bridges are of type dpdkhostuser. The performance of the VNFs are further improved by increasing the number of forwarding threads and allocating 1G huge pages to the VM. Performance can also be improved by assigning the forwarding threads to CPU cores that are isolated from the operating system scheduling. Performance can also be improved in a NUMA (non-uniform memory access)- aware system by allocating the forwarding threads servicing the physical ports to the CPU cores on the socket where the physical ports are located. Performance can also be improved by assigning the transmitting and receiving thread to the same socket where the forwarding thread is scheduled.

[00117] In some embodiments, ports are managed by DPDK. In such a case, the QoS and rate limiting controls typically cannot be applied. However, open source solutions may provide approaches for doing the ingress and egress throughput control. Further, the ingress and egress network throughput can be controlled by applying the ingress and egress policing rates on the vhost ports connected to the integration bridge by setting the ingress_policing_rate and egress_policing_rate parameter of the port at the integration bridge. However, using this method, the maximum bandwidth of the VNF can be set. In such a case, the SNU minimum and maximum values will be the same, and no oversubscription is implemented. Applications requiring no change in QoS are scheduled on such systems (e.g., mission critical video applications).

[00118] Further, as previously described, embodiments may be adapted to a software and hardware co-design. For instance, a hardware offload architecture may include an interface and management logic, a platform telemetry distributor, a call back manager, and a intellectual property (IP) prediction and telemetry acceleration function. The interface and management logic exposes to a software stack (e.g., of the system 1600) interfaces that allow a particular tenant executing an instance of QoE to instantiate bit streams for the two agents and two predictor components discussed above, as well as a bit stream for an agent responsible to process the telemetry sent by the telemetry distributor.

[00119] The platform telemetry distributor is to collect corresponding performance counters exposed by the platform converged telemetry architecture that is associated to each of the tenants and automatically deliver the counters to the bit stream for processing the telemetry. The bit stream can share (e.g., contemporaneously) the processed data to the different bit-stream predictors. When a particular QoE-accelerated bit stream is registered via the interface and management logic, a tenant can specify what telemetry data the predictor and telemetry processors use.

[00120] The call back manager exposes interfaces for the bit streams to send call backs to the corresponding software entities (e.g., the various QoE managers, CPU, network, etc.). The IP prediction and telemetry acceleration function IP library exposes a set of functions that can be used by the bit streams. The library also provides access accelerated functions that are exposed by proprietary bit stream logic. Further, the software stack, before registering user bit streams, can check what functions are exposed by a given IP via a CPUID mechanism.

EXAMPLES

[00121] Illustrative examples of the technologies disclosed herein are provided below.

An embodiment of the technologies may include any one or more, and any combination of, the examples described below.

[00122] Example 1 includes an orchestrator server for managing service assurance of a platform, the orchestrator server comprising one or more processors; and a memory storing a plurality of instructions, which, when executed on the one or more processors, causes the orchestrator server to receive a request to launch a virtual machine (VM) instance, the request specifying a selection of a class of service (CLoS) of a Quality of Experience (QoS) specification; map the selected CLoS to one or more Service Level Objective (SLO) units, the one or more SLO units being indicative of a compute capability and a required network bandwidth specified in a service level agreement (SLA); launch the VM on a compute device of a plurality of compute devices identified as a function of the mapped SLO units; generate one or more scores associated with a performance of the VM; and determine, as a function of the generated one or more scores, whether the performance of the VM on the compute device satisfies each of the one or more SLO units.

[00123] Example 2 includes the subject matter of Example 1, and wherein the plurality of instructions further causes the orchestrator server to determine, in the platform, a plurality of available service compute units and a plurality of available service network units.

[00124] Example 3 includes the subject matter of any of Examples 1 and 2, and wherein to determine the plurality of available service compute units and the plurality of available service network units comprises to determine the plurality of available service compute units and the plurality of available service network units as a function of collected compute and network metrics from agent applications executing on compute devices in the platform.

[00125] Example 4 includes the subject matter of any of Examples 1-3, and wherein to identify the compute device as a function of the mapped SLO units comprises to evaluate the plurality of available service compute units, the plurality of available service network units, and a predicted quality of service (QoS) of each of the plurality of compute devices. [00126] Example 5 includes the subject matter of any of Examples 1-4, and wherein the plurality of instructions further causes the orchestrator server to place the VM in the identified compute device.

[00127] Example 6 includes the subject matter of any of Examples 1-5, and wherein the plurality of instructions further causes the orchestrator server to, upon a determination that at least one of the SLO units is not satisfied, generate a remediation action to be performed.

[00128] Example 7 includes the subject matter of any of Examples 1-6, and wherein the plurality of instructions further causes the orchestrator server to cause the identified compute device to perform the remediation action.

[00129] Example 8 includes a method for managing service assurance of a platform, comprising receiving, by an orchestrator server, a request to launch a virtual machine (VM) instance, the request specifying a selection of a class of service (CLoS) of a Quality of Experience (QoS) specification; mapping, by the orchestrator server, the selected CLoS to one or more Service Level Objective (SLO) units, the one or more SLO units being indicative of a compute capability and a required network bandwidth specified in a service level agreement (SLA); launching, by the orchestrator server, the VM on a compute device of a plurality of compute devices identified as a function of the mapped SLO units; generating, by the orchestrator server, one or more scores associated with a performance of the VM; and determining, by the orchestrator server, as a function of the generated one or more scores, whether the performance of the VM on the compute device satisfies each of the one or more SLO units.

[00130] Example 9 includes the subject matter of Example 8, and further including determining, in the platform and by the orchestrator server, a plurality of available service compute units and a plurality of available service network units.

[00131] Example 10 includes the subject matter of any of Examples 8 and 9, and wherein determining the plurality of available service compute units and the plurality of available service network units comprises determining, by the orchestrator server, the plurality of available service compute units and the plurality of available service network units as a function of collected compute and network metrics from agent applications executing on compute devices in the platform.

[00132] Example 11 includes the subject matter of any of Examples 8-10, and wherein identifying the compute device as a function of the mapped SLO units comprises evaluating, by the orchestrator server, the plurality of available service compute units, the plurality of available service network units, and a predicted quality of service (QoS) of each of the plurality of compute devices.

[00133] Example 12 includes the subject matter of any of Examples 8-11, and further including placing, by the orchestrator server, the VM in the identified compute device.

[00134] Example 13 includes the subject matter of any of Examples 8-12, and further including, upon determining, by the orchestrator server, that at least one of the SLO units is not satisfied, generating a remediation action to be performed.

[00135] Example 14 includes the subject matter of any of Examples 8-13, and further including causing, by the orchestrator server, the identified compute device to perform the remediation action.

[00136] Example 15 includes an orchestrator server for managing service assurance of a platform, comprising circuitry for receiving a request to launch a virtual machine (VM) instance, the request specifying a selection of a class of service (CLoS) of a Quality of Experience (QoS) specification; means for mapping the selected CLoS to one or more Service Level Objective (SLO) units, the one or more SLO units being indicative of a compute capability and a required network bandwidth specified in a service level agreement (SLA); circuitry for launching the VM on a compute device of a plurality of compute devices identified as a function of the mapped SLO units; means for generating one or more scores associated with a performance of the VM; and means for determining, as a function of the generated one or more scores, whether the performance of the VM on the compute device satisfies each of the one or more SLO units.

[00137] Example 16 includes the subject matter of Example 15, and further including means for determining, in the platform, a plurality of available service compute units and a plurality of available service network units.

[00138] Example 17 includes the subject matter of any of Examples 15 and 16, and wherein the means for determining the plurality of available service compute units and the plurality of available service network units comprises means for determining the plurality of available service compute units and the plurality of available service network units as a function of collected compute and network metrics from agent applications executing on compute devices in the platform.

[00139] Example 18 includes the subject matter of any of Examples 15-17, and further including means for evaluating the plurality of available service compute units, the plurality of available service network units, and a predicted quality of service (QoS) of each of the plurality of compute devices to identify the compute device as a function of the mapped SLO units.

[00140] Example 19 includes the subject matter of any of Examples 15-18, and further including circuitry for placing the VM in the identified compute device.

[00141] Example 20 includes the subject matter of any of Examples 15-19, and further including means for generating a remediation action to be performed upon determining that at least one of the SLO units is not satisfied; and means for causing the identified compute device to perform the remediation action.

[00142] Example 21 includes one or more machine -readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause an orchestrator server to perform the method of any of Examples 8-14.

[00143] Example 22 includes an orchestrator server comprising circuitry for performing the method of any of Examples 8-14.