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Patent Searching and Data


Title:
TEST CIRCUIT AND MEMORY CHIP USING THE TEST CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2021/073128
Kind Code:
A1
Abstract:
The present invention provides a test circuit and a memory chip. The test circuit is used for reading compressed data of a memory. The test circuit comprises a number M of storage blocks, wherein M is an even number greater than or equal to 2. A number N of the M storage blocks form a storage set, wherein N is an even number greater than or equal to 2 and less than or equal to M, and M is an integer multiple of N. The test circuit is characterized by further comprising compressed data reading units. One compressed data reading unit corresponds to one storage set, and each compressed data reading unit is connected to N storage blocks in the corresponding storage set. The compressed data reading units receive a compressed data reading command and address information, and read data in the N storage blocks according to the compressed data reading command and the address information. The present invention has advantages that the size of the memory chip is not additionally increased and test time can be greatly reduced.

Inventors:
WANG, Jia (Xingye AvenueEconomic and Technological Development Are, Hefei Anhui 0, CN)
ZHANG, Liang (Xingye AvenueEconomic and Technological Development Are, Hefei Anhui 0, CN)
LI, Hongwen (Xingye AvenueEconomic and Technological Development Are, Hefei Anhui 0, CN)
Application Number:
CN2020/095339
Publication Date:
April 22, 2021
Filing Date:
June 10, 2020
Export Citation:
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Assignee:
CHANGXIN MEMORY TECHNOLOGIES, INC. (Xingye AvenueEconomic and Technological Development Are, Hefei Anhui 0, CN)
International Classes:
G11C29/40
Attorney, Agent or Firm:
SHANGHAI WINSUN INTELLECTUAL PROPERTY AGENCY (12/F Enterprice Square228 Meiyuan Road, Jingan District, Shanghai 0, CN)
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