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Patent Searching and Data


Title:
TEST CIRCUIT OF MEMORY AND DEVICE
Document Type and Number:
WIPO Patent Application WO/2021/031149
Kind Code:
A1
Abstract:
A test circuit of a memory and a device, which relate to the technical field of chips, and solve the problems with testing in the prior art in which the overhead is too high for the area of a built-in self-test circuit of a memory and in which it is difficult to achieve simultaneous read and write operations on a plurality of ports. The test circuit comprises a test controller (301) and an address signal converter (302). The test controller (301) is used to generate a test address and write test data into a memory (303); the address signal converter (302) is used to receive the test address, convert the test address into a plurality of storage addresses of the test data in the memory (303), and input the plurality of storage addresses into a plurality of address input ports of the memory (303); and the test controller (301) is further used to read data from the plurality of storage addresses, and generate a test result on the basis of the read data.

Inventors:
XU TUANHUI (CN)
Application Number:
PCT/CN2019/101781
Publication Date:
February 25, 2021
Filing Date:
August 21, 2019
Export Citation:
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Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
G11C29/08
Foreign References:
US20030120974A12003-06-26
CN109903805A2019-06-18
CN102013274A2011-04-13
CN1920783A2007-02-28
US6691264B22004-02-10
US9946620B22018-04-17
Other References:
See also references of EP 4012712A4
Attorney, Agent or Firm:
BEIJING ZBSD PATENT & TRADEMARK AGENT LTD. (CN)
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