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Patent Searching and Data


Title:
TIMING TEST METHOD AND DEVICE, AND VR CHIP
Document Type and Number:
WIPO Patent Application WO/2020/042695
Kind Code:
A1
Abstract:
Provided in the present invention are a timing test method and device, and a VR chip. When a timing test is performed on a VR chip in a server board card, a circuit in the VR chip in the server board card is improved so that an enable voltage obtained by the circuit for dividing an input voltage of the server board card is an enable voltage under a critical state wherein the enable voltage is the maximum and the enable voltage does not drop to an uncontrollable interval when the input voltage drops. Since the circuit in the VR chip in the server board card may cause the enable voltage to not drop to an uncontrollable interval when the input voltage drops, the problem in which the output voltage of the VR chip is not monotonic during the timing test of the VR chip is prevented. Moreover, the circuit in the VR chip in the server board card may ensure that the enable voltage is the maximum on the basis that the enable voltage does not drop to an uncontrollable interval when the input voltage drops. Therefore, the problem in which the VR chip operates abnormally because the voltage is too low may also be prevented.

Inventors:
GAO YU (CN)
Application Number:
CN2019/089279
Publication Date:
March 05, 2020
Filing Date:
May 30, 2019
Export Citation:
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Assignee:
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD (CN)
International Classes:
G01R31/28
Foreign References:
CN108173422A2018-06-15
CN109188242A2019-01-11
CN108549009A2018-09-18
CN108646173A2018-10-12
CN102411395A2012-04-11
CN203798978U2014-08-27
TW201027314A2010-07-16
Other References:
ZHANG LIPING ET AL: "Design of a minimum system development board based on the EP1C3T144", JOURNAL OF WUHAN UNIVERSITY OF SCIENCE AND TECHNOLOGY ( NATURAL SCIENCE EDITION), vol. 3, no. 30, 30 June 2007 (2007-06-30), pages 293 - 295, 307, XP055696773
Attorney, Agent or Firm:
UNITALEN ATTORNEYS AT LAW (CN)
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