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Patent Searching and Data


Title:
TRACK AND HOLD CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2021/205531
Kind Code:
A1
Abstract:
Bias adjustment circuits (1_(2k-1), 1_2k) (where k is an integer from 1 to N, and N is an integer of 2 or more) adjust a DC bias voltage of at least one clock signal from between clock signals (ckp, ckn) such that a duty ratio, which is the ratio of a period in which a clock signal (ckp_k) is High with respect to a clock signal (ckn_k) to a period in which the clock signal (ckp_k) is Low with respect to the clock signal (ckn_k), becomes (2N-2k+1):(2k-1). Sampling circuits (1_1 to 1_2N) switch a mode between a track mode in which an output signal follows an input signal (da) and a hold mode in which a value of the input signal (da) at a timing when the mode is switched from the track mode to the hold mode is held and output, in accordance with clock signals output from bias adjustment circuits (2_1 to 2_2N).

Inventors:
TERAO NAOKI (JP)
NAGATANI MUNEHIKO (JP)
NOSAKA HIDEYUKI (JP)
Application Number:
PCT/JP2020/015636
Publication Date:
October 14, 2021
Filing Date:
April 07, 2020
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
H03M1/12
Attorney, Agent or Firm:
YAMAKAWA, Shigeki et al. (JP)
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