TRAINING FOR CHIP SELECT SIGNAL READ OPERATIONS BY MEMORY DEVICES

Title:

TRAINING FOR CHIP SELECT SIGNAL READ OPERATIONS BY MEMORY DEVICES

Document Type and Number:

WIPO Patent Application WO/2020/237410

Kind Code:

A1

Abstract:

A reference voltage value and a chip select (CS) signal timing delay provided to memory devices can be determined based on samples of the CS signal received by the memory devices. The CS signal can be provided to the memory devices with varying time delays and for various reference voltages. Various samples of the CS signal from the memory devices can indicate different times for rising and falling edges of the CS signal. A composite signal eye can be generated by the latest occurring rising edge and the earliest occurring falling edge of the CS signal. The reference voltage value and timing delay can be chosen based on the composite signal eye width that is the closest to a reference eye width.

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Inventors:

WU ZHENGLONG (CN)
MORRIS TONIA G (US)
JUE CHRISTINA (US)
BECERRA PEREZ DANIEL (MX)
ELLIS DAVID G (US)

Application Number:

PCT/CN2019/088263

Publication Date:

December 03, 2020

Filing Date:

May 24, 2019

Export Citation:

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Assignee:

INTEL CORP (US)
WU ZHENGLONG (CN)
MORRIS TONIA G (US)
JUE CHRISTINA (US)
BECERRA PEREZ DANIEL (MX)
ELLIS DAVID G (US)

International Classes:

G11C7/08

Foreign References:

US20120257459A1	2012-10-11
US20090244997A1	2009-10-01
US7068064B1	2006-06-27
US20120257459A1	2012-10-11

Other References: