TECHNICAL FIELD The present invention relates to the field of transistors, and in particular metal-oxide semiconductor field-effect transistors (MOFSETs).

BACKGROUND A transistor can be thought of as an electrical switch, and is typically used to amplify, switch or control an electrical signal. Transistors have at least three terminals, with two arranged to allow current to flow between them, and the third arranged to control the current flow between the other two terminals. When no voltage is applied to the third terminal, the resistance of the transistor is sufficiently high so as to substantially prevent current flow between the other two terminals. When a voltage is applied to the third terminal, the resistance of the transistor is lowered, allowing current to flow through the transistor. In a field-effect transistor (FET), the three terminals are called the source, drain and gate, and the current flow between the source and drain is controlled by applying voltage to the gate.

Figure 1 shows a cross section (not to scale) through a typical nMOFSET (NMOS) 1 , which is a common type of FET. The NMOS 1 has a gate 2, source 3, drain 4 (which are arranged in a lengthwise direction of the transistor), and a substrate 5. Transistors having the gate, source and drain arranged in a lengthwise direction are commonly known as lateral transistors. In this example, the substrate 5 is a silicon structure and has a p doped region 7, forming a p-well (shown as a dotted outline in the substrate 5). Two n doped regions 6, which correspond to the position of the source 3 and the drain 4 are formed in the p-well 7. Boron is typically used as the dopant for the p doped region. The gate 2 is isolated from the substrate 5 by an insulating layer 8. This insulating layer may be Si0 ₂ . In this arrangement, a depletion zone is formed between the pn boundaries (i.e. between the n doped region 6 and the p doped region 7), where there are a reduced number of free charge carriers. Therefore, in the off-state of the transistor, voltage applied across the source 3 and drain 4 will not produce any significant current flow through the substrate 7 due to the depletion zone. In Figure 2, the gate 2 is positively charged due to a voltage V _G s (where V _G s is the voltage between the gate and source) being applied to the gate 2. The positive charge creates an electric field (not shown) which extends into the substrate 5, repelling positive holes away from the gate and drawing electrons towards the gate 2. This effectively turns the upper part of the p doped substrate into an n doped region, creating a conductive channel 9 between the source 3 and the drain 4. If a voltage is now applied across the source 3 and drain 4, a current can flow through the conductive channel 9. The minimum voltage that is needed to be applied to the gate 2 in order that an appreciable current may flow between the source 3 and drain 4 is known as the threshold voltage, V _T .

Shallow Trench Isolation (STI) is a technique used in integrated circuits and which helps to prevent current leakage. Typically, channels of Si0 ₂ are formed in the silicon based substrate and act to separate different regions of the device. However, problems can arise when using Si0 ₂ in an NMOS where boron was used as a dopant. During high temperature processes, some of the boron tends to diffuse into the Si0 ₂ in a process known as boron segregation. This reduces the boron concentration in regions of the p-well that border the Si0 ₂ . Figure 3 shows a top view of a layout of the NMOS 1 and Figure 4 shows a cross section through the NMOS 1 , along the line a shown in Figure 3. Also shown in Figure 4 is a cross section through two STI trenches

10 (not shown in Figure 3). Regions 1 1 in the p doped region 7 which border the trenches 10 have a lower boron concentration than other parts of the p doped region 7 due to boron segregation. Figure 5 shows a top view of the NMOS 1 , with the regions

1 1 having the lower boron concentration highlighted.

As the p doping is effectively lower in these regions 1 1 than in the rest of the p doped region 7, a lower threshold voltage, V _PT , is required to "turn on" these parts of the transistor than the rest of the transistor. This leads to a situation where there are two "parasitic edge transistors" 12, 13 along the boundary region 1 1 , which turn on before the "main transistor" 14 in the centre, as shown in Figure 6. This leads to a "double hump" phenomenon which can be seen in the V _G S-IDS Curve shown in Figure 7. The VQS-I DS curve of Figure 7 is a composite curve showing the contribution from both the main transistor 14 and the parasitic transistors 12, 13. The dotted line shows how the curve would look without the contribution from the parasitic transistors. SUMMARY

According to a first aspect of the present invention, there is provided a transistor comprising a source, gate and a drain, the source, gate and drain being arranged next to each other in a lengthwise direction of the transistor. The gate comprises a layer of an at least partially conductive material, wherein said layer has a recess such that, at a lengthwise position within the recess, the width of said layer is smaller than at a lengthwise position outside the recess. As an option, at the lengthwise position within the recess, the width of said layer may be smaller than the width of at least one of the source and the drain.

As an option, the transistor may comprise an active layer in a substrate, the source and drain being formed in said active layer wherein the active layer has a width and wherein, at a lengthwise position within the recess, the width of said layer may be smaller than the width of the active layer. The width of the active layer may be defined by one or more insulating trenches.

A portion of the active layer may be doped with boron. Optionally, a further portion of the active layer may comprise a non-doped region, the non-doped region being arranged substantially below the recess.

As an option, the transistor may further comprise a salicide blocking layer. The salicide blocking layer may be formed substantially in the recess, and may extend over an upper portion of the gate.

The layer of the gate may comprise a polysilicon or a metal.

According to a second aspect of the present invention, there is provided a lateral transistor comprising a source, gate and a drain, the source, gate and drain being arranged next to each other in a lengthwise direction of the transistor. The gate comprises a layer of an at least partially conductive material, said layer being implanted with ions in an implanted region, wherein the implanted region has a recess such that, at a lengthwise position within the recess, the width of the implanted region is smaller than at a lengthwise position outside the recess. Optionally, said layer of the gate may be a polysilicon or a metal.

According to a third aspect of the present invention, there is provided a lateral transistor comprising a source, gate and a drain, the source, gate and drain being arranged next to each other in a lengthwise direction of the transistor, wherein the gate comprises a conductive portion and a non-conductive potion, the non-conductive portion being arranged such that, at a lengthwise position where the non-conductive portion is located, the width of the conductive portion is smaller than at a lengthwise position where the non-conductive portion is not located.

According to a fourth aspect of the present invention, there is provided a transistor comprising a substrate and a gate, wherein the gate is arranged over the substrate. The substrate comprises an active layer comprising a doped semiconductor material. The gate comprising a recess, where the recess is arranged so as to reduce an electric field in a portion of the substrate substantially below an area defined by the recess, when a voltage is applied to the gate, relative to a portion of the substrate located substantially under the gate. Optionally, the active layer of the substrate may comprise a portion that is p-doped with a p-type dopant. The p-type dopant may comprise boron.

Optionally, the transistor may further comprise a source and a drain. The source, drain and gate may be arranged next to each other in a lengthwise direction of the transistor.

Optionally, the recess may be formed such that at the lengthwise position within the recess, the width of the gate is shorter than at a lengthwise position outside the recess.

Optionally, the transistor may further comprise an insulating trench. The insulating trench may comprise an oxide, and be arranged such that at least a part of the trench runs substantially parallel to the lengthwise direction. The trench may form a boundary with the p-doped region, and the boundary may be arranged such that at least a part of the boundary runs substantially parallel to the lengthwise direction. The recess may be arranged such that a portion of the boundary running substantially parallel to the lengthwise direction is located under the recess. Optionally, the active layer may comprise a non-doped region, the non-doped region being arranged substantially below the recess. Optionally, the transistor may further comprise a salicide blocking layer. The salicide blocking layer may be formed substantially in the recess, and may extend over an upper portion of the gate.

Optionally, the gate may comprise two or more recesses.

The transistor may be an NMOS, and/or may be a lateral transistor. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates a cross section through a transistor in an off state;

Figure 2 illustrates a cross section through the transistor of Figure 1 in an active state;

Figure 3 illustrates a plan view of a transistor;

Figure 4 illustrates a cross section through the transistor of Figure 3;

Figure 5 illustrates a plan view of the transistor of Figure 3 highlighting areas which are susceptible to boron segregation;

Figure 6 illustrates a schematic view of the transistor of Figure 5;

Figure 7 illustrates a plot of a typical V _G S-IDS Curve;

Figure 8 illustrates a plan view of a transistor;

Figure 9 illustrates a plan view of a transistor according to an embodiment of the invention;

Figure 10a illustrates a plan view of a transistor according to a second embodiment of the invention;

Figure 10b illustrates a doped region of Figure 10a;

Figure 1 1 illustrates a plan view of a transistor according to a third embodiment of the invention;

Figure 12a illustrates a cross section through the transistor of Figure 1 1 ;

Figure 12b illustrates a further cross section through the transistor of Figure 1 1 ; and

Figure 12c illustrates a further cross section through the transistor of Figure 1 1 . DETAILED DESCRIPTION

With reference to Figures 8 to 12, there will now be described an improved NMOS transistor that addresses the aforementioned problems.

Figure 8 (included here to help with the understanding of embodiments of the present invention) shows a conventional layout of a typical lateral NMOS, and shows the gate 2 and the gate's active layer 15 under which part of the conductive channel 9 will form. The active layer borders Si0 ₂ trenches along the interfaces 15a and 15b. STI regions arranged between the source and the drain are typically used for NMOSs that may be more suited in a high voltage circuit. The double headed arrow in Figure 8 shows a primary axis in a lengthwise direction of the lateral NMOS.

Figure 9 shows a gate 16 according to an embodiment of the invention, where the gate 16 has been formed or reshaped so as to comprise two recesses 17. The gate may be formed ab initio with the recesses as shown, or it may be formed in a different shape first (such as a rectangle) and then etched or cut etc. so as to result in the shape as shown. The recesses 17 are formed so as to run substantially along the primary axis of the NMOS, and are arranged such that the width of the gate between the recesses, indicated by W in Figure 9, is smaller than the width of the gate at a lengthwise position outside the recesses. The width of the gate between the recesses, W, is also smaller than the width of the active layer 15, where the width of the active layer equals 2B +W.

As an example, the dimensions of the reshaped gate 16 may be such that: A is greater than or equal to 10nm, B is greater than or equal to 20nm, C is greater than or equal to 20nm, Lg is greater than or equal to 40nm (where Lg = 2A +C), and W is greater than or equal to 40nm. The skilled person will understand that these values are not limiting, and will be aware that the lithography tools available at the time will determine the lower limit. In one particular example, A is approximately 1 μιτι, B is approximately 0.5 μιη and C is equal to Lg - 2A, where Lg is the length of the gate 16. In this example Lg may be around 2.9 μιτι, and the width, W, of the gate may be around 2.9 μιη as well. While the recesses are shown as being formed symmetrically, and midway in relation to the gate, it will be appreciated by the skilled person that the recesses may be formed so as to be closer to the drain than the source, or vice versa. The length B is defined as the distance to the innermost portion of the recess from the STI trench/p-doped boundary 15a. B is not the total depth of the recess of the gate, and so it is possible that, when viewed from above, a portion of the STI trench/p-doped boundary 15a falls within one of the recess 17 of the gate 12. When a positive charge is placed on the gate 16 an electric field permeates into the substrate 5 below the gate 16. However, regions of substrate located (in vertical projection) below the recesses 17 will be subjected to a reduced electric field when compared with regions of the substrate located under the gate 16, since the recess does not hold any charge. Therefore, by arranging the areas defined by the recesses 17 to extend over the regions 1 1 where there is a lower concentration of boron, a reduced electric field penetrates the regions 11 . The reduced electric field in the regions 1 1 means that a greater value of V _PT is required in order to turn the parasitic transistors 12, 13 on, to the extent that they can be considered to form at all. Therefore, by reducing the electric field in these regions 1 1 , the reshaped gate 16 helps to prevent the parasitic edge transistors 12, 13 from forming in regions 1 1 before the main transistor 14 has turned on, thus substantially avoiding the double hump phenomenon.

To further reduce the chance of the parasitic edge transistors 12, 13 forming, the regions of the substrate 5 below the recess may not be subjected to doping. That is, the area of the substrate 5 that is doped with boron may be shaped so as to resemble the shape of the gate 12, as shown in Figure 10b, leaving a pair of regions 18, 19 where no doping has occurred. This further prevents a conductive channel from forming at a voltage below the threshold voltage. Figure 10a shows an overlay of the source, drain and gate over the substrate 5 of Figure 10b.

As a further option, a Salicide Blocking Layer (SBLK) 20, 21 may be applied to the NMOS. For example, the SBLK may be applied in the recesses of the gate, such that the exposed sides of gate and the exposed substrate immediately below the recesses (i.e. the faces defining the recesses) are covered by the SBLK layer. The SBLK layer may extend over a part of the (top surface of the) gate. This is shown in Figure 1 1 , which shows a top view of the NMOS 1 , and Figures 12 a, b and c. In Figure 1 1 , the three lines, a, b and c, correspond to the three cross sections shown in Figure 12. As can be seen in cross section a of Figure 12, the recesses 17 of the gate 12 ensure that the gate does not extend over the regions 1 1 , where there is a reduced boron concentration. Furthermore, the SBLK 21 is formed in the recesses 17.

The SBLK helps to prevent portions of the active layer of the substrate from becoming salicide. When portions of the active layer become salicide, they can become more conductive, which can lead to parasitic edge transistors being formed through the salicide layer, leading again to the double hump phenomenon.

Figures 12b and 12c show STI regions 10a arranged between the source and the drain. This arrangement is typically used for NMOSs that may be more suited in a high voltage circuit. In NMOSs that are used in low voltage circuits, regions 10a may not be necessary.

Although the invention has been described in terms of embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. For example, while a lateral transistor has been described, the invention is not limited to a lateral transistor. For example, gate 16 may be used with a quasi-vertical DMOS. While a recess in the gate has been described, the same effect can be achieved by providing a non-conductive portion in the gate in place of the recess. For example, while an NMOS has been described, and specifically an NMOS using boron as a p dopant, it will be understood that the invention may be applied to other transistors having different dopants.

Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.