RELATED APPLICATIONS

[0001] This application claims the benefit of provisional patent application number 61/594,851 to Kalb et al., filed February 3, 2012.

BACKGROUND OF THE INVENTION

Field of the Invention

[0002] This invention relates generally to voltage reference circuits, and more particularly to voltage reference circuits having very low noise specifications.

DESCRIPTION OF THE RELATED ART

[0003] One type of voltage reference circuit having a low or zero temperature coefficient (TC) is the bandgap voltage reference. The low TC is achieved by generating a voltage having a positive TC (PTAT) and summing it with a voltage having a negative TC (CTAT) to create a reference voltage with a first-order zero TC. One conventional method of generating a bandgap reference voltage is shown in FIG. 1. An amplifier 10 provides equal currents to bipolar junction transistors (BJTs) Ql and Q2; however, the emitter areas of Ql and Q2 are intentionally made different, such that the base-emitter voltages for the two transistors are different. This difference, AV _B E, is a PTAT voltage which appears across resistor R2. It is summed with the base-emitter voltage (VBE) of Ql , which is a CTAT voltage, to generate reference voltage V _REF , which is given by:

V ~^~ VpTAT ⁼ + K(V _T ln(N)+ V _QS ) ,

where K = Ri/R ₂ , VT is the thermal voltage, N is the ratio of the emitter areas and Vos is the offset voltage of amplifier 10.

[0004] When so arranged, the noise v _{n PTAT} generated in the creation of the PTAT voltage is given by:

[0005] Another bandgap voltage reference approach, described in U.S. Patent No. 8,228,052 to Marinca, is illustrated in FIG. 2. Explicit amplifiers are not used with this AV _B E voltage generation method in favor of stacked, independent AV _B E cells. Here, the output of the voltage reference is given by:

V R,EF AV _BEl + AV _BE2 + - - - + AV _BEK BE

The noise of each AV _B E cell is uncorrelated with the others; thus, the noise contributions to the PTAT hion as given by:

^V n,PTAT

Though this approach generates less noise that the conventional approach shown in FIG. 1 , the noise level may still be unacceptably high for certain implementations.

SUMMARY OF THE INVENTION

[0006] A voltage reference circuit is presented which is capable of providing a noise figure lower than those associated with the prior art methods described above.

[0007] The present voltage reference circuit comprises a plurality of AVBE cells, each comprising four bipolar junction transistors (BJTs) connected in a cross-quad configuration and arranged to generate a AV _B E voltage. The plurality of AVBE cells are stacked such that their AVBE voltages are summed. A last stage is coupled to the summed AVBE voltages; the last stage is arranged to generate a V _B E voltage which is summed with the AVBE voltages to provide a reference voltage. This arrangement serves to cancel out the first-order noise and mismatch associated with the two current sources present in each AV _BE cell, such that the present voltage reference circuit provides ultra- low 1/f noise in the bandgap voltage output.

[0008] These and other features, aspects, and advantages of the present invention will become better understood with reference to the following description and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 is a schematic diagram of a known bandgap voltage reference.

[0010] FIG. 2 is a block diagram of another known bandgap voltage reference.

[0011] FIG. 3 is a schematic diagram of a AVBE cell.

[0012] FIG. 4 is a plot of the constituent noise components of a AVBE cell such as that shown in

FIG. 3.

[0013] FIG. 5 is a schematic diagram of a quad AV _B E cell. [0014] FIG. 6 is a plot of the constituent noise components of a quad AV _B E cell such as that shown in FIG. 5.

[0015] FIG. 7 is a schematic diagram of a cross-quad AVBE cell.

[0016] FIG. 8 is a plot comparing the noise of a cross-quad AV _B E with that of quad AV _B E cell and a basic AV _BE cell.

[0017] FIG. 9 is a plot of the constituent noise components of a cross-quad AVBE cell such as that shown in FIG. 7.

[0018] FIG. 10 is a schematic diagram of one possible embodiment of an ultra-low noise voltage reference circuit in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0019] One possible implementation of a cell capable of generating a AV _B E voltage is shown in FIG. 3 (Marinca, ibid.). BJTs Qj and Q ₂ are arranged such that the emitter area of Q ₂ is N times that of Qi, and FETs MP] and MP ₂ are arranged to provide equal currents Ii and I ₂ to Qj and Q ₂ , respectively. An NMOS FET MN _\ functions as a resistance across which the cell's output voltage (ΔΥΒΕ) appears, given by:

wherein V _T is the thermal voltage, lc\ and l t are the collector currents of Ql and Q2, respectively, and /si and ½ are the saturation currents of Ql and Q2, respectively. Thus, the AV _B E voltage is purely dependent on the emitter area ratio, nominally /V, of NPNs Qi and Q ₂ , the matching of currents Ii and I ₂ (generated by the PMOS current mirror transistors MP ₂ and MP ₃ ), and the matching of Qj and Q ₂ . NMOS FET MNi acts as a variable resistor, which is tuned by the circuit to sink the current necessary to keep the cell in an equilibrium state. Multiple AVBE cells of this sort could be "stacked" - i.e., connected such that their individual AVBE voltages are summed - and then coupled to a stage which adds a V _BE voltage to the summed AV _B E voltages to provide a voltage reference circuit. An NMOS FET MN ₂ is preferably connected as shown and used to drive the bases of Q 1 and Q2, though other means might also be used; a BJT might also be used for this purpose.

[0020] The constituent noise components of a AVBE cell such as that shown in FIG. 3, designed on a standard CMOS process, are shown in FIG. 4. At frequencies below lOHz, the 1/f noise of the PMOS FETs MP ₂ and MP ₃ dominates. Above 10Hz, the overall AV _BE noise is split approximately equally between the PMOS current mirror thermal noise and the shot noise of NPNs Qi and Q ₂ . Note that even if MP ₂ and MP ₃ match perfectly, the small-signal collector currents of Qi and Q ₂ are not equal because MP ₂ and MP ₃ each has its own uncorrected noise; this differential noise results in noise in the AV _B E output. The 1/f noise is more pronounced in MOS devices than bipolar devices; thus, the contribution of the PMOS noise to the total noise is dominant at frequencies below 10Hz in FIG. 4.

[0021] One could theoretically improve the noise performance of the AV _BE cell discussed above by using two sets of two NPNs to create the AV _BE voltage. This approach, referred to herein as a

"quad AVBE cell" for its four NPNs, is shown in FIG. 5. Note that, as above, multiple quad AV _B E cells could be stacked and coupled to a stage which adds a V _B E voltage to the summed AV _BE voltages to provide a voltage reference circuit.

[0022] The output voltage AV _B E of this configuration is given by:

AV BE -V ^v BE,Q2 -V ^v BE.QA

V _r ln(N ² )= 2V ₇ . ln(N), assuming equal ?'s

[0023] In the quad AV _BE cell, the AV _BE voltage increases by a factor of 2, while the NPN shot noise contribution to the AV _B E voltage increases by a factor of 2 since the NPN shot noise generators are uncorrected. As a result, the quad AV _B E cell provides a signal-to-noise ratio (SNR) improvement of :

V((4/6)/( l/2)) = V(4/3) = - 1.15,

if the overall wideband AV _BE noise is split evenly between PMOS thermal noise and NPN shot noise.

[0024] As noted above, the quad cell increases AV _B E magnitude by a factor of 2, which corresponds with an increase in signal power by 4. However, the PMOS noise magnitude also doubles (it sees twice the gain in converting from current to voltage), so it increases in power by 4. The shot noise increases because of a doubling in the number of noise generators. There are twice as many noise generators, so the shot noise power goes up by 2. FIG. 6 depicts the constituent noise components of the quad AV _B E cell.

[0025] A closer look at the quad AV _BE cell reveals that Ii≠ I ₂ in a small-signal sense due to the uncorrected noise of the PMOS current mirrors MP and MP ₃ . The high-current-density pair Qi and Q ₃ sees Ii with its independent noise, while the low-current-density pair Q ₂ and Q ₄ sees I ₂ with its own independent noise. The uncorrelated nature of the PMOS noise sources leads to noise in the generation of the AVBE voltage with the quad AVBE cell. Thus, while the SNR of the quad AVBE cell is improved over the standard AVBE cell, the performance may still be unacceptable for some applications.

[0026] A voltage reference circuit capable of providing ultra-low noise performance is now described. The present voltage reference circuit employs a "cross-quad AVBE cell" that to first- order cancels out the noise and mismatch of the two current sources which provide currents Ii and I ₂ . Without the cross-quad connection, the current sources can be the dominant sources of noise and mismatch in the overall AV _B E output voltage. Here, however, the voltage reference provides ultra-low 1/f noise in the bandgap voltage output, making it suitable for demanding applications such as medical instrumentation. For example, one possible application is as an ultra-low-noise voltage reference for an electrocardiograph (ECG) medical application-specific standard product (ASSP).

[0027] A schematic of a preferred embodiment of the cross-quad AV _B E cell is shown in FIG. 7. The output of this arrangement is given by:

A V _BE = V _{BE Cn} + V _BEm - V _BE - V _BEiQ2 =

where / _S1 , / _C1 , l _S2 , l _C2 , / _S3 , / _C3 , / _S4 , and / _C4 are the saturation and collector currents of transistors Ql , Q2, Q3, and Q4, respectively.

Since 7c3 = Ii and 7c4 = h, it can be shown that:

, _ , βΛ ^β , , βΛ _! and

where, β , β ₂ , β _ζ and β _Λ are the current gains of transistors Ql , Q2, Q3, and Q4, respectively. Typically, transistors Ql and Q4 will have an emitter area, A, and transistors Q2 and Q4 will have an emitter area N*A. Then, the output is given by: C1 'C4

^BE — ^ ΒΕ,ΟΙ ⁺ ^ΒΕ,ΟΑ ^SE,03 ^BE,Q2 ~ ' ^Π

fC2 ^' 'C3

It should be noted that other scalings of the emitter areas are possible. As above, NMOS FET MNi is preferably employed as a resistance across which the cell's output voltage (AV _B E) appears, and NMOS FET MN ₂ is preferably connected as shown to drive the bases of Ql and Q2; note, however, that MN ₂ might alternatively be implemented with an NPN transistor, and that the functions provided by MNi and MN ₂ might alternatively be provided by other means.

[0028] In this configuration, the high-current-density pair Qi and Q ₃ and the low-current-density pair Q ₂ and Q ₄ each have one NPN with a collector current originating from Ii and one NPN with a collector current originating from I ₂ . The noise components introduced by MP ₂ and MP ₃ are forced to be correlated via the cross-quad configuration. Thus, the 1/f and wideband noise, and the mismatch of the PMOS current mirror transistors, are rejected to an amount limited only by the β of the NPNs used in the cross-quad configuration.

[0029] The last statement can be better appreciated by revisiting the Ici and Ic ₃ equations shown above, which indicate that currents Ici and Ic ₃ are not perfectly correlated due to finite β. Current Ic3 is purely a function of Ii, while Ici is a function of i! and I ₂ ; the relative contribution of I ₂ to Ici depends on β. The same condition applies to Ic ₂ and Ic ₄ . The sensitivity of the AVBE voltage to noise in the current sources can be calculated as the partial derivative of the AVBE voltage with respect to each current. For simplicity of calculation, the transistor current gains will be assumed to be equal to β and the calculation will be carried out at the nominal operating point 11=12=1.

T

It is clear that the sensitivities are inversely proportional to the current gain, β . The conclusion is that the PMOS current source noise suppression is limited by β, with greater suppression achieved when using fabrication processes that enable larger β.

[0030] A comparison of the noise of the cross-quad AV _B E cell with the quad and standard AV _B E cells is shown in FIG. 8. The 1/f noise of the cross-quad ΔΥΒΕ cell is 7x lower than that of the quad and standard AVBE cells (the β for the process was approximately 8), and the wideband noise is reduced by nearly 2x over the standard cell. FIG. 9 shows the constituent noise components of the cross-quad AVBE cell. Due to finite β as described earlier, there is still a 1/f noise component due to the PMOS current mirrors; however, the overall contribution of the PMOS current mirror noise is reduced because of the cross-quad AV _B E configuration.

[0031] Multiple cross-quad AVBE cells can be stacked together and then coupled to a last stage to create a first-order zero TC voltage reference with ultra-low noise; one possible embodiment is shown in FIG. 10. Two cross-quad AV _B E cells 20 and 22 are shown in FIG. 10, though more or fewer cross-quad AV _B E cells could be used as needed. The stacked cross-quad AV _BE cells are connected such that their individual AV _BE voltages are summed. In the exemplary embodiment shown, this is accomplished by connecting the AVBE voltage that appears across the resistance (MN1) in first cross-quad AVBE cell 20 to the circuit common point of the second cross-quad AV _B E cell in the stack, connecting the AV _BE voltage across the resistance (MN3) in second cross- quad AV _B E cell 22 to the circuit common point of the third cross-quad AVB _E cell in the stack (if present), and so on.

[0032] The AVBE voltage that appears across the resistance in the last cross-quad AVBE cell in the stack is connected to a last stage 24, which, in the exemplary embodiment shown, is nearly identical to the other cross-quad AV _BE cells. The output 26 (VREF) of the last stage is taken from the base of Qn and Qj ₂ such that the last stage contributes a cross-quad AV _BE voltage to the reference voltage output, along with two full V _B E voltages which provide the CTAT component of the voltage reference. The AVBE voltage provided by the last stage is given by:

where W is the thermal voltage and Ic9, ^cio, 7cu and Icn are the collector currents of Q9, Q10, Ql 1 and Q12, respectively. The voltage reference V _REF is then given by:

[0033] Note that the currents in the last stage are sourced by a mirror configuration (with MP7 diode-connected), instead of via two current sources as in the cross-quad AVBE cells. Also, rather than using an MOS FET as a resistance across which the cell's AVBE voltage appears as in the preferred embodiment of the cross-quad cell, here the stage current is set by a resistor Ri, which may be made variable to provide a trim mechanism for the TC. [0034] Most of the error in such circuits is due to the V _B E term. In theory, VBE intersects VGO (the bandgap voltage) at OK. The slope away from OK is determined by the sizing of the transistor providing the V _B E voltage and the current through it - which will vary for each transistor and each die. Prior art designs typically add a fraction of a V _BE voltage to a AV _BE voltage to obtain a zero TC. This means that the circuit adds K*VG0 at OK, and 0 at some unknown temperature; that trim scheme rotates the V _B E curve around the unknown temperature. The net result is that the "magic voltage" at which the bandgap voltage reference has zero TC changes from die to die. This makes trimming difficult, with both TC trim and gain trim mechanisms needed to provide acceptable performance.

[0035] The present trim scheme is to change the final stage current to affect a change in V _BE . This rotates the V _B E curve around VGO at OK, and allows for the size and current errors to be nulled out in the same mathematical way as they enter. The end result is that the reference voltage output has zero TC at the same magic voltage for each die (assuming VGO is not changing). This allows for a simple single point trim of the TC. Ideally, only a TC trim mechanism is needed, as the output will always be at the magic voltage. The output voltage of the reference is then divided down (via, for example, a voltage divider 26) to get a desired output voltage VOUT-

[0036] The cross-quad AV _BE cell is described and shown as consisting of two NPNs as the AV _B E generators, two PMOS devices as the current mirrors, and an NMOS device as the variable resistor. However, it is conceivable that one could use, for example, NMOS FETs in weak inversion in lieu of the NPNs, or PNPs instead of PMOS FETs for the current mirrors, or an NPN instead of an NMOS FET MN2. Any variant of the AV _BE cell could be improved by the cross- quad technique.

[0037] The embodiments of the invention described herein are exemplary and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.