Title:
VARIABLE FREQUENCY DIVIDER
Document Type and Number:
WIPO Patent Application WO/2017/158761
Kind Code:
A1
Abstract:
A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal outputted from a last-stage one of dual modulus frequency dividers, among a plurality of dual modulus frequency dividers (1-1, 1-2) in a first frequency divider group (1), to which a non-significant reset signal is being output from a reset circuit (6). In this way, when the frequency division ratio of the last-stage dual modulus frequency divider among effective dual modulus frequency dividers involved in a frequency division operation is one third, a normal frequency division operation can be achieved even if frequency division ratio setting data for reducing the number of effective dual modulus frequency dividers involved in the frequency division operation is given.
Inventors:
YANAGIHARA YUKI (JP)
TSUTSUMI KOJI (JP)
TSUTSUMI KOJI (JP)
Application Number:
PCT/JP2016/058335
Publication Date:
September 21, 2017
Filing Date:
March 16, 2016
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H03K23/64; H03L7/18
Foreign References:
| JP2015228569A | 2015-12-17 | |||
| JP2005510109A | 2005-04-14 | |||
| JP2009130760A | 2009-06-11 |
Other References:
See also references of EP 3419177A4
Attorney, Agent or Firm:
TAZAWA, Hideaki et al. (JP)
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