The present invention relates to voltage regulators, particularly low-dropout voltage regulators.

Low-dropout (or LDO) voltage regulators are linear DC voltage regulators that are capable of operating with very low input-output differential voltages. The advantages of such regulators with respect to other types of voltage regulators include having a lower minimum operating voltage, higher power efficiency and lower heat dissipation.

A conventional LDO voltage regulator consists of an error amplifier and a pass field- effect-transistor or "pass-FET". The error amplifier compares the output voltage (or a voltage derived therefrom) being generated by the LDO to a reference voltage and alters the conductivity of the pass-FET in order to drive the output voltage to the desired value.

Two important design parameters that must be considered when designing an LDO are the accuracy of the output voltage and the stability of the LDO. As with any circuit, the error amplifier of an LDO regulator has an associated transfer function which describes the frequency response of the circuit. The transfer function typically has a pole located at a particular frequency known as a corner frequency. Once the frequency of the lowest frequency or "dominant" pole has been reached, the gain of the circuit begins to decrease at a rate of 20 dB/decade (i.e. for every ten-fold increase in frequency, the gain drops by 20 dB). Any subsequent poles will then increase this rate by a further 20 dB/decade. Each pole will also introduce a 90 degree phase shift. Thus with two poles, the output is then in antiphase (i.e. 180 degrees out of phase) with the input, which can cause the circuit to be unstable. Thus in order for a circuit to be stable, the gain should drop to unity at a frequency lower than that of the second (or any subsequent) pole (i.e. the first "non-dominant" pole). The first pole arises from the capacitance of a (typically large) output capacitor and the output resistance of the pass-FET while the second pole arises from the gate capacitance of the pass-FET and the output resistance of the error amplifier. In some conventional LDO regulators a source follower stage is placed at the output of the error amplifier. Such a source follower stage drives the gate of the pass-FET and pushes the second pole to a relatively high frequency with a view to improving the stability of the LDO voltage regulator. However, with a large pass- FET the bias current required to drive the second pole up to such high frequencies increases dramatically, increasing the current consumption of the device as a whole.

When viewed from a first aspect the present invention provides a low-dropout voltage regulator arranged to convert an input voltage to an output voltage, the low- dropout voltage regulator comprising:

a pass field-effect-transistor having a first terminal connected to the input voltage and a second terminal arranged to produce the output voltage;

an error amplifier circuit portion arranged to produce an error signal proportional to a difference between a feedback voltage and a reference voltage, said feedback voltage being derived from the output voltage, wherein the error amplifier circuit portion is arranged to apply the error signal to the gate terminal of the pass field-effect-transistor via an error amplifier output terminal; and

a diode-connected field-effect-transistor connected to the error amplifier output terminal.

Thus it will be appreciated by those skilled in the art that, in accordance with embodiments of the present invention, there is provided a low-dropout (LDO) voltage regulator arranged such that the output impedance of the error amplifier circuit portion scales with the output current due to the diode-connected field-effect- transistor (FET) connected to its output. The scaling output current of the error amplifier drives the pole due to the output impedance of the error amplifier (and the gate capacitance of the pass-FET) to much higher frequencies than the unity gain frequency. This improves the overall stability of the LDO regulator across a wider range of load currents compared to conventional LDO voltage regulators. It will be readily understood by those skilled in the art that the term "diode- connected transistor" as used herein refers to a field-effect-transistor having its drain and gate terminals connected together so as to effectively form a two-terminal device from the three-terminal transistor. One characteristic of a diode-connected transistor is that it always operates in the saturation region. While it will be appreciated that there are a number of transistor technologies suitable for implementing the diode-connected field-effect-transistor, in at least some embodiments the diode-connected field-effect-transistor comprises a p-channel metal-oxide-semiconductor field-effect-transistor (pMOSFET), wherein the source terminal of the diode-connected field-effect-transistor is connected to the input voltage.

In at least some preferred embodiments the pass field-effect-transistor comprises a p-channel metal-oxide-semiconductor field-effect-transistor, wherein the source terminal of the pass field-effect-transistor is connected to the input voltage. In some such embodiments, the error amplifier is arranged such that the feedback voltage is applied to a non-inverting input of said error amplifier and the reference voltage is applied to an inverting input of said error amplifier. In such embodiments, the error amplifier is arranged to detect if the feedback voltage has fallen to the reference voltage and if so decrease its output voltage such that the conductivity of the pMOS pass-FET increases.

However, it will be appreciated that in alternative embodiments, the pass field- effect-transistor comprises an n-channel metal-oxide-semiconductor field-effect- transistor (nMOSFET), wherein the drain terminal of the pass field-effect-transistor is connected to the input voltage. In some such embodiments, the error amplifier is arranged such that the reference voltage is applied to a non-inverting input of said error amplifier and the feedback voltage is applied to an inverting input of said error amplifier. In such embodiments, the error amplifier is arranged to detect if the feedback voltage has fallen to the reference voltage and if so increase its output voltage such that the conductivity of the nMOS pass-FET increases.

While the output voltage could be compared to the reference voltage directly (i.e. by having the feedback voltage being the output voltage), in some embodiments the pass field-effect-transistor is connected in series with a potential divider circuit portion comprising at least first and second resistors, wherein the feedback voltage comprises the voltage at a node between said first and second resistors. Thus it will be appreciated that in such embodiments the potential divider circuit portion acts as a feedback for the error amplifier. The feedback voltage taken from this node will be proportional to the output voltage and will depend on the ratio between the resistance of the first resistor and the resistance of the second resistor. While the resistance of these resistors may be fixed, in some embodiments the potential divider circuit has an adjustable resistance ratio. It will be understood by those skilled in the art that such an adjustable resistance ratio (i.e. the ratio between the resistance of the first resistor and the resistance of the second resistor) may be achieved by having one or both of the resistors be variable. This may be achieved using a physically variable resistor (e.g. a potentiometer), however in practice this is more readily achieved by using an array of fixed resistors that can be "switched in and out", e.g. using a control signal.

In some embodiments, the error amplifier comprises:

a differential pair circuit portion comprising first and second differential field- effect-transistors;

a bias current circuit portion connected to the source terminals of said first and second differential field-effect-transistors arranged to provide a bias current thereto; and

a current mirror load connected to the drain terminals of said first and second differential field-effect-transistors. In some such embodiments, the current mirror load comprises first and second mirror field-effect-transistors, wherein:

the drain terminal of the first mirror field-effect-transistor is connected to the drain terminal of the first differential field-effect-transistor;

the drain terminal of the second mirror field-effect-transistor is connected to the drain terminal of the second differential field-effect-transistor; and

the gate terminal of the first mirror field-effect-transistor is connected to the drain terminal of the first mirror field-effect-transistor and the gate terminal of the second mirror field-effect-transistor. ln some embodiments, the bias current circuit portion comprises a current source connected between the source terminals of the first and second differential field- effect-transistors and ground. Such a current source provides a constant, static bias current to the LDO voltage regulator.

While providing the LDO voltage regulator with a constant bias current is sufficient, the Applicant has appreciated that this is not necessarily the best way of biasing the regulator. In some potentially overlapping embodiments, the bias current circuit portion comprises an adaptive bias circuit portion arranged to increase the bias current in response to an increase in the error voltage.

In some such embodiments, the adaptive bias circuit portion comprises:

a scaling field-effect transistor having its gate terminal connected to the output of the error amplifier output terminal;

an adaptive bias current mirror circuit portion comprising first and second adaptive bias mirror field-effect-transistors, wherein:

the drain terminal of the first adaptive bias mirror field-effect-transistor is connected to the gate terminal of the first and second adaptive bias mirror field- effect-transistors and to the drain terminal of the scaling field-effect-transistor; and the drain terminal of the second adaptive bias mirror field-effect-transistor is connected to the source terminals of the first and second differential field-effect- transistors; and

the source terminal of the second adaptive bias mirror field-effect-transistor is connected to ground.

The Applicant has appreciated that scaling the output impedance of the error amplifier in response to the output current of the LDO voltage regulator is novel and inventive in its own right. Thus when viewed from a second aspect, the present invention provides a low-dropout voltage regulator arranged to convert an input voltage to an output voltage, the low-dropout voltage regulator comprising:

an error amplifier circuit portion arranged to produce an error signal proportional to a difference between a feedback voltage and a reference voltage, said feedback voltage being derived from the output voltage; and an impedance scaling circuit portion arranged to vary an output impedance of the error amplifier circuit portion in response to an output current of the low- dropout voltage regulator.

In a set of embodiments of this aspect of the invention the impedance scaling circuit portion comprises a diode-connected filed-effect-transistor connected to an output of the error amplifier circuit portion. However other ways of achieving this can be envisaged.

Certain embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

Fig. 1 shows a circuit diagram of a low-dropout voltage regulator in accordance with an embodiment of the present invention;

Fig. 2 shows a simulation of the voltages at various nodes within the regulator of Fig. 1 as a function of load current; and

Fig. 3 shows a comparative simulation of the transient step response of the regulator of Fig. 1 to a step in the load current.

Fig. 1 shows a low-dropout (LDO) voltage regulator 102 in accordance with an embodiment of the present invention. While it will be appreciated that the LDO voltage regulator 102 would typically be implemented as a single integrated circuit, it has been divided into several logical circuit portions for illustrative purposes only. The LDO voltage regulator 102 comprises: an error amplifier circuit portion 104; an adaptive bias circuit portion 106; an output circuit portion 108; and a variable output impedance circuit portion 1 10. Each of these circuit portions will be described in turn below.

The error amplifier circuit portion 104 is constructed as a "long tailed pair" and comprises a differential pair of n-channel metal-oxide-semiconductor field-effect- transistors (nMOSFETs) M0, M1 arranged such that their respective source terminals are connected together and are further connected to a current source 112. The current source 1 12 is also connected to ground. The error amplifier circuit portion 104 further comprises a current mirror load constructed from two p- channel metal-oxide-semiconductor field-effect-transistors (pMOSFETs) M2, M3. The respective gate terminals these two pMOSFETs M2, M3 are connected to the respective drain terminals of M1 and M2. The drain terminal of M3 is connected to the drain terminal of MO.

The source terminals of both M2 and M3 are connected to the input voltage 114. The gate terminals of the differential pair nMOSFETs MO, M1 are connected to a reference voltage V _ref and a feedback voltage respectively as will be described in further detail below. The error amplifier circuit portion 104 also comprises an output terminal 1 16 which is connected to the adaptive bias circuit portion 106 and the output circuit portion 108 as will also be described in further detail below.

The adaptive bias circuit portion 106 comprises a scaling pMOSFET M6 arranged such that its gate terminal is connected to the output terminal 1 16 of the error amplifier circuit portion 104. The adaptive bias circuit portion 106 further comprises a current mirror arrangement constructed from a first adaptive bias mirror nMOSFET M7 and a second adaptive bias mirror nMOSFET M8. The first adaptive bias current mirror nMOSFET M7 is arranged as a diode-connected transistor, i.e. its gate and drain terminals are connected together. The gate and drain terminals of M7 are further connected to the gate terminal of M8 and to the drain terminal of M6 while the source terminal of M7 is connected to ground. The source terminal of M8 is also connected to ground, however the drain terminal of M8 is connected to the source terminals of the differential pair transistors M0 and M1 in the error amplifier circuit portion 104.

While the current source 1 12 provides constant, static current to the error amplifier circuit portion 104, the adaptive bias circuit portion 106 provides an additional current to the error amplifier circuit portion 104 that depends on the voltage at the output terminal 1 16.

The output circuit portion 108 comprises a buffer nMOSFET M5 and an output drive pMOSFET MP. The buffer transistor M5 is arranged such that its drain terminal is connected to the input voltage 1 14 and its source terminal is connected to ground via a current source 118. The gate terminal of the buffer transistor M5 is connected to the output terminal 116 of the error amplifier circuit portion 104. The source terminal of the buffer transistor M5 is further connected to the gate terminal of the output drive transistor MP. The source terminal of the output drive transistor MP is connected to the input voltage 1 14 while its drain terminal is connected to ground via a load capacitor CL. The output voltage V _ou t of the LDO regulator 102 is taken from a regulator output terminal 120 at the drain of MOP. The feedback voltage ν¾ applied to the gate terminal of M1 is also taken from this regulator output terminal 120, however it will be appreciated that in practice a potential divider (not shown) could be connected between this regulator output terminal 120 and the gate terminal of M1.

The variable output impedance circuit portion 110 comprises a diode-connected pMOSFET M4 arranged such that its source terminal is connected to the input voltage 114 and its gate and drain terminals are connected to the output terminal 116 of the error amplifier circuit portion 104. As will be described in further detail below, it is this diode-connected transistor M4 that provides the error amplifier circuit portion 104 with an output resistance that varies with the load current l| _0a d-

Also shown in Fig. 1 are the illustrative labels that show where the poles of the system arise, i.e. a position corresponding to the respective positions where the output resistance and capacitance associated with the components of the LDO voltage regulator 102 that give rise to each of the poles can be observed. A first pole P _ota arising from the output resistance of the error amplifier circuit portion 104 and the gate capacitance of M5 is shown at the output terminal 116 of the error amplifier circuit portion 104. A second pole P _uf arising from the output resistance of the buffer transistor M5 and the gate capacitance of the output drive transistor MP is shown at the source terminal of the buffer transistor M5 and the gate terminal of the output drive transistor MP. Thirdly, a pole P _ou t arising from the output resistance of the output drive transistor MP and the load capacitor CL is shown at the regulator output terminal 120. It is this third pole P _ou t that is the dominant pole of the LDO regulator 102. By way of example only, if the LDO regulator 102 is to deliver 150 mA of current, the size of the output drive transistor MP needs to be relatively large e.g.

7.2 mm/400 nm. This results in a relatively large parasitic gate capacitance at the output drive transistor MP. The buffer transistor M5 helps to isolate the output of the error amplifier circuit portion 104 from the large gate capacitance of MP. This helps to provide a larger possible signal swing at the gate terminal of the output drive transistor MP.

In a conventional LDO voltage regulator, the output resistance of a source follower buffer such as the buffer transistor M5 is sufficiently low (1/g _m ) such that the pole P _Uf at the gate terminal of the output drive transistor MP is raised to a sufficiently high frequency in order to obtain stability of the voltage regulator. However, in this design the output drive transistor MP is so large that in order to move the pole P _Uf to such high frequencies, the buffer transistor M5 requires relatively high bias currents or its size must also be increased substantially. However by increasing the size of the buffer transistor M5, its gate capacitance would also increase pushing the pole P _ota at the output terminal 1 16 of the error amplifier circuit portion 104 to lower frequencies which may cause further instability. The Applicant has appreciated that the resistance in the bond wires connected to the output terminal 120 of the LDO voltage regulator 102 and the equivalent series resistance of the load capacitor CL cause a zero in the transfer function that increases the unity gain frequency of the LDO voltage regulator 102. It is known in the art per se to place the pole P _ota at the output of the error amplifier circuit portion 104 so as to cancel this zero, however since the gate capacitance of the output drive transistor MP is so large, it is difficult to push the pole P _uf to high frequencies and therefore the Applicant has appreciated that it is advantageous to place the pole P _uf such that it cancels with this zero instead. Thus instead of placing the pole P _bUf at a high frequency, the diode-connected transistor M4 is placed parallel to the output 116 of the error amplifier circuit portion 104 in order to reduce the output resistance of the error amplifier circuit portion 104. This pushes the pole P _ota at the output 116 of the error amplifier circuit portion 104 to much higher frequencies than the unity gain frequency. If the load current l| _0ad increases and the dominant pole P _ou t at the regulator output terminal 120 of the LDO voltage regulator 102 moves to higher frequencies, the diode- connected transistor M4 causes the output resistance of the error amplifier circuit portion 104 to decrease which in turn causes the pole P _ota to move up to a high frequency, improving the overall stability of the LDO voltage regulator 102. It will be understood that when the load current l| _0ad increases, the voltage at the gate terminal of the output drive transistor MP is pulled down towards ground which will also pull down the voltage at the gate terminal of the buffer transistor M5. As the voltage at the gate terminal of the buffer transistor M5 is equal to the voltage at the output terminal 116 of the error amplifier circuit portion 104, the voltage drop across the diode-connected transistor M4 will increase which makes it draw more current. This lead to an increased transconductance (g _m ). The output resistance of the error amplifier circuit portion 104 is dominated by the output resistance of the diode-connected transistor M4 which is equal to 1/g _m . Therefore by increasing the transconductance of the diode-connected transistor M4, this pole P _ou t will be pushed to a higher frequency.

The adaptive biasing circuit portion 106 provides an increase in the

transconductance of the differential pair of transistors M0, M1 and thereby increases the gain of the error amplifier circuit portion 104 in order to compensate for some of the loss gain caused by the decreased output impedance at higher load current l| _0ad .

Fig. 2 shows a simulation of the voltages at various nodes within the regulator of Fig. 1 as a function of load current l| _0ad . It will be appreciated by those skilled in the art that the values of the voltages and currents shown in the simulation results are merely exemplary. It can be seen from Fig. 2 that as the load current l| _0ad increases, the current l _M4 through the diode-connected transistor M4 also increases (note the negative scale on the current-current plot). This increases the

transconductance g _m of the diode-connected transistor M4 which in turn lowers the output resistance of the error amplifier circuit portion 104.

It will be seen that an increase in the load current I i _oad also causes the voltage Viie at the node 1 16 to decrease. As the gate voltage V _M PGATE of the output drive transistor MP tracks the voltage V ₁₁₆ at the node 1 16, it decreases at the same time. The output voltage V _ou t decreases linearly in response to an increase in the load current I i _oad . However, it can be seen that there is a non-linearity in Viie, VMPGATE and l _M4 when l| _0ad is approximately 3 mA. When l| _0ad is 0 mA, the output drive transistor MP is nearly off and is operating quite far into the weak inversion region. As l| _0ad increases, the output drive transistor MP moves into the strong inversion operating region. This transition from weak to strong inversion causes the sudden change in V ₁₁₆ , V _M PGATE and l _M4 when l| _0ad is approximately 3 mA. The abrupt change shown in Fig. 2 is due to limitations of the simulation software used to produce the plots, and in reality (or with higher simulation accuracy) the transition is typically more smooth. In the weak inversion operating region, the voltage- current relationship is exponential, while in strong inversion it is quadratic.

Fig. 3 shows a comparative simulation of the transient step response of the regulator of Fig. 1 to a step in the load current l| _0ad - It will be appreciated by those skilled in the art that the values of the voltages and currents shown in the simulation results are merely exemplary. More specifically, Fig. 3 shows a comparison of the transient responses of the output voltage V _ou t and voltage V ₁₁₆ at the node 116 typical of the voltage regulator 102 of Fig. 1 when compared to the transient responses of the corresponding voltages V _ou t* and V ₁₁₆ * typical of a conventional voltage regulator.

It can be seen in Fig. 3 that the load current l| _0ad steps up from 0 mA to 150 mA in a 10 ms step. Due to the diode-connected transistor M4 within the variable output impedance circuit portion 1 10 of the voltage regulator 102, the voltage V ₁₁₆ at the node 116 undergoes a much reduced drop compared to the voltage V ₁₁₆ * in a conventional regulator. The voltage V ₁₁₆ at the node 1 16 also remains smooth throughout the transient response, whereas "ringing" is typically observed in the voltage V ₁₁₆ * of a conventional regulator. This ringing is then also present at the output voltage V _ou t* of such a conventional regulator. Such ringing is indicative of unstable operation due to the low phase margin associated with conventional regulators. It can also be seen that the output voltage V _ou t and voltage V ₁₁₆ at the node 116 reach their final values (i.e. are stable) earlier than those V _ou t*, V ₁₁₆ * of a conventional regulator. Thus it will be seen that embodiments of the present invention provide an improved low-dropout voltage regulator arranged to vary the output impedance of the error amplifier in response to changes in the load current. It will be appreciated by those skilled in the art that the embodiments described above are merely exemplary and are not limiting on the scope of the invention.